2 * PPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 //#define DO_SINGLE_STEP
31 //#define PPC_DEBUG_DISAS
34 #define DEF(s, n, copy_size) INDEX_op_ ## s,
40 static uint16_t *gen_opc_ptr;
41 static uint32_t *gen_opparam_ptr;
45 #define GEN8(func, NAME) \
46 static GenOpFunc *NAME ## _table [8] = { \
47 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
48 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
50 static inline void func(int n) \
52 NAME ## _table[n](); \
55 #define GEN16(func, NAME) \
56 static GenOpFunc *NAME ## _table [16] = { \
57 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
58 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
59 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
60 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
62 static inline void func(int n) \
64 NAME ## _table[n](); \
67 #define GEN32(func, NAME) \
68 static GenOpFunc *NAME ## _table [32] = { \
69 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
72 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
73 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
74 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
75 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
76 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
78 static inline void func(int n) \
80 NAME ## _table[n](); \
83 /* Condition register moves */
84 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
85 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
86 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
87 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
89 /* Floating point condition and status register moves */
90 GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
91 GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
92 GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
93 static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
94 &gen_op_store_T0_fpscri_fpscr0,
95 &gen_op_store_T0_fpscri_fpscr1,
96 &gen_op_store_T0_fpscri_fpscr2,
97 &gen_op_store_T0_fpscri_fpscr3,
98 &gen_op_store_T0_fpscri_fpscr4,
99 &gen_op_store_T0_fpscri_fpscr5,
100 &gen_op_store_T0_fpscri_fpscr6,
101 &gen_op_store_T0_fpscri_fpscr7,
103 static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
105 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
108 /* Segment register moves */
109 GEN16(gen_op_load_sr, gen_op_load_sr);
110 GEN16(gen_op_store_sr, gen_op_store_sr);
112 /* General purpose registers moves */
113 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
114 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
115 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
117 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
118 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
119 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
121 /* floating point registers moves */
122 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
123 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
124 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
125 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
126 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
127 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
129 static uint8_t spr_access[1024 / 2];
131 /* internal defines */
132 typedef struct DisasContext {
133 struct TranslationBlock *tb;
138 #if !defined(CONFIG_USER_ONLY)
141 /* Routine used to access memory */
145 typedef struct opc_handler_t {
148 /* instruction type */
151 void (*handler)(DisasContext *ctx);
154 #define RET_EXCP(ctx, excp, error) \
156 if ((ctx)->exception == EXCP_NONE) { \
157 gen_op_update_nip((ctx)->nip); \
159 gen_op_raise_exception_err((excp), (error)); \
160 ctx->exception = (excp); \
163 #define RET_INVAL(ctx) \
164 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
166 #define RET_PRIVOPC(ctx) \
167 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
169 #define RET_PRIVREG(ctx) \
170 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
172 #define RET_MTMSR(ctx) \
173 RET_EXCP((ctx), EXCP_MTMSR, 0)
175 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
176 static void gen_##name (DisasContext *ctx); \
177 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
178 static void gen_##name (DisasContext *ctx)
180 typedef struct opcode_t {
181 unsigned char opc1, opc2, opc3;
182 opc_handler_t handler;
185 /*** Instruction decoding ***/
186 #define EXTRACT_HELPER(name, shift, nb) \
187 static inline uint32_t name (uint32_t opcode) \
189 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
192 #define EXTRACT_SHELPER(name, shift, nb) \
193 static inline int32_t name (uint32_t opcode) \
195 return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \
199 EXTRACT_HELPER(opc1, 26, 6);
201 EXTRACT_HELPER(opc2, 1, 5);
203 EXTRACT_HELPER(opc3, 6, 5);
204 /* Update Cr0 flags */
205 EXTRACT_HELPER(Rc, 0, 1);
207 EXTRACT_HELPER(rD, 21, 5);
209 EXTRACT_HELPER(rS, 21, 5);
211 EXTRACT_HELPER(rA, 16, 5);
213 EXTRACT_HELPER(rB, 11, 5);
215 EXTRACT_HELPER(rC, 6, 5);
217 EXTRACT_HELPER(crfD, 23, 3);
218 EXTRACT_HELPER(crfS, 18, 3);
219 EXTRACT_HELPER(crbD, 21, 5);
220 EXTRACT_HELPER(crbA, 16, 5);
221 EXTRACT_HELPER(crbB, 11, 5);
223 EXTRACT_HELPER(SPR, 11, 10);
224 /*** Get constants ***/
225 EXTRACT_HELPER(IMM, 12, 8);
226 /* 16 bits signed immediate value */
227 EXTRACT_SHELPER(SIMM, 0, 16);
228 /* 16 bits unsigned immediate value */
229 EXTRACT_HELPER(UIMM, 0, 16);
231 EXTRACT_HELPER(NB, 11, 5);
233 EXTRACT_HELPER(SH, 11, 5);
235 EXTRACT_HELPER(MB, 6, 5);
237 EXTRACT_HELPER(ME, 1, 5);
239 EXTRACT_HELPER(TO, 21, 5);
241 EXTRACT_HELPER(CRM, 12, 8);
242 EXTRACT_HELPER(FM, 17, 8);
243 EXTRACT_HELPER(SR, 16, 4);
244 EXTRACT_HELPER(FPIMM, 20, 4);
246 /*** Jump target decoding ***/
248 EXTRACT_SHELPER(d, 0, 16);
249 /* Immediate address */
250 static inline uint32_t LI (uint32_t opcode)
252 return (opcode >> 0) & 0x03FFFFFC;
255 static inline uint32_t BD (uint32_t opcode)
257 return (opcode >> 0) & 0xFFFC;
260 EXTRACT_HELPER(BO, 21, 5);
261 EXTRACT_HELPER(BI, 16, 5);
262 /* Absolute/relative address */
263 EXTRACT_HELPER(AA, 1, 1);
265 EXTRACT_HELPER(LK, 0, 1);
267 /* Create a mask between <start> and <end> bits */
268 static inline uint32_t MASK (uint32_t start, uint32_t end)
272 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
279 #if defined(__APPLE__)
280 #define OPCODES_SECTION \
281 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) ))
283 #define OPCODES_SECTION \
284 __attribute__ ((section(".opcodes"), unused, aligned (8) ))
287 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
288 OPCODES_SECTION static opcode_t opc_##name = { \
295 .handler = &gen_##name, \
299 #define GEN_OPCODE_MARK(name) \
300 OPCODES_SECTION static opcode_t opc_##name = { \
305 .inval = 0x00000000, \
311 /* Start opcode list */
312 GEN_OPCODE_MARK(start);
314 /* Invalid instruction */
315 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
320 /* Special opcode to stop emulation */
321 GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
323 RET_EXCP(ctx, EXCP_HLT, 0);
326 /* Special opcode to call open-firmware */
327 GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON)
329 RET_EXCP(ctx, EXCP_OFCALL, 0);
332 /* Special opcode to call RTAS */
333 GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON)
335 printf("RTAS entry point !\n");
336 RET_EXCP(ctx, EXCP_RTASCALL, 0);
339 static opc_handler_t invalid_handler = {
342 .handler = gen_invalid,
345 /*** Integer arithmetic ***/
346 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
347 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
349 gen_op_load_gpr_T0(rA(ctx->opcode)); \
350 gen_op_load_gpr_T1(rB(ctx->opcode)); \
352 if (Rc(ctx->opcode) != 0) \
354 gen_op_store_T0_gpr(rD(ctx->opcode)); \
357 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
358 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
360 gen_op_load_gpr_T0(rA(ctx->opcode)); \
361 gen_op_load_gpr_T1(rB(ctx->opcode)); \
363 if (Rc(ctx->opcode) != 0) \
364 gen_op_set_Rc0_ov(); \
365 gen_op_store_T0_gpr(rD(ctx->opcode)); \
368 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
369 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
371 gen_op_load_gpr_T0(rA(ctx->opcode)); \
373 if (Rc(ctx->opcode) != 0) \
375 gen_op_store_T0_gpr(rD(ctx->opcode)); \
377 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
378 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
380 gen_op_load_gpr_T0(rA(ctx->opcode)); \
382 if (Rc(ctx->opcode) != 0) \
383 gen_op_set_Rc0_ov(); \
384 gen_op_store_T0_gpr(rD(ctx->opcode)); \
387 /* Two operands arithmetic functions */
388 #define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
389 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
390 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
392 /* Two operands arithmetic functions with no overflow allowed */
393 #define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
394 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
396 /* One operand arithmetic functions */
397 #define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
398 __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
399 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
401 /* add add. addo addo. */
402 GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
403 /* addc addc. addco addco. */
404 GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
405 /* adde adde. addeo addeo. */
406 GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
407 /* addme addme. addmeo addmeo. */
408 GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
409 /* addze addze. addzeo addzeo. */
410 GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
411 /* divw divw. divwo divwo. */
412 GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
413 /* divwu divwu. divwuo divwuo. */
414 GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
416 GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
418 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
419 /* mullw mullw. mullwo mullwo. */
420 GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
421 /* neg neg. nego nego. */
422 GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
423 /* subf subf. subfo subfo. */
424 GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
425 /* subfc subfc. subfco subfco. */
426 GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
427 /* subfe subfe. subfeo subfeo. */
428 GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
429 /* subfme subfme. subfmeo subfmeo. */
430 GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
431 /* subfze subfze. subfzeo subfzeo. */
432 GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
434 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
436 int32_t simm = SIMM(ctx->opcode);
438 if (rA(ctx->opcode) == 0) {
441 gen_op_load_gpr_T0(rA(ctx->opcode));
444 gen_op_store_T0_gpr(rD(ctx->opcode));
447 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
449 gen_op_load_gpr_T0(rA(ctx->opcode));
450 gen_op_addic(SIMM(ctx->opcode));
451 gen_op_store_T0_gpr(rD(ctx->opcode));
454 GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
456 gen_op_load_gpr_T0(rA(ctx->opcode));
457 gen_op_addic(SIMM(ctx->opcode));
459 gen_op_store_T0_gpr(rD(ctx->opcode));
462 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
464 int32_t simm = SIMM(ctx->opcode);
466 if (rA(ctx->opcode) == 0) {
467 gen_op_set_T0(simm << 16);
469 gen_op_load_gpr_T0(rA(ctx->opcode));
470 gen_op_addi(simm << 16);
472 gen_op_store_T0_gpr(rD(ctx->opcode));
475 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
477 gen_op_load_gpr_T0(rA(ctx->opcode));
478 gen_op_mulli(SIMM(ctx->opcode));
479 gen_op_store_T0_gpr(rD(ctx->opcode));
482 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
484 gen_op_load_gpr_T0(rA(ctx->opcode));
485 gen_op_subfic(SIMM(ctx->opcode));
486 gen_op_store_T0_gpr(rD(ctx->opcode));
489 /*** Integer comparison ***/
490 #define GEN_CMP(name, opc) \
491 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
493 gen_op_load_gpr_T0(rA(ctx->opcode)); \
494 gen_op_load_gpr_T1(rB(ctx->opcode)); \
496 gen_op_store_T0_crf(crfD(ctx->opcode)); \
502 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
504 gen_op_load_gpr_T0(rA(ctx->opcode));
505 gen_op_cmpi(SIMM(ctx->opcode));
506 gen_op_store_T0_crf(crfD(ctx->opcode));
511 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
513 gen_op_load_gpr_T0(rA(ctx->opcode));
514 gen_op_cmpli(UIMM(ctx->opcode));
515 gen_op_store_T0_crf(crfD(ctx->opcode));
518 /*** Integer logical ***/
519 #define __GEN_LOGICAL2(name, opc2, opc3) \
520 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
522 gen_op_load_gpr_T0(rS(ctx->opcode)); \
523 gen_op_load_gpr_T1(rB(ctx->opcode)); \
525 if (Rc(ctx->opcode) != 0) \
527 gen_op_store_T0_gpr(rA(ctx->opcode)); \
529 #define GEN_LOGICAL2(name, opc) \
530 __GEN_LOGICAL2(name, 0x1C, opc)
532 #define GEN_LOGICAL1(name, opc) \
533 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
535 gen_op_load_gpr_T0(rS(ctx->opcode)); \
537 if (Rc(ctx->opcode) != 0) \
539 gen_op_store_T0_gpr(rA(ctx->opcode)); \
543 GEN_LOGICAL2(and, 0x00);
545 GEN_LOGICAL2(andc, 0x01);
547 GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
549 gen_op_load_gpr_T0(rS(ctx->opcode));
550 gen_op_andi_(UIMM(ctx->opcode));
552 gen_op_store_T0_gpr(rA(ctx->opcode));
555 GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
557 gen_op_load_gpr_T0(rS(ctx->opcode));
558 gen_op_andi_(UIMM(ctx->opcode) << 16);
560 gen_op_store_T0_gpr(rA(ctx->opcode));
564 GEN_LOGICAL1(cntlzw, 0x00);
566 GEN_LOGICAL2(eqv, 0x08);
568 GEN_LOGICAL1(extsb, 0x1D);
570 GEN_LOGICAL1(extsh, 0x1C);
572 GEN_LOGICAL2(nand, 0x0E);
574 GEN_LOGICAL2(nor, 0x03);
577 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
579 gen_op_load_gpr_T0(rS(ctx->opcode));
580 /* Optimisation for mr case */
581 if (rS(ctx->opcode) != rB(ctx->opcode)) {
582 gen_op_load_gpr_T1(rB(ctx->opcode));
585 if (Rc(ctx->opcode) != 0)
587 gen_op_store_T0_gpr(rA(ctx->opcode));
591 GEN_LOGICAL2(orc, 0x0C);
593 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
595 gen_op_load_gpr_T0(rS(ctx->opcode));
596 /* Optimisation for "set to zero" case */
597 if (rS(ctx->opcode) != rB(ctx->opcode)) {
598 gen_op_load_gpr_T1(rB(ctx->opcode));
603 if (Rc(ctx->opcode) != 0)
605 gen_op_store_T0_gpr(rA(ctx->opcode));
608 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
610 uint32_t uimm = UIMM(ctx->opcode);
612 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
616 gen_op_load_gpr_T0(rS(ctx->opcode));
619 gen_op_store_T0_gpr(rA(ctx->opcode));
622 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
624 uint32_t uimm = UIMM(ctx->opcode);
626 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
630 gen_op_load_gpr_T0(rS(ctx->opcode));
632 gen_op_ori(uimm << 16);
633 gen_op_store_T0_gpr(rA(ctx->opcode));
636 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
638 uint32_t uimm = UIMM(ctx->opcode);
640 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
644 gen_op_load_gpr_T0(rS(ctx->opcode));
647 gen_op_store_T0_gpr(rA(ctx->opcode));
651 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
653 uint32_t uimm = UIMM(ctx->opcode);
655 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
659 gen_op_load_gpr_T0(rS(ctx->opcode));
661 gen_op_xori(uimm << 16);
662 gen_op_store_T0_gpr(rA(ctx->opcode));
665 /*** Integer rotate ***/
666 /* rlwimi & rlwimi. */
667 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
671 mb = MB(ctx->opcode);
672 me = ME(ctx->opcode);
673 gen_op_load_gpr_T0(rS(ctx->opcode));
674 gen_op_load_gpr_T1(rA(ctx->opcode));
675 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
676 if (Rc(ctx->opcode) != 0)
678 gen_op_store_T0_gpr(rA(ctx->opcode));
680 /* rlwinm & rlwinm. */
681 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
685 sh = SH(ctx->opcode);
686 mb = MB(ctx->opcode);
687 me = ME(ctx->opcode);
688 gen_op_load_gpr_T0(rS(ctx->opcode));
691 gen_op_andi_(MASK(mb, me));
700 } else if (me == (31 - sh)) {
705 } else if (me == 31) {
707 if (sh == (32 - mb)) {
713 gen_op_rlwinm(sh, MASK(mb, me));
715 if (Rc(ctx->opcode) != 0)
717 gen_op_store_T0_gpr(rA(ctx->opcode));
720 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
724 mb = MB(ctx->opcode);
725 me = ME(ctx->opcode);
726 gen_op_load_gpr_T0(rS(ctx->opcode));
727 gen_op_load_gpr_T1(rB(ctx->opcode));
728 if (mb == 0 && me == 31) {
732 gen_op_rlwnm(MASK(mb, me));
734 if (Rc(ctx->opcode) != 0)
736 gen_op_store_T0_gpr(rA(ctx->opcode));
739 /*** Integer shift ***/
741 __GEN_LOGICAL2(slw, 0x18, 0x00);
743 __GEN_LOGICAL2(sraw, 0x18, 0x18);
745 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
747 gen_op_load_gpr_T0(rS(ctx->opcode));
748 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
749 if (Rc(ctx->opcode) != 0)
751 gen_op_store_T0_gpr(rA(ctx->opcode));
754 __GEN_LOGICAL2(srw, 0x18, 0x10);
756 /*** Floating-Point arithmetic ***/
757 #define _GEN_FLOAT_ACB(name, op1, op2) \
758 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
760 gen_op_reset_scrfx(); \
761 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
762 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
763 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
765 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
766 if (Rc(ctx->opcode)) \
770 #define GEN_FLOAT_ACB(name, op2) \
771 _GEN_FLOAT_ACB(name, 0x3F, op2); \
772 _GEN_FLOAT_ACB(name##s, 0x3B, op2);
774 #define _GEN_FLOAT_AB(name, op1, op2, inval) \
775 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
777 gen_op_reset_scrfx(); \
778 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
779 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
781 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
782 if (Rc(ctx->opcode)) \
785 #define GEN_FLOAT_AB(name, op2, inval) \
786 _GEN_FLOAT_AB(name, 0x3F, op2, inval); \
787 _GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
789 #define _GEN_FLOAT_AC(name, op1, op2, inval) \
790 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
792 gen_op_reset_scrfx(); \
793 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
794 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
796 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
797 if (Rc(ctx->opcode)) \
800 #define GEN_FLOAT_AC(name, op2, inval) \
801 _GEN_FLOAT_AC(name, 0x3F, op2, inval); \
802 _GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
804 #define GEN_FLOAT_B(name, op2, op3) \
805 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
807 gen_op_reset_scrfx(); \
808 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
810 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
811 if (Rc(ctx->opcode)) \
815 #define GEN_FLOAT_BS(name, op2) \
816 GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
818 gen_op_reset_scrfx(); \
819 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
821 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
822 if (Rc(ctx->opcode)) \
827 GEN_FLOAT_AB(add, 0x15, 0x000007C0);
829 GEN_FLOAT_AB(div, 0x12, 0x000007C0);
831 GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
834 GEN_FLOAT_BS(res, 0x18);
837 GEN_FLOAT_BS(rsqrte, 0x1A);
840 _GEN_FLOAT_ACB(sel, 0x3F, 0x17);
842 GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
845 GEN_FLOAT_BS(sqrt, 0x16);
847 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
849 gen_op_reset_scrfx();
850 gen_op_load_fpr_FT0(rB(ctx->opcode));
852 gen_op_store_FT0_fpr(rD(ctx->opcode));
857 /*** Floating-Point multiply-and-add ***/
859 GEN_FLOAT_ACB(madd, 0x1D);
861 GEN_FLOAT_ACB(msub, 0x1C);
863 GEN_FLOAT_ACB(nmadd, 0x1F);
865 GEN_FLOAT_ACB(nmsub, 0x1E);
867 /*** Floating-Point round & convert ***/
869 GEN_FLOAT_B(ctiw, 0x0E, 0x00);
871 GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
873 GEN_FLOAT_B(rsp, 0x0C, 0x00);
875 /*** Floating-Point compare ***/
877 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
879 gen_op_reset_scrfx();
880 gen_op_load_fpr_FT0(rA(ctx->opcode));
881 gen_op_load_fpr_FT1(rB(ctx->opcode));
883 gen_op_store_T0_crf(crfD(ctx->opcode));
887 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
889 gen_op_reset_scrfx();
890 gen_op_load_fpr_FT0(rA(ctx->opcode));
891 gen_op_load_fpr_FT1(rB(ctx->opcode));
893 gen_op_store_T0_crf(crfD(ctx->opcode));
896 /*** Floating-point move ***/
898 GEN_FLOAT_B(abs, 0x08, 0x08);
901 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
903 gen_op_reset_scrfx();
904 gen_op_load_fpr_FT0(rB(ctx->opcode));
905 gen_op_store_FT0_fpr(rD(ctx->opcode));
911 GEN_FLOAT_B(nabs, 0x08, 0x04);
913 GEN_FLOAT_B(neg, 0x08, 0x01);
915 /*** Floating-Point status & ctrl register ***/
917 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
919 gen_op_load_fpscr_T0(crfS(ctx->opcode));
920 gen_op_store_T0_crf(crfD(ctx->opcode));
921 gen_op_clear_fpscr(crfS(ctx->opcode));
925 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
928 gen_op_store_FT0_fpr(rD(ctx->opcode));
934 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
938 crb = crbD(ctx->opcode) >> 2;
939 gen_op_load_fpscr_T0(crb);
940 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
941 gen_op_store_T0_fpscr(crb);
947 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
951 crb = crbD(ctx->opcode) >> 2;
952 gen_op_load_fpscr_T0(crb);
953 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
954 gen_op_store_T0_fpscr(crb);
960 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
962 gen_op_load_fpr_FT0(rB(ctx->opcode));
963 gen_op_store_fpscr(FM(ctx->opcode));
969 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
971 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
976 /*** Integer load ***/
977 #if defined(CONFIG_USER_ONLY)
978 #define op_ldst(name) gen_op_##name##_raw()
979 #define OP_LD_TABLE(width)
980 #define OP_ST_TABLE(width)
982 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
983 #define OP_LD_TABLE(width) \
984 static GenOpFunc *gen_op_l##width[] = { \
985 &gen_op_l##width##_user, \
986 &gen_op_l##width##_kernel, \
988 #define OP_ST_TABLE(width) \
989 static GenOpFunc *gen_op_st##width[] = { \
990 &gen_op_st##width##_user, \
991 &gen_op_st##width##_kernel, \
995 #define GEN_LD(width, opc) \
996 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
998 uint32_t simm = SIMM(ctx->opcode); \
999 if (rA(ctx->opcode) == 0) { \
1000 gen_op_set_T0(simm); \
1002 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1004 gen_op_addi(simm); \
1006 op_ldst(l##width); \
1007 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1010 #define GEN_LDU(width, opc) \
1011 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1013 uint32_t simm = SIMM(ctx->opcode); \
1014 if (rA(ctx->opcode) == 0 || \
1015 rA(ctx->opcode) == rD(ctx->opcode)) { \
1019 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1021 gen_op_addi(simm); \
1022 op_ldst(l##width); \
1023 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1024 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1027 #define GEN_LDUX(width, opc) \
1028 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1030 if (rA(ctx->opcode) == 0 || \
1031 rA(ctx->opcode) == rD(ctx->opcode)) { \
1035 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1036 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1038 op_ldst(l##width); \
1039 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1040 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1043 #define GEN_LDX(width, opc2, opc3) \
1044 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1046 if (rA(ctx->opcode) == 0) { \
1047 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1049 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1050 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1053 op_ldst(l##width); \
1054 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1057 #define GEN_LDS(width, op) \
1058 OP_LD_TABLE(width); \
1059 GEN_LD(width, op | 0x20); \
1060 GEN_LDU(width, op | 0x21); \
1061 GEN_LDUX(width, op | 0x01); \
1062 GEN_LDX(width, 0x17, op | 0x00)
1064 /* lbz lbzu lbzux lbzx */
1066 /* lha lhau lhaux lhax */
1068 /* lhz lhzu lhzux lhzx */
1070 /* lwz lwzu lwzux lwzx */
1073 /*** Integer store ***/
1074 #define GEN_ST(width, opc) \
1075 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1077 uint32_t simm = SIMM(ctx->opcode); \
1078 if (rA(ctx->opcode) == 0) { \
1079 gen_op_set_T0(simm); \
1081 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1083 gen_op_addi(simm); \
1085 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1086 op_ldst(st##width); \
1089 #define GEN_STU(width, opc) \
1090 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1092 uint32_t simm = SIMM(ctx->opcode); \
1093 if (rA(ctx->opcode) == 0) { \
1097 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1099 gen_op_addi(simm); \
1100 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1101 op_ldst(st##width); \
1102 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1105 #define GEN_STUX(width, opc) \
1106 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1108 if (rA(ctx->opcode) == 0) { \
1112 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1113 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1115 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1116 op_ldst(st##width); \
1117 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1120 #define GEN_STX(width, opc2, opc3) \
1121 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1123 if (rA(ctx->opcode) == 0) { \
1124 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1126 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1127 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1130 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1131 op_ldst(st##width); \
1134 #define GEN_STS(width, op) \
1135 OP_ST_TABLE(width); \
1136 GEN_ST(width, op | 0x20); \
1137 GEN_STU(width, op | 0x21); \
1138 GEN_STUX(width, op | 0x01); \
1139 GEN_STX(width, 0x17, op | 0x00)
1141 /* stb stbu stbux stbx */
1143 /* sth sthu sthux sthx */
1145 /* stw stwu stwux stwx */
1148 /*** Integer load and store with byte reverse ***/
1151 GEN_LDX(hbr, 0x16, 0x18);
1154 GEN_LDX(wbr, 0x16, 0x10);
1157 GEN_STX(hbr, 0x16, 0x1C);
1160 GEN_STX(wbr, 0x16, 0x14);
1162 /*** Integer load and store multiple ***/
1163 #if defined(CONFIG_USER_ONLY)
1164 #define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1166 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1167 static GenOpFunc1 *gen_op_lmw[] = {
1171 static GenOpFunc1 *gen_op_stmw[] = {
1173 &gen_op_stmw_kernel,
1178 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1180 int simm = SIMM(ctx->opcode);
1182 if (rA(ctx->opcode) == 0) {
1183 gen_op_set_T0(simm);
1185 gen_op_load_gpr_T0(rA(ctx->opcode));
1189 op_ldstm(lmw, rD(ctx->opcode));
1193 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1195 int simm = SIMM(ctx->opcode);
1197 if (rA(ctx->opcode) == 0) {
1198 gen_op_set_T0(simm);
1200 gen_op_load_gpr_T0(rA(ctx->opcode));
1204 op_ldstm(stmw, rS(ctx->opcode));
1207 /*** Integer load and store strings ***/
1208 #if defined(CONFIG_USER_ONLY)
1209 #define op_ldsts(name, start) gen_op_##name##_raw(start)
1210 #define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1212 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1213 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1214 static GenOpFunc1 *gen_op_lswi[] = {
1216 &gen_op_lswi_kernel,
1218 static GenOpFunc3 *gen_op_lswx[] = {
1220 &gen_op_lswx_kernel,
1222 static GenOpFunc1 *gen_op_stsw[] = {
1224 &gen_op_stsw_kernel,
1229 /* PPC32 specification says we must generate an exception if
1230 * rA is in the range of registers to be loaded.
1231 * In an other hand, IBM says this is valid, but rA won't be loaded.
1232 * For now, I'll follow the spec...
1234 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1236 int nb = NB(ctx->opcode);
1237 int start = rD(ctx->opcode);
1238 int ra = rA(ctx->opcode);
1244 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1245 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
1246 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1252 gen_op_load_gpr_T0(ra);
1255 op_ldsts(lswi, start);
1259 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1261 int ra = rA(ctx->opcode);
1262 int rb = rB(ctx->opcode);
1265 gen_op_load_gpr_T0(rb);
1268 gen_op_load_gpr_T0(ra);
1269 gen_op_load_gpr_T1(rb);
1272 gen_op_load_xer_bc();
1273 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
1277 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1279 int nb = NB(ctx->opcode);
1281 if (rA(ctx->opcode) == 0) {
1284 gen_op_load_gpr_T0(rA(ctx->opcode));
1289 op_ldsts(stsw, rS(ctx->opcode));
1293 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1295 int ra = rA(ctx->opcode);
1298 gen_op_load_gpr_T0(rB(ctx->opcode));
1299 ra = rB(ctx->opcode);
1301 gen_op_load_gpr_T0(ra);
1302 gen_op_load_gpr_T1(rB(ctx->opcode));
1305 gen_op_load_xer_bc();
1306 op_ldsts(stsw, rS(ctx->opcode));
1309 /*** Memory synchronisation ***/
1311 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1316 GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1321 #if defined(CONFIG_USER_ONLY)
1322 #define op_lwarx() gen_op_lwarx_raw()
1323 #define op_stwcx() gen_op_stwcx_raw()
1325 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1326 static GenOpFunc *gen_op_lwarx[] = {
1328 &gen_op_lwarx_kernel,
1330 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1331 static GenOpFunc *gen_op_stwcx[] = {
1333 &gen_op_stwcx_kernel,
1337 GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1339 if (rA(ctx->opcode) == 0) {
1340 gen_op_load_gpr_T0(rB(ctx->opcode));
1342 gen_op_load_gpr_T0(rA(ctx->opcode));
1343 gen_op_load_gpr_T1(rB(ctx->opcode));
1347 gen_op_store_T1_gpr(rD(ctx->opcode));
1351 GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
1353 if (rA(ctx->opcode) == 0) {
1354 gen_op_load_gpr_T0(rB(ctx->opcode));
1356 gen_op_load_gpr_T0(rA(ctx->opcode));
1357 gen_op_load_gpr_T1(rB(ctx->opcode));
1360 gen_op_load_gpr_T1(rS(ctx->opcode));
1365 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1369 /*** Floating-point load ***/
1370 #define GEN_LDF(width, opc) \
1371 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1373 uint32_t simm = SIMM(ctx->opcode); \
1374 if (rA(ctx->opcode) == 0) { \
1375 gen_op_set_T0(simm); \
1377 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1379 gen_op_addi(simm); \
1381 op_ldst(l##width); \
1382 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1385 #define GEN_LDUF(width, opc) \
1386 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1388 uint32_t simm = SIMM(ctx->opcode); \
1389 if (rA(ctx->opcode) == 0 || \
1390 rA(ctx->opcode) == rD(ctx->opcode)) { \
1394 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1396 gen_op_addi(simm); \
1397 op_ldst(l##width); \
1398 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1399 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1402 #define GEN_LDUXF(width, opc) \
1403 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1405 if (rA(ctx->opcode) == 0 || \
1406 rA(ctx->opcode) == rD(ctx->opcode)) { \
1410 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1411 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1413 op_ldst(l##width); \
1414 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1415 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1418 #define GEN_LDXF(width, opc2, opc3) \
1419 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1421 if (rA(ctx->opcode) == 0) { \
1422 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1424 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1425 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1428 op_ldst(l##width); \
1429 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1432 #define GEN_LDFS(width, op) \
1433 OP_LD_TABLE(width); \
1434 GEN_LDF(width, op | 0x20); \
1435 GEN_LDUF(width, op | 0x21); \
1436 GEN_LDUXF(width, op | 0x01); \
1437 GEN_LDXF(width, 0x17, op | 0x00)
1439 /* lfd lfdu lfdux lfdx */
1441 /* lfs lfsu lfsux lfsx */
1444 /*** Floating-point store ***/
1445 #define GEN_STF(width, opc) \
1446 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1448 uint32_t simm = SIMM(ctx->opcode); \
1449 if (rA(ctx->opcode) == 0) { \
1450 gen_op_set_T0(simm); \
1452 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1454 gen_op_addi(simm); \
1456 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1457 op_ldst(st##width); \
1460 #define GEN_STUF(width, opc) \
1461 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1463 uint32_t simm = SIMM(ctx->opcode); \
1464 if (rA(ctx->opcode) == 0) { \
1468 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1470 gen_op_addi(simm); \
1471 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1472 op_ldst(st##width); \
1473 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1476 #define GEN_STUXF(width, opc) \
1477 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1479 if (rA(ctx->opcode) == 0) { \
1483 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1484 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1486 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1487 op_ldst(st##width); \
1488 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1491 #define GEN_STXF(width, opc2, opc3) \
1492 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1494 if (rA(ctx->opcode) == 0) { \
1495 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1497 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1498 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1501 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1502 op_ldst(st##width); \
1505 #define GEN_STFS(width, op) \
1506 OP_ST_TABLE(width); \
1507 GEN_STF(width, op | 0x20); \
1508 GEN_STUF(width, op | 0x21); \
1509 GEN_STUXF(width, op | 0x01); \
1510 GEN_STXF(width, 0x17, op | 0x00)
1512 /* stfd stfdu stfdux stfdx */
1514 /* stfs stfsu stfsux stfsx */
1519 GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1527 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1529 uint32_t li, target;
1531 /* sign extend LI */
1532 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
1534 if (AA(ctx->opcode) == 0)
1535 target = ctx->nip + li - 4;
1538 if (LK(ctx->opcode)) {
1539 gen_op_setlr(ctx->nip);
1541 gen_op_b((long)ctx->tb, target);
1542 ctx->exception = EXCP_BRANCH;
1549 static inline void gen_bcond(DisasContext *ctx, int type)
1551 uint32_t target = 0;
1552 uint32_t bo = BO(ctx->opcode);
1553 uint32_t bi = BI(ctx->opcode);
1557 if ((bo & 0x4) == 0)
1561 li = s_ext16(BD(ctx->opcode));
1562 if (AA(ctx->opcode) == 0) {
1563 target = ctx->nip + li - 4;
1569 gen_op_movl_T1_ctr();
1573 gen_op_movl_T1_lr();
1576 if (LK(ctx->opcode)) {
1577 gen_op_setlr(ctx->nip);
1580 /* No CR condition */
1591 if (type == BCOND_IM) {
1592 gen_op_b((long)ctx->tb, target);
1599 mask = 1 << (3 - (bi & 0x03));
1600 gen_op_load_crf_T0(bi >> 2);
1604 gen_op_test_ctr_true(mask);
1607 gen_op_test_ctrz_true(mask);
1612 gen_op_test_true(mask);
1618 gen_op_test_ctr_false(mask);
1621 gen_op_test_ctrz_false(mask);
1626 gen_op_test_false(mask);
1631 if (type == BCOND_IM) {
1632 gen_op_btest((long)ctx->tb, target, ctx->nip);
1634 gen_op_btest_T1(ctx->nip);
1637 ctx->exception = EXCP_BRANCH;
1640 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1642 gen_bcond(ctx, BCOND_IM);
1645 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1647 gen_bcond(ctx, BCOND_CTR);
1650 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1652 gen_bcond(ctx, BCOND_LR);
1655 /*** Condition register logical ***/
1656 #define GEN_CRLOGIC(op, opc) \
1657 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1659 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1660 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1661 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1662 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1664 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1665 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1666 3 - (crbD(ctx->opcode) & 0x03)); \
1667 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
1671 GEN_CRLOGIC(and, 0x08)
1673 GEN_CRLOGIC(andc, 0x04)
1675 GEN_CRLOGIC(eqv, 0x09)
1677 GEN_CRLOGIC(nand, 0x07)
1679 GEN_CRLOGIC(nor, 0x01)
1681 GEN_CRLOGIC(or, 0x0E)
1683 GEN_CRLOGIC(orc, 0x0D)
1685 GEN_CRLOGIC(xor, 0x06)
1687 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1689 gen_op_load_crf_T0(crfS(ctx->opcode));
1690 gen_op_store_T0_crf(crfD(ctx->opcode));
1693 /*** System linkage ***/
1694 /* rfi (supervisor only) */
1695 GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1697 #if defined(CONFIG_USER_ONLY)
1700 /* Restore CPU state */
1701 if (!ctx->supervisor) {
1706 RET_EXCP(ctx, EXCP_RFI, 0);
1711 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1713 #if defined(CONFIG_USER_ONLY)
1714 RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
1716 RET_EXCP(ctx, EXCP_SYSCALL, 0);
1722 GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1724 gen_op_load_gpr_T0(rA(ctx->opcode));
1725 gen_op_load_gpr_T1(rB(ctx->opcode));
1726 gen_op_tw(TO(ctx->opcode));
1730 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1732 gen_op_load_gpr_T0(rA(ctx->opcode));
1734 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1735 SIMM(ctx->opcode), TO(ctx->opcode));
1737 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
1740 /*** Processor control ***/
1741 static inline int check_spr_access (int spr, int rw, int supervisor)
1743 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1746 if (spr != LR && spr != CTR) {
1748 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1749 SPR_ENCODE(spr), supervisor, rw, rights,
1750 (rights >> ((2 * supervisor) + rw)) & 1);
1752 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1753 SPR_ENCODE(spr), supervisor, rw, rights,
1754 (rights >> ((2 * supervisor) + rw)) & 1);
1760 rights = rights >> (2 * supervisor);
1761 rights = rights >> rw;
1767 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1769 gen_op_load_xer_cr();
1770 gen_op_store_T0_crf(crfD(ctx->opcode));
1771 gen_op_clear_xer_cr();
1775 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1778 gen_op_store_T0_gpr(rD(ctx->opcode));
1782 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1784 #if defined(CONFIG_USER_ONLY)
1787 if (!ctx->supervisor) {
1792 gen_op_store_T0_gpr(rD(ctx->opcode));
1797 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1799 uint32_t sprn = SPR(ctx->opcode);
1801 #if defined(CONFIG_USER_ONLY)
1802 switch (check_spr_access(sprn, 0, 0))
1804 switch (check_spr_access(sprn, 0, ctx->supervisor))
1808 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1827 gen_op_load_ibat(0, 0);
1830 gen_op_load_ibat(0, 1);
1833 gen_op_load_ibat(0, 2);
1836 gen_op_load_ibat(0, 3);
1839 gen_op_load_ibat(0, 4);
1842 gen_op_load_ibat(0, 5);
1845 gen_op_load_ibat(0, 6);
1848 gen_op_load_ibat(0, 7);
1851 gen_op_load_ibat(1, 0);
1854 gen_op_load_ibat(1, 1);
1857 gen_op_load_ibat(1, 2);
1860 gen_op_load_ibat(1, 3);
1863 gen_op_load_ibat(1, 4);
1866 gen_op_load_ibat(1, 5);
1869 gen_op_load_ibat(1, 6);
1872 gen_op_load_ibat(1, 7);
1875 gen_op_load_dbat(0, 0);
1878 gen_op_load_dbat(0, 1);
1881 gen_op_load_dbat(0, 2);
1884 gen_op_load_dbat(0, 3);
1887 gen_op_load_dbat(0, 4);
1890 gen_op_load_dbat(0, 5);
1893 gen_op_load_dbat(0, 6);
1896 gen_op_load_dbat(0, 7);
1899 gen_op_load_dbat(1, 0);
1902 gen_op_load_dbat(1, 1);
1905 gen_op_load_dbat(1, 2);
1908 gen_op_load_dbat(1, 3);
1911 gen_op_load_dbat(1, 4);
1914 gen_op_load_dbat(1, 5);
1917 gen_op_load_dbat(1, 6);
1920 gen_op_load_dbat(1, 7);
1935 gen_op_load_spr(sprn);
1938 gen_op_store_T0_gpr(rD(ctx->opcode));
1942 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
1944 uint32_t sprn = SPR(ctx->opcode);
1946 /* We need to update the time base before reading it */
1958 gen_op_store_T0_gpr(rD(ctx->opcode));
1962 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
1964 gen_op_load_gpr_T0(rS(ctx->opcode));
1965 gen_op_store_cr(CRM(ctx->opcode));
1969 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
1971 #if defined(CONFIG_USER_ONLY)
1974 if (!ctx->supervisor) {
1978 gen_op_load_gpr_T0(rS(ctx->opcode));
1980 /* Must stop the translation as machine state (may have) changed */
1986 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
1988 uint32_t sprn = SPR(ctx->opcode);
1992 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
1993 rS(ctx->opcode), sprn);
1996 #if defined(CONFIG_USER_ONLY)
1997 switch (check_spr_access(sprn, 1, 0))
1999 switch (check_spr_access(sprn, 1, ctx->supervisor))
2003 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2011 gen_op_load_gpr_T0(rS(ctx->opcode));
2023 gen_op_store_ibat(0, 0);
2027 gen_op_store_ibat(0, 1);
2031 gen_op_store_ibat(0, 2);
2035 gen_op_store_ibat(0, 3);
2039 gen_op_store_ibat(0, 4);
2043 gen_op_store_ibat(0, 5);
2047 gen_op_store_ibat(0, 6);
2051 gen_op_store_ibat(0, 7);
2055 gen_op_store_ibat(1, 0);
2059 gen_op_store_ibat(1, 1);
2063 gen_op_store_ibat(1, 2);
2067 gen_op_store_ibat(1, 3);
2071 gen_op_store_ibat(1, 4);
2075 gen_op_store_ibat(1, 5);
2079 gen_op_store_ibat(1, 6);
2083 gen_op_store_ibat(1, 7);
2087 gen_op_store_dbat(0, 0);
2091 gen_op_store_dbat(0, 1);
2095 gen_op_store_dbat(0, 2);
2099 gen_op_store_dbat(0, 3);
2103 gen_op_store_dbat(0, 4);
2107 gen_op_store_dbat(0, 5);
2111 gen_op_store_dbat(0, 6);
2115 gen_op_store_dbat(0, 7);
2119 gen_op_store_dbat(1, 0);
2123 gen_op_store_dbat(1, 1);
2127 gen_op_store_dbat(1, 2);
2131 gen_op_store_dbat(1, 3);
2135 gen_op_store_dbat(1, 4);
2139 gen_op_store_dbat(1, 5);
2143 gen_op_store_dbat(1, 6);
2147 gen_op_store_dbat(1, 7);
2151 gen_op_store_sdr1();
2161 gen_op_store_decr();
2165 gen_op_store_hid0();
2169 gen_op_store_spr(sprn);
2174 /*** Cache management ***/
2175 /* For now, all those will be implemented as nop:
2176 * this is valid, regarding the PowerPC specs...
2177 * We just have to flush tb while invalidating instruction cache lines...
2180 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
2182 if (rA(ctx->opcode) == 0) {
2183 gen_op_load_gpr_T0(rB(ctx->opcode));
2185 gen_op_load_gpr_T0(rA(ctx->opcode));
2186 gen_op_load_gpr_T1(rB(ctx->opcode));
2192 /* dcbi (Supervisor only) */
2193 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
2195 #if defined(CONFIG_USER_ONLY)
2198 if (!ctx->supervisor) {
2202 if (rA(ctx->opcode) == 0) {
2203 gen_op_load_gpr_T0(rB(ctx->opcode));
2205 gen_op_load_gpr_T0(rA(ctx->opcode));
2206 gen_op_load_gpr_T1(rB(ctx->opcode));
2215 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
2217 if (rA(ctx->opcode) == 0) {
2218 gen_op_load_gpr_T0(rB(ctx->opcode));
2220 gen_op_load_gpr_T0(rA(ctx->opcode));
2221 gen_op_load_gpr_T1(rB(ctx->opcode));
2228 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
2233 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
2238 #if defined(CONFIG_USER_ONLY)
2239 #define op_dcbz() gen_op_dcbz_raw()
2241 #define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2242 static GenOpFunc *gen_op_dcbz[] = {
2244 &gen_op_dcbz_kernel,
2248 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
2250 if (rA(ctx->opcode) == 0) {
2251 gen_op_load_gpr_T0(rB(ctx->opcode));
2253 gen_op_load_gpr_T0(rA(ctx->opcode));
2254 gen_op_load_gpr_T1(rB(ctx->opcode));
2258 gen_op_check_reservation();
2262 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
2264 if (rA(ctx->opcode) == 0) {
2265 gen_op_load_gpr_T0(rB(ctx->opcode));
2267 gen_op_load_gpr_T0(rA(ctx->opcode));
2268 gen_op_load_gpr_T1(rB(ctx->opcode));
2276 GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
2280 /*** Segment register manipulation ***/
2281 /* Supervisor only: */
2283 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2285 #if defined(CONFIG_USER_ONLY)
2288 if (!ctx->supervisor) {
2292 gen_op_load_sr(SR(ctx->opcode));
2293 gen_op_store_T0_gpr(rD(ctx->opcode));
2298 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
2300 #if defined(CONFIG_USER_ONLY)
2303 if (!ctx->supervisor) {
2307 gen_op_load_gpr_T1(rB(ctx->opcode));
2309 gen_op_store_T0_gpr(rD(ctx->opcode));
2314 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
2316 #if defined(CONFIG_USER_ONLY)
2319 if (!ctx->supervisor) {
2323 gen_op_load_gpr_T0(rS(ctx->opcode));
2324 gen_op_store_sr(SR(ctx->opcode));
2329 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
2331 #if defined(CONFIG_USER_ONLY)
2334 if (!ctx->supervisor) {
2338 gen_op_load_gpr_T0(rS(ctx->opcode));
2339 gen_op_load_gpr_T1(rB(ctx->opcode));
2340 gen_op_store_srin();
2344 /*** Lookaside buffer management ***/
2345 /* Optional & supervisor only: */
2347 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
2349 #if defined(CONFIG_USER_ONLY)
2352 if (!ctx->supervisor) {
2354 fprintf(logfile, "%s: ! supervisor\n", __func__);
2364 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
2366 #if defined(CONFIG_USER_ONLY)
2369 if (!ctx->supervisor) {
2373 gen_op_load_gpr_T0(rB(ctx->opcode));
2380 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
2382 #if defined(CONFIG_USER_ONLY)
2385 if (!ctx->supervisor) {
2389 /* This has no effect: it should ensure that all previous
2390 * tlbie have completed
2396 /*** External control ***/
2399 #if defined(CONFIG_USER_ONLY)
2400 #define op_eciwx() gen_op_eciwx_raw()
2401 #define op_ecowx() gen_op_ecowx_raw()
2403 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2404 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2405 static GenOpFunc *gen_op_eciwx[] = {
2407 &gen_op_eciwx_kernel,
2409 static GenOpFunc *gen_op_ecowx[] = {
2411 &gen_op_ecowx_kernel,
2415 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2417 /* Should check EAR[E] & alignment ! */
2418 if (rA(ctx->opcode) == 0) {
2419 gen_op_load_gpr_T0(rB(ctx->opcode));
2421 gen_op_load_gpr_T0(rA(ctx->opcode));
2422 gen_op_load_gpr_T1(rB(ctx->opcode));
2426 gen_op_store_T0_gpr(rD(ctx->opcode));
2430 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2432 /* Should check EAR[E] & alignment ! */
2433 if (rA(ctx->opcode) == 0) {
2434 gen_op_load_gpr_T0(rB(ctx->opcode));
2436 gen_op_load_gpr_T0(rA(ctx->opcode));
2437 gen_op_load_gpr_T1(rB(ctx->opcode));
2440 gen_op_load_gpr_T2(rS(ctx->opcode));
2444 /* End opcode list */
2445 GEN_OPCODE_MARK(end);
2447 /*****************************************************************************/
2451 int fflush (FILE *stream);
2453 /* Main ppc opcodes table:
2454 * at init, all opcodes are invalids
2456 static opc_handler_t *ppc_opcodes[0x40];
2460 PPC_DIRECT = 0, /* Opcode routine */
2461 PPC_INDIRECT = 1, /* Indirect opcode table */
2464 static inline int is_indirect_opcode (void *handler)
2466 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2469 static inline opc_handler_t **ind_table(void *handler)
2471 return (opc_handler_t **)((unsigned long)handler & ~3);
2474 /* Instruction table creation */
2475 /* Opcodes tables creation */
2476 static void fill_new_table (opc_handler_t **table, int len)
2480 for (i = 0; i < len; i++)
2481 table[i] = &invalid_handler;
2484 static int create_new_table (opc_handler_t **table, unsigned char idx)
2486 opc_handler_t **tmp;
2488 tmp = malloc(0x20 * sizeof(opc_handler_t));
2491 fill_new_table(tmp, 0x20);
2492 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2497 static int insert_in_table (opc_handler_t **table, unsigned char idx,
2498 opc_handler_t *handler)
2500 if (table[idx] != &invalid_handler)
2502 table[idx] = handler;
2507 static int register_direct_insn (opc_handler_t **ppc_opcodes,
2508 unsigned char idx, opc_handler_t *handler)
2510 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2511 printf("*** ERROR: opcode %02x already assigned in main "
2512 "opcode table\n", idx);
2519 static int register_ind_in_table (opc_handler_t **table,
2520 unsigned char idx1, unsigned char idx2,
2521 opc_handler_t *handler)
2523 if (table[idx1] == &invalid_handler) {
2524 if (create_new_table(table, idx1) < 0) {
2525 printf("*** ERROR: unable to create indirect table "
2526 "idx=%02x\n", idx1);
2530 if (!is_indirect_opcode(table[idx1])) {
2531 printf("*** ERROR: idx %02x already assigned to a direct "
2536 if (handler != NULL &&
2537 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2538 printf("*** ERROR: opcode %02x already assigned in "
2539 "opcode table %02x\n", idx2, idx1);
2546 static int register_ind_insn (opc_handler_t **ppc_opcodes,
2547 unsigned char idx1, unsigned char idx2,
2548 opc_handler_t *handler)
2552 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2557 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2558 unsigned char idx1, unsigned char idx2,
2559 unsigned char idx3, opc_handler_t *handler)
2561 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2562 printf("*** ERROR: unable to join indirect table idx "
2563 "[%02x-%02x]\n", idx1, idx2);
2566 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2568 printf("*** ERROR: unable to insert opcode "
2569 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2576 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2578 if (insn->opc2 != 0xFF) {
2579 if (insn->opc3 != 0xFF) {
2580 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2581 insn->opc3, &insn->handler) < 0)
2584 if (register_ind_insn(ppc_opcodes, insn->opc1,
2585 insn->opc2, &insn->handler) < 0)
2589 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2596 static int test_opcode_table (opc_handler_t **table, int len)
2600 for (i = 0, count = 0; i < len; i++) {
2601 /* Consistency fixup */
2602 if (table[i] == NULL)
2603 table[i] = &invalid_handler;
2604 if (table[i] != &invalid_handler) {
2605 if (is_indirect_opcode(table[i])) {
2606 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2609 table[i] = &invalid_handler;
2622 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2624 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2625 printf("*** WARNING: no opcode defined !\n");
2628 #define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
2629 #define SPR_UR SPR_RIGHTS(0, 0)
2630 #define SPR_UW SPR_RIGHTS(1, 0)
2631 #define SPR_SR SPR_RIGHTS(0, 1)
2632 #define SPR_SW SPR_RIGHTS(1, 1)
2634 #define spr_set_rights(spr, rights) \
2636 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2639 static void init_spr_rights (uint32_t pvr)
2642 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
2644 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
2646 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
2648 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
2650 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
2651 /* DSISR (SPR 18) */
2652 spr_set_rights(DSISR, SPR_SR | SPR_SW);
2654 spr_set_rights(DAR, SPR_SR | SPR_SW);
2656 spr_set_rights(DECR, SPR_SR | SPR_SW);
2658 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2660 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2662 spr_set_rights(SRR1, SPR_SR | SPR_SW);
2663 /* SPRG0 (SPR 272) */
2664 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
2665 /* SPRG1 (SPR 273) */
2666 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
2667 /* SPRG2 (SPR 274) */
2668 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
2669 /* SPRG3 (SPR 275) */
2670 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
2672 spr_set_rights(ASR, SPR_SR | SPR_SW);
2674 spr_set_rights(EAR, SPR_SR | SPR_SW);
2676 spr_set_rights(O_TBL, SPR_SW);
2678 spr_set_rights(O_TBU, SPR_SW);
2680 spr_set_rights(PVR, SPR_SR);
2681 /* IBAT0U (SPR 528) */
2682 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
2683 /* IBAT0L (SPR 529) */
2684 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
2685 /* IBAT1U (SPR 530) */
2686 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
2687 /* IBAT1L (SPR 531) */
2688 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
2689 /* IBAT2U (SPR 532) */
2690 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
2691 /* IBAT2L (SPR 533) */
2692 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
2693 /* IBAT3U (SPR 534) */
2694 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
2695 /* IBAT3L (SPR 535) */
2696 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
2697 /* DBAT0U (SPR 536) */
2698 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
2699 /* DBAT0L (SPR 537) */
2700 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
2701 /* DBAT1U (SPR 538) */
2702 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
2703 /* DBAT1L (SPR 539) */
2704 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
2705 /* DBAT2U (SPR 540) */
2706 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
2707 /* DBAT2L (SPR 541) */
2708 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
2709 /* DBAT3U (SPR 542) */
2710 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
2711 /* DBAT3L (SPR 543) */
2712 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
2713 /* FPECR (SPR 1022) */
2714 spr_set_rights(FPECR, SPR_SR | SPR_SW);
2715 /* Special registers for PPC 604 */
2716 if ((pvr & 0xFFFF0000) == 0x00040000) {
2718 spr_set_rights(IABR , SPR_SR | SPR_SW);
2719 /* DABR (SPR 1013) */
2720 spr_set_rights(DABR, SPR_SR | SPR_SW);
2722 spr_set_rights(HID0, SPR_SR | SPR_SW);
2724 spr_set_rights(PIR, SPR_SR | SPR_SW);
2726 spr_set_rights(PMC1, SPR_SR | SPR_SW);
2728 spr_set_rights(PMC2, SPR_SR | SPR_SW);
2730 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
2732 spr_set_rights(SIA, SPR_SR | SPR_SW);
2734 spr_set_rights(SDA, SPR_SR | SPR_SW);
2736 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2737 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2738 (pvr & 0xFFFF0000) == 0x70000000) {
2740 spr_set_rights(HID0, SPR_SR | SPR_SW);
2742 spr_set_rights(HID1, SPR_SR | SPR_SW);
2744 spr_set_rights(IABR, SPR_SR | SPR_SW);
2746 spr_set_rights(ICTC, SPR_SR | SPR_SW);
2748 spr_set_rights(L2CR, SPR_SR | SPR_SW);
2750 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
2752 spr_set_rights(MMCR1, SPR_SR | SPR_SW);
2754 spr_set_rights(PMC1, SPR_SR | SPR_SW);
2756 spr_set_rights(PMC2, SPR_SR | SPR_SW);
2758 spr_set_rights(PMC3, SPR_SR | SPR_SW);
2760 spr_set_rights(PMC4, SPR_SR | SPR_SW);
2762 spr_set_rights(SIA, SPR_SR | SPR_SW);
2764 spr_set_rights(SDA, SPR_SR | SPR_SW);
2766 spr_set_rights(THRM1, SPR_SR | SPR_SW);
2768 spr_set_rights(THRM2, SPR_SR | SPR_SW);
2770 spr_set_rights(THRM3, SPR_SR | SPR_SW);
2772 spr_set_rights(UMMCR0, SPR_UR | SPR_UW);
2774 spr_set_rights(UMMCR1, SPR_UR | SPR_UW);
2776 spr_set_rights(UPMC1, SPR_UR | SPR_UW);
2778 spr_set_rights(UPMC2, SPR_UR | SPR_UW);
2780 spr_set_rights(UPMC3, SPR_UR | SPR_UW);
2782 spr_set_rights(UPMC4, SPR_UR | SPR_UW);
2784 spr_set_rights(USIA, SPR_UR | SPR_UW);
2786 /* MPC755 has special registers */
2787 if (pvr == 0x00083100) {
2789 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2791 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2793 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2795 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2797 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2799 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2801 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2803 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2805 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2807 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2809 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2811 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2813 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2815 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2817 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2819 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
2821 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
2823 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
2825 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
2827 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
2829 spr_set_rights(DMISS, SPR_SR | SPR_SW);
2831 spr_set_rights(DCMP, SPR_SR | SPR_SW);
2833 spr_set_rights(DHASH1, SPR_SR | SPR_SW);
2835 spr_set_rights(DHASH2, SPR_SR | SPR_SW);
2837 spr_set_rights(IMISS, SPR_SR | SPR_SW);
2839 spr_set_rights(ICMP, SPR_SR | SPR_SW);
2841 spr_set_rights(RPA, SPR_SR | SPR_SW);
2843 spr_set_rights(HID2, SPR_SR | SPR_SW);
2845 spr_set_rights(L2PM, SPR_SR | SPR_SW);
2849 /*****************************************************************************/
2850 /* PPC "main stream" common instructions (no optional ones) */
2852 typedef struct ppc_proc_t {
2857 typedef struct ppc_def_t {
2859 unsigned long pvr_mask;
2863 static ppc_proc_t ppc_proc_common = {
2864 .flags = PPC_COMMON,
2868 static ppc_proc_t ppc_proc_G3 = {
2873 static ppc_def_t ppc_defs[] =
2875 /* MPC740/745/750/755 (G3) */
2878 .pvr_mask = 0xFFFF0000,
2879 .proc = &ppc_proc_G3,
2881 /* IBM 750FX (G3 embedded) */
2884 .pvr_mask = 0xFFFF0000,
2885 .proc = &ppc_proc_G3,
2887 /* Fallback (generic PPC) */
2890 .pvr_mask = 0x00000000,
2891 .proc = &ppc_proc_common,
2895 static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
2900 fill_new_table(ppc_opcodes, 0x40);
2901 for (i = 0; ; i++) {
2902 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
2903 (pvr & ppc_defs[i].pvr_mask)) {
2904 flags = ppc_defs[i].proc->flags;
2909 for (opc = &opc_start + 1; opc != &opc_end; opc++) {
2910 if ((opc->handler.type & flags) != 0)
2911 if (register_insn(ppc_opcodes, opc) < 0) {
2912 printf("*** ERROR initializing PPC instruction "
2913 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2918 fix_opcode_tables(ppc_opcodes);
2924 /*****************************************************************************/
2925 /* Misc PPC helpers */
2927 void cpu_dump_state(CPUState *env, FILE *f,
2928 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2933 cpu_fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
2934 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
2935 _load_xer(env), _load_msr(env));
2936 for (i = 0; i < 32; i++) {
2938 cpu_fprintf(f, "GPR%02d:", i);
2939 cpu_fprintf(f, " %08x", env->gpr[i]);
2941 cpu_fprintf(f, "\n");
2943 cpu_fprintf(f, "CR: 0x");
2944 for (i = 0; i < 8; i++)
2945 cpu_fprintf(f, "%01x", env->crf[i]);
2946 cpu_fprintf(f, " [");
2947 for (i = 0; i < 8; i++) {
2949 if (env->crf[i] & 0x08)
2951 else if (env->crf[i] & 0x04)
2953 else if (env->crf[i] & 0x02)
2955 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
2957 cpu_fprintf(f, " ] ");
2958 cpu_fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
2959 cpu_ppc_load_tbl(env));
2960 for (i = 0; i < 16; i++) {
2962 cpu_fprintf(f, "FPR%02d:", i);
2963 cpu_fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
2965 cpu_fprintf(f, "\n");
2967 cpu_fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
2968 env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env));
2969 cpu_fprintf(f, "reservation 0x%08x\n", env->reserve);
2972 #if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE)
2973 int setup_machine (CPUPPCState *env, uint32_t mid);
2976 CPUPPCState *cpu_ppc_init(void)
2982 env = qemu_mallocz(sizeof(CPUPPCState));
2985 #if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE)
2986 setup_machine(env, 0);
2988 // env->spr[PVR] = 0; /* Basic PPC */
2989 env->spr[PVR] = 0x00080100; /* G3 CPU */
2990 // env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
2991 // env->spr[PVR] = 0x00070100; /* IBM 750FX */
2994 #if defined (DO_SINGLE_STEP)
2995 /* Single step trace mode */
2998 msr_fp = 1; /* Allow floating point exceptions */
2999 msr_me = 1; /* Allow machine check exceptions */
3000 #if defined(CONFIG_USER_ONLY)
3002 cpu_ppc_register(env, 0x00080000);
3004 env->nip = 0xFFFFFFFC;
3006 cpu_single_env = env;
3010 int cpu_ppc_register (CPUPPCState *env, uint32_t pvr)
3012 env->spr[PVR] = pvr;
3013 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
3015 init_spr_rights(env->spr[PVR]);
3020 void cpu_ppc_close(CPUPPCState *env)
3022 /* Should also remove all opcode tables... */
3026 /*****************************************************************************/
3027 int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3030 DisasContext ctx, *ctxp = &ctx;
3031 opc_handler_t **table, *handler;
3033 uint16_t *gen_opc_end;
3037 gen_opc_ptr = gen_opc_buf;
3038 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3039 gen_opparam_ptr = gen_opparam_buf;
3042 ctx.exception = EXCP_NONE;
3043 #if defined(CONFIG_USER_ONLY)
3046 ctx.supervisor = 1 - msr_pr;
3047 ctx.mem_idx = (1 - msr_pr);
3049 #if defined (DO_SINGLE_STEP)
3050 /* Single step trace mode */
3053 /* Set env in case of segfault during code fetch */
3054 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
3056 j = gen_opc_ptr - gen_opc_buf;
3060 gen_opc_instr_start[lj++] = 0;
3061 gen_opc_pc[lj] = ctx.nip;
3062 gen_opc_instr_start[lj] = 1;
3065 #if defined PPC_DEBUG_DISAS
3066 if (loglevel & CPU_LOG_TB_IN_ASM) {
3067 fprintf(logfile, "----------------\n");
3068 fprintf(logfile, "nip=%08x super=%d ir=%d\n",
3069 ctx.nip, 1 - msr_pr, msr_ir);
3072 ctx.opcode = ldl_code((void *)ctx.nip);
3073 #if defined PPC_DEBUG_DISAS
3074 if (loglevel & CPU_LOG_TB_IN_ASM) {
3075 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3076 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3081 table = ppc_opcodes;
3082 handler = table[opc1(ctx.opcode)];
3083 if (is_indirect_opcode(handler)) {
3084 table = ind_table(handler);
3085 handler = table[opc2(ctx.opcode)];
3086 if (is_indirect_opcode(handler)) {
3087 table = ind_table(handler);
3088 handler = table[opc3(ctx.opcode)];
3091 /* Is opcode *REALLY* valid ? */
3092 if (handler->handler == &gen_invalid) {
3094 fprintf(logfile, "invalid/unsupported opcode: "
3095 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3096 opc1(ctx.opcode), opc2(ctx.opcode),
3097 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3099 printf("invalid/unsupported opcode: "
3100 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3101 opc1(ctx.opcode), opc2(ctx.opcode),
3102 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3105 if ((ctx.opcode & handler->inval) != 0) {
3107 fprintf(logfile, "invalid bits: %08x for opcode: "
3108 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
3109 ctx.opcode & handler->inval, opc1(ctx.opcode),
3110 opc2(ctx.opcode), opc3(ctx.opcode),
3111 ctx.opcode, ctx.nip - 4);
3113 printf("invalid bits: %08x for opcode: "
3114 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
3115 ctx.opcode & handler->inval, opc1(ctx.opcode),
3116 opc2(ctx.opcode), opc3(ctx.opcode),
3117 ctx.opcode, ctx.nip - 4);
3123 (*(handler->handler))(&ctx);
3124 /* Check trace mode exceptions */
3125 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3126 /* Check in single step trace mode
3127 * we need to stop except if:
3128 * - rfi, trap or syscall
3129 * - first instruction of an exception handler
3131 (msr_se && (ctx.nip < 0x100 ||
3133 (ctx.nip & 0xFC) != 0x04) &&
3134 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3135 ctx.exception != EXCP_TRAP)) {
3136 RET_EXCP(ctxp, EXCP_TRACE, 0);
3138 /* if we reach a page boundary, stop generation */
3139 if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
3140 RET_EXCP(ctxp, EXCP_BRANCH, 0);
3143 if (ctx.exception == EXCP_NONE) {
3144 gen_op_b((unsigned long)ctx.tb, ctx.nip);
3145 } else if (ctx.exception != EXCP_BRANCH) {
3149 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3150 * do bad business and then qemu crashes !
3154 /* Generate the return instruction */
3156 *gen_opc_ptr = INDEX_op_end;
3158 j = gen_opc_ptr - gen_opc_buf;
3161 gen_opc_instr_start[lj++] = 0;
3169 tb->size = ctx.nip - pc_start;
3172 if (loglevel & CPU_LOG_TB_CPU) {
3173 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
3174 cpu_dump_state(env, logfile, fprintf, 0);
3176 if (loglevel & CPU_LOG_TB_IN_ASM) {
3177 fprintf(logfile, "IN: %s\n", lookup_symbol((void *)pc_start));
3178 disas(logfile, (void *)pc_start, ctx.nip - pc_start, 0, 0);
3179 fprintf(logfile, "\n");
3181 if (loglevel & CPU_LOG_TB_OP) {
3182 fprintf(logfile, "OP:\n");
3183 dump_ops(gen_opc_buf, gen_opparam_buf);
3184 fprintf(logfile, "\n");
3190 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3192 return gen_intermediate_code_internal(env, tb, 0);
3195 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3197 return gen_intermediate_code_internal(env, tb, 1);