2 * QEMU IDE disk and CD-ROM Emulator
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* debug IDE devices */
28 //#define DEBUG_IDE_ATAPI
30 /* Bits of HD_STATUS */
32 #define INDEX_STAT 0x02
33 #define ECC_STAT 0x04 /* Corrected error */
35 #define SEEK_STAT 0x10
37 #define WRERR_STAT 0x20
38 #define READY_STAT 0x40
39 #define BUSY_STAT 0x80
41 /* Bits for HD_ERROR */
42 #define MARK_ERR 0x01 /* Bad address mark */
43 #define TRK0_ERR 0x02 /* couldn't find track 0 */
44 #define ABRT_ERR 0x04 /* Command aborted */
45 #define MCR_ERR 0x08 /* media change request */
46 #define ID_ERR 0x10 /* ID field not found */
47 #define MC_ERR 0x20 /* media changed */
48 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
49 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
50 #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
52 /* Bits of HD_NSECTOR */
58 #define IDE_CMD_RESET 0x04
59 #define IDE_CMD_DISABLE_IRQ 0x02
61 /* ATA/ATAPI Commands pre T13 Spec */
66 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
70 #define WIN_SRST 0x08 /* ATAPI soft reset command */
71 #define WIN_DEVICE_RESET 0x08
75 #define WIN_RECAL 0x10
76 #define WIN_RESTORE WIN_RECAL
80 #define WIN_READ 0x20 /* 28-Bit */
81 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
82 #define WIN_READ_LONG 0x22 /* 28-Bit */
83 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
84 #define WIN_READ_EXT 0x24 /* 48-Bit */
85 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
86 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
87 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
91 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
95 #define WIN_WRITE 0x30 /* 28-Bit */
96 #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
97 #define WIN_WRITE_LONG 0x32 /* 28-Bit */
98 #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
99 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
100 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
101 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
102 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
103 #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
104 #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
106 * 0x3A->0x3B Reserved
108 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
110 * 0x3D->0x3F Reserved
112 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
113 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
114 #define WIN_VERIFY_EXT 0x42 /* 48-Bit */
116 * 0x43->0x4F Reserved
118 #define WIN_FORMAT 0x50
120 * 0x51->0x5F Reserved
122 #define WIN_INIT 0x60
124 * 0x61->0x5F Reserved
126 #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
127 #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
128 #define WIN_DIAGNOSE 0x90
129 #define WIN_SPECIFY 0x91 /* set drive geometry translation */
130 #define WIN_DOWNLOAD_MICROCODE 0x92
131 #define WIN_STANDBYNOW2 0x94
132 #define WIN_STANDBY2 0x96
133 #define WIN_SETIDLE2 0x97
134 #define WIN_CHECKPOWERMODE2 0x98
135 #define WIN_SLEEPNOW2 0x99
139 #define WIN_PACKETCMD 0xA0 /* Send a packet command. */
140 #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
141 #define WIN_QUEUED_SERVICE 0xA2
142 #define WIN_SMART 0xB0 /* self-monitoring and reporting */
143 #define CFA_ERASE_SECTORS 0xC0
144 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
145 #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
146 #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
147 #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
148 #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
149 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
150 #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
151 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
152 #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
153 #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
154 #define WIN_GETMEDIASTATUS 0xDA
155 #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
156 #define WIN_POSTBOOT 0xDC
157 #define WIN_PREBOOT 0xDD
158 #define WIN_DOORLOCK 0xDE /* lock door on removable drives */
159 #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
160 #define WIN_STANDBYNOW1 0xE0
161 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
162 #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
163 #define WIN_SETIDLE1 0xE3
164 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
165 #define WIN_CHECKPOWERMODE1 0xE5
166 #define WIN_SLEEPNOW1 0xE6
167 #define WIN_FLUSH_CACHE 0xE7
168 #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
169 #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
170 /* SET_FEATURES 0x22 or 0xDD */
171 #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
172 #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
173 #define WIN_MEDIAEJECT 0xED
174 #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
175 #define WIN_SETFEATURES 0xEF /* set special drive features */
176 #define EXABYTE_ENABLE_NEST 0xF0
177 #define WIN_SECURITY_SET_PASS 0xF1
178 #define WIN_SECURITY_UNLOCK 0xF2
179 #define WIN_SECURITY_ERASE_PREPARE 0xF3
180 #define WIN_SECURITY_ERASE_UNIT 0xF4
181 #define WIN_SECURITY_FREEZE_LOCK 0xF5
182 #define WIN_SECURITY_DISABLE 0xF6
183 #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
184 #define WIN_SET_MAX 0xF9
185 #define DISABLE_SEAGATE 0xFB
187 /* set to 1 set disable mult support */
188 #define MAX_MULT_SECTORS 16
192 #define ATAPI_PACKET_SIZE 12
194 /* The generic packet command opcodes for CD/DVD Logical Units,
195 * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
196 #define GPCMD_BLANK 0xa1
197 #define GPCMD_CLOSE_TRACK 0x5b
198 #define GPCMD_FLUSH_CACHE 0x35
199 #define GPCMD_FORMAT_UNIT 0x04
200 #define GPCMD_GET_CONFIGURATION 0x46
201 #define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
202 #define GPCMD_GET_PERFORMANCE 0xac
203 #define GPCMD_INQUIRY 0x12
204 #define GPCMD_LOAD_UNLOAD 0xa6
205 #define GPCMD_MECHANISM_STATUS 0xbd
206 #define GPCMD_MODE_SELECT_10 0x55
207 #define GPCMD_MODE_SENSE_10 0x5a
208 #define GPCMD_PAUSE_RESUME 0x4b
209 #define GPCMD_PLAY_AUDIO_10 0x45
210 #define GPCMD_PLAY_AUDIO_MSF 0x47
211 #define GPCMD_PLAY_AUDIO_TI 0x48
212 #define GPCMD_PLAY_CD 0xbc
213 #define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e
214 #define GPCMD_READ_10 0x28
215 #define GPCMD_READ_12 0xa8
216 #define GPCMD_READ_CDVD_CAPACITY 0x25
217 #define GPCMD_READ_CD 0xbe
218 #define GPCMD_READ_CD_MSF 0xb9
219 #define GPCMD_READ_DISC_INFO 0x51
220 #define GPCMD_READ_DVD_STRUCTURE 0xad
221 #define GPCMD_READ_FORMAT_CAPACITIES 0x23
222 #define GPCMD_READ_HEADER 0x44
223 #define GPCMD_READ_TRACK_RZONE_INFO 0x52
224 #define GPCMD_READ_SUBCHANNEL 0x42
225 #define GPCMD_READ_TOC_PMA_ATIP 0x43
226 #define GPCMD_REPAIR_RZONE_TRACK 0x58
227 #define GPCMD_REPORT_KEY 0xa4
228 #define GPCMD_REQUEST_SENSE 0x03
229 #define GPCMD_RESERVE_RZONE_TRACK 0x53
230 #define GPCMD_SCAN 0xba
231 #define GPCMD_SEEK 0x2b
232 #define GPCMD_SEND_DVD_STRUCTURE 0xad
233 #define GPCMD_SEND_EVENT 0xa2
234 #define GPCMD_SEND_KEY 0xa3
235 #define GPCMD_SEND_OPC 0x54
236 #define GPCMD_SET_READ_AHEAD 0xa7
237 #define GPCMD_SET_STREAMING 0xb6
238 #define GPCMD_START_STOP_UNIT 0x1b
239 #define GPCMD_STOP_PLAY_SCAN 0x4e
240 #define GPCMD_TEST_UNIT_READY 0x00
241 #define GPCMD_VERIFY_10 0x2f
242 #define GPCMD_WRITE_10 0x2a
243 #define GPCMD_WRITE_AND_VERIFY_10 0x2e
244 /* This is listed as optional in ATAPI 2.6, but is (curiously)
245 * missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
246 * Table 377 as an MMC command for SCSi devices though... Most ATAPI
247 * drives support it. */
248 #define GPCMD_SET_SPEED 0xbb
249 /* This seems to be a SCSI specific CD-ROM opcode
250 * to play data at track/index */
251 #define GPCMD_PLAYAUDIO_TI 0x48
253 * From MS Media Status Notification Support Specification. For
256 #define GPCMD_GET_MEDIA_STATUS 0xda
258 /* Mode page codes for mode sense/set */
259 #define GPMODE_R_W_ERROR_PAGE 0x01
260 #define GPMODE_WRITE_PARMS_PAGE 0x05
261 #define GPMODE_AUDIO_CTL_PAGE 0x0e
262 #define GPMODE_POWER_PAGE 0x1a
263 #define GPMODE_FAULT_FAIL_PAGE 0x1c
264 #define GPMODE_TO_PROTECT_PAGE 0x1d
265 #define GPMODE_CAPABILITIES_PAGE 0x2a
266 #define GPMODE_ALL_PAGES 0x3f
267 /* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
268 * of MODE_SENSE_POWER_PAGE */
269 #define GPMODE_CDROM_PAGE 0x0d
271 #define ATAPI_INT_REASON_CD 0x01 /* 0 = data transfer */
272 #define ATAPI_INT_REASON_IO 0x02 /* 1 = transfer to the host */
273 #define ATAPI_INT_REASON_REL 0x04
274 #define ATAPI_INT_REASON_TAG 0xf8
276 /* same constants as bochs */
277 #define ASC_ILLEGAL_OPCODE 0x20
278 #define ASC_LOGICAL_BLOCK_OOR 0x21
279 #define ASC_INV_FIELD_IN_CMD_PACKET 0x24
280 #define ASC_MEDIUM_NOT_PRESENT 0x3a
281 #define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39
284 #define SENSE_NOT_READY 2
285 #define SENSE_ILLEGAL_REQUEST 5
286 #define SENSE_UNIT_ATTENTION 6
290 typedef void EndTransferFunc(struct IDEState *);
292 /* NOTE: IDEState represents in fact one drive */
293 typedef struct IDEState {
296 int cylinders, heads, sectors;
302 struct BMDMAState *bmdma;
307 uint16_t nsector; /* 0 is 256 to ease computations */
313 /* 0x3f6 command, only meaningful for drive 0 */
315 /* depends on bit 4 in select, only meaningful for drive 0 */
316 struct IDEState *cur_drive;
317 BlockDriverState *bs;
321 int packet_transfer_size;
322 int elementary_transfer_size;
326 int atapi_dma; /* true if dma is requested for the packet cmd */
329 /* PIO transfer handling */
330 int req_nb_sectors; /* number of sectors per interrupt */
331 EndTransferFunc *end_transfer_func;
334 uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
337 #define BM_STATUS_DMAING 0x01
338 #define BM_STATUS_ERROR 0x02
339 #define BM_STATUS_INT 0x04
341 #define BM_CMD_START 0x01
342 #define BM_CMD_READ 0x08
344 typedef int IDEDMAFunc(IDEState *s,
345 target_phys_addr_t phys_addr,
348 typedef struct BMDMAState {
352 /* current transfer state */
357 typedef struct PCIIDEState {
363 static void ide_dma_start(IDEState *s, IDEDMAFunc *dma_cb);
365 static void padstr(char *str, const char *src, int len)
368 for(i = 0; i < len; i++) {
373 *(char *)((long)str ^ 1) = v;
378 static void padstr8(uint8_t *buf, int buf_size, const char *src)
381 for(i = 0; i < buf_size; i++) {
389 static void put_le16(uint16_t *p, unsigned int v)
394 static void ide_identify(IDEState *s)
397 unsigned int oldsize;
400 memset(s->io_buffer, 0, 512);
401 p = (uint16_t *)s->io_buffer;
402 put_le16(p + 0, 0x0040);
403 put_le16(p + 1, s->cylinders);
404 put_le16(p + 3, s->heads);
405 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
406 put_le16(p + 5, 512); /* XXX: retired, remove ? */
407 put_le16(p + 6, s->sectors);
408 snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
409 padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
410 put_le16(p + 20, 3); /* XXX: retired, remove ? */
411 put_le16(p + 21, 512); /* cache size in sectors */
412 put_le16(p + 22, 4); /* ecc bytes */
413 padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
414 padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); /* model */
415 #if MAX_MULT_SECTORS > 1
416 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
418 put_le16(p + 48, 1); /* dword I/O */
419 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
420 put_le16(p + 51, 0x200); /* PIO transfer cycle */
421 put_le16(p + 52, 0x200); /* DMA transfer cycle */
422 put_le16(p + 53, 1 | 1 << 2); /* words 54-58,88 are valid */
423 put_le16(p + 54, s->cylinders);
424 put_le16(p + 55, s->heads);
425 put_le16(p + 56, s->sectors);
426 oldsize = s->cylinders * s->heads * s->sectors;
427 put_le16(p + 57, oldsize);
428 put_le16(p + 58, oldsize >> 16);
430 put_le16(p + 59, 0x100 | s->mult_sectors);
431 put_le16(p + 60, s->nb_sectors);
432 put_le16(p + 61, s->nb_sectors >> 16);
433 put_le16(p + 80, (1 << 1) | (1 << 2));
434 put_le16(p + 82, (1 << 14));
435 put_le16(p + 83, (1 << 14));
436 put_le16(p + 84, (1 << 14));
437 put_le16(p + 85, (1 << 14));
439 put_le16(p + 87, (1 << 14));
440 put_le16(p + 88, 0x1f | (1 << 13));
441 put_le16(p + 93, 1 | (1 << 14) | 0x2000 | 0x4000);
444 static void ide_atapi_identify(IDEState *s)
449 memset(s->io_buffer, 0, 512);
450 p = (uint16_t *)s->io_buffer;
451 /* Removable CDROM, 50us response, 12 byte packets */
452 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
453 snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
454 padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
455 put_le16(p + 20, 3); /* buffer type */
456 put_le16(p + 21, 512); /* cache size in sectors */
457 put_le16(p + 22, 4); /* ecc bytes */
458 padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
459 padstr((uint8_t *)(p + 27), "QEMU CD-ROM", 40); /* model */
460 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
461 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
462 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
463 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
464 put_le16(p + 64, 1); /* PIO modes */
465 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
466 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
467 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
468 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
470 put_le16(p + 71, 30); /* in ns */
471 put_le16(p + 72, 30); /* in ns */
473 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
476 static void ide_set_signature(IDEState *s)
478 s->select &= 0xf0; /* clear head */
494 static inline void ide_abort_command(IDEState *s)
496 s->status = READY_STAT | ERR_STAT;
500 static inline void ide_set_irq(IDEState *s)
502 if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
505 openpic_set_irq(s->openpic, s->irq, 1);
509 pci_set_irq(s->pci_dev, 0, 1);
511 pic_set_irq(s->irq, 1);
515 /* prepare data transfer and tell what to do after */
516 static void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
517 EndTransferFunc *end_transfer_func)
519 s->end_transfer_func = end_transfer_func;
521 s->data_end = buf + size;
522 s->status |= DRQ_STAT;
525 static void ide_transfer_stop(IDEState *s)
527 s->end_transfer_func = ide_transfer_stop;
528 s->data_ptr = s->io_buffer;
529 s->data_end = s->io_buffer;
530 s->status &= ~DRQ_STAT;
533 static int64_t ide_get_sector(IDEState *s)
536 if (s->select & 0x40) {
538 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
539 (s->lcyl << 8) | s->sector;
541 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
542 (s->select & 0x0f) * s->sectors +
548 static void ide_set_sector(IDEState *s, int64_t sector_num)
551 if (s->select & 0x40) {
552 s->select = (s->select & 0xf0) | (sector_num >> 24);
553 s->hcyl = (sector_num >> 16);
554 s->lcyl = (sector_num >> 8);
555 s->sector = (sector_num);
557 cyl = sector_num / (s->heads * s->sectors);
558 r = sector_num % (s->heads * s->sectors);
561 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
562 s->sector = (r % s->sectors) + 1;
566 static void ide_sector_read(IDEState *s)
571 s->status = READY_STAT | SEEK_STAT;
572 s->error = 0; /* not needed by IDE spec, but needed by Windows */
573 sector_num = ide_get_sector(s);
576 /* no more sector to read from disk */
577 ide_transfer_stop(s);
579 #if defined(DEBUG_IDE)
580 printf("read sector=%Ld\n", sector_num);
582 if (n > s->req_nb_sectors)
583 n = s->req_nb_sectors;
584 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
585 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
587 ide_set_sector(s, sector_num + n);
592 static int ide_read_dma_cb(IDEState *s,
593 target_phys_addr_t phys_addr,
596 int len, transfer_size, n;
599 transfer_size = transfer_size1;
600 while (transfer_size > 0) {
601 len = s->io_buffer_size - s->io_buffer_index;
603 /* transfert next data */
607 if (n > MAX_MULT_SECTORS)
608 n = MAX_MULT_SECTORS;
609 sector_num = ide_get_sector(s);
610 bdrv_read(s->bs, sector_num, s->io_buffer, n);
611 s->io_buffer_index = 0;
612 s->io_buffer_size = n * 512;
613 len = s->io_buffer_size;
615 ide_set_sector(s, sector_num);
618 if (len > transfer_size)
620 cpu_physical_memory_write(phys_addr,
621 s->io_buffer + s->io_buffer_index, len);
622 s->io_buffer_index += len;
623 transfer_size -= len;
626 if (s->io_buffer_index >= s->io_buffer_size && s->nsector == 0) {
627 s->status = READY_STAT | SEEK_STAT;
629 #ifdef DEBUG_IDE_ATAPI
630 printf("dma status=0x%x\n", s->status);
634 return transfer_size1 - transfer_size;
637 static void ide_sector_read_dma(IDEState *s)
639 s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
640 s->io_buffer_index = 0;
641 s->io_buffer_size = 0;
642 ide_dma_start(s, ide_read_dma_cb);
645 static void ide_sector_write(IDEState *s)
650 s->status = READY_STAT | SEEK_STAT;
651 sector_num = ide_get_sector(s);
652 #if defined(DEBUG_IDE)
653 printf("write sector=%Ld\n", sector_num);
656 if (n > s->req_nb_sectors)
657 n = s->req_nb_sectors;
658 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
660 if (s->nsector == 0) {
661 /* no more sector to write */
662 ide_transfer_stop(s);
665 if (n1 > s->req_nb_sectors)
666 n1 = s->req_nb_sectors;
667 ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
669 ide_set_sector(s, sector_num + n);
673 static int ide_write_dma_cb(IDEState *s,
674 target_phys_addr_t phys_addr,
677 int len, transfer_size, n;
680 transfer_size = transfer_size1;
682 len = s->io_buffer_size - s->io_buffer_index;
684 n = s->io_buffer_size >> 9;
685 sector_num = ide_get_sector(s);
686 bdrv_write(s->bs, sector_num, s->io_buffer,
687 s->io_buffer_size >> 9);
689 ide_set_sector(s, sector_num);
693 /* end of transfer */
694 s->status = READY_STAT | SEEK_STAT;
698 if (n > MAX_MULT_SECTORS)
699 n = MAX_MULT_SECTORS;
700 s->io_buffer_index = 0;
701 s->io_buffer_size = n * 512;
702 len = s->io_buffer_size;
704 if (transfer_size <= 0)
706 if (len > transfer_size)
708 cpu_physical_memory_read(phys_addr,
709 s->io_buffer + s->io_buffer_index, len);
710 s->io_buffer_index += len;
711 transfer_size -= len;
714 return transfer_size1 - transfer_size;
717 static void ide_sector_write_dma(IDEState *s)
720 s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
722 if (n > MAX_MULT_SECTORS)
723 n = MAX_MULT_SECTORS;
724 s->io_buffer_index = 0;
725 s->io_buffer_size = n * 512;
726 ide_dma_start(s, ide_write_dma_cb);
729 static void ide_atapi_cmd_ok(IDEState *s)
732 s->status = READY_STAT;
733 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
737 static void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
739 #ifdef DEBUG_IDE_ATAPI
740 printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
742 s->error = sense_key << 4;
743 s->status = READY_STAT | ERR_STAT;
744 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
745 s->sense_key = sense_key;
750 static inline void cpu_to_ube16(uint8_t *buf, int val)
756 static inline void cpu_to_ube32(uint8_t *buf, unsigned int val)
764 static inline int ube16_to_cpu(const uint8_t *buf)
766 return (buf[0] << 8) | buf[1];
769 static inline int ube32_to_cpu(const uint8_t *buf)
771 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
774 static void lba_to_msf(uint8_t *buf, int lba)
777 buf[0] = (lba / 75) / 60;
778 buf[1] = (lba / 75) % 60;
782 static void cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf,
785 switch(sector_size) {
787 bdrv_read(bs, (int64_t)lba << 2, buf, 4);
792 memset(buf + 1, 0xff, 11);
795 lba_to_msf(buf, lba);
796 buf[3] = 0x01; /* mode 1 data */
799 bdrv_read(bs, (int64_t)lba << 2, buf, 4);
809 /* The whole ATAPI transfer logic is handled in this function */
810 static void ide_atapi_cmd_reply_end(IDEState *s)
812 int byte_count_limit, size;
813 #ifdef DEBUG_IDE_ATAPI
814 printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
815 s->packet_transfer_size,
816 s->elementary_transfer_size,
819 if (s->packet_transfer_size <= 0) {
820 /* end of transfer */
821 ide_transfer_stop(s);
822 s->status = READY_STAT;
823 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
825 #ifdef DEBUG_IDE_ATAPI
826 printf("status=0x%x\n", s->status);
829 /* see if a new sector must be read */
830 if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) {
831 cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
833 s->io_buffer_index = 0;
835 if (s->elementary_transfer_size > 0) {
836 /* there are some data left to transmit in this elementary
838 size = s->cd_sector_size - s->io_buffer_index;
839 if (size > s->elementary_transfer_size)
840 size = s->elementary_transfer_size;
841 ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
842 size, ide_atapi_cmd_reply_end);
843 s->packet_transfer_size -= size;
844 s->elementary_transfer_size -= size;
845 s->io_buffer_index += size;
847 /* a new transfer is needed */
848 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
849 byte_count_limit = s->lcyl | (s->hcyl << 8);
850 #ifdef DEBUG_IDE_ATAPI
851 printf("byte_count_limit=%d\n", byte_count_limit);
853 if (byte_count_limit == 0xffff)
855 size = s->packet_transfer_size;
856 if (size > byte_count_limit) {
857 /* byte count limit must be even if this case */
858 if (byte_count_limit & 1)
860 size = byte_count_limit;
864 s->elementary_transfer_size = size;
865 /* we cannot transmit more than one sector at a time */
867 if (size > (s->cd_sector_size - s->io_buffer_index))
868 size = (s->cd_sector_size - s->io_buffer_index);
870 ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
871 size, ide_atapi_cmd_reply_end);
872 s->packet_transfer_size -= size;
873 s->elementary_transfer_size -= size;
874 s->io_buffer_index += size;
876 #ifdef DEBUG_IDE_ATAPI
877 printf("status=0x%x\n", s->status);
883 /* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
884 static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size)
888 s->lba = -1; /* no sector read */
889 s->packet_transfer_size = size;
890 s->elementary_transfer_size = 0;
891 s->io_buffer_index = 0;
893 s->status = READY_STAT;
894 ide_atapi_cmd_reply_end(s);
897 /* start a CD-CDROM read command */
898 static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors,
902 s->packet_transfer_size = nb_sectors * sector_size;
903 s->elementary_transfer_size = 0;
904 s->io_buffer_index = sector_size;
905 s->cd_sector_size = sector_size;
907 s->status = READY_STAT;
908 ide_atapi_cmd_reply_end(s);
911 /* ATAPI DMA support */
912 static int ide_atapi_cmd_read_dma_cb(IDEState *s,
913 target_phys_addr_t phys_addr,
916 int len, transfer_size;
918 transfer_size = transfer_size1;
919 while (transfer_size > 0) {
920 if (s->packet_transfer_size <= 0)
922 len = s->cd_sector_size - s->io_buffer_index;
924 /* transfert next data */
925 cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
927 s->io_buffer_index = 0;
928 len = s->cd_sector_size;
930 if (len > transfer_size)
932 cpu_physical_memory_write(phys_addr,
933 s->io_buffer + s->io_buffer_index, len);
934 s->packet_transfer_size -= len;
935 s->io_buffer_index += len;
936 transfer_size -= len;
939 if (s->packet_transfer_size <= 0) {
940 s->status = READY_STAT;
941 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
943 #ifdef DEBUG_IDE_ATAPI
944 printf("dma status=0x%x\n", s->status);
948 return transfer_size1 - transfer_size;
951 /* start a CD-CDROM read command with DMA */
952 /* XXX: test if DMA is available */
953 static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors,
957 s->packet_transfer_size = nb_sectors * sector_size;
958 s->io_buffer_index = sector_size;
959 s->cd_sector_size = sector_size;
961 s->status = READY_STAT | DRQ_STAT;
962 ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
965 static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors,
968 #ifdef DEBUG_IDE_ATAPI
969 printf("read: LBA=%d nb_sectors=%d\n", lba, nb_sectors);
972 ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size);
974 ide_atapi_cmd_read_pio(s, lba, nb_sectors, sector_size);
978 /* same toc as bochs. Return -1 if error or the toc length */
979 /* XXX: check this */
980 static int cdrom_read_toc(IDEState *s, uint8_t *buf, int msf, int start_track)
985 if (start_track > 1 && start_track != 0xaa)
988 *q++ = 1; /* first session */
989 *q++ = 1; /* last session */
990 if (start_track <= 1) {
991 *q++ = 0; /* reserved */
992 *q++ = 0x14; /* ADR, control */
993 *q++ = 1; /* track number */
994 *q++ = 0; /* reserved */
996 *q++ = 0; /* reserved */
997 *q++ = 0; /* minute */
998 *q++ = 2; /* second */
999 *q++ = 0; /* frame */
1006 /* lead out track */
1007 *q++ = 0; /* reserved */
1008 *q++ = 0x16; /* ADR, control */
1009 *q++ = 0xaa; /* track number */
1010 *q++ = 0; /* reserved */
1011 nb_sectors = s->nb_sectors >> 2;
1013 *q++ = 0; /* reserved */
1014 lba_to_msf(q, nb_sectors);
1017 cpu_to_ube32(q, nb_sectors);
1021 cpu_to_ube16(buf, len - 2);
1025 /* mostly same info as PearPc */
1026 static int cdrom_read_toc_raw(IDEState *s, uint8_t *buf, int msf,
1030 int nb_sectors, len;
1033 *q++ = 1; /* first session */
1034 *q++ = 1; /* last session */
1036 *q++ = 1; /* session number */
1037 *q++ = 0x14; /* data track */
1038 *q++ = 0; /* track number */
1039 *q++ = 0xa0; /* lead-in */
1042 *q++ = 0; /* frame */
1044 *q++ = 1; /* first track */
1045 *q++ = 0x00; /* disk type */
1048 *q++ = 1; /* session number */
1049 *q++ = 0x14; /* data track */
1050 *q++ = 0; /* track number */
1054 *q++ = 0; /* frame */
1056 *q++ = 1; /* last track */
1060 *q++ = 1; /* session number */
1061 *q++ = 0x14; /* data track */
1062 *q++ = 0; /* track number */
1063 *q++ = 0xa2; /* lead-out */
1066 *q++ = 0; /* frame */
1067 nb_sectors = s->nb_sectors >> 2;
1069 *q++ = 0; /* reserved */
1070 lba_to_msf(q, nb_sectors);
1073 cpu_to_ube32(q, nb_sectors);
1077 *q++ = 1; /* session number */
1078 *q++ = 0x14; /* ADR, control */
1079 *q++ = 0; /* track number */
1080 *q++ = 1; /* point */
1083 *q++ = 0; /* frame */
1090 cpu_to_ube16(buf, len - 2);
1094 static void ide_atapi_cmd(IDEState *s)
1096 const uint8_t *packet;
1100 packet = s->io_buffer;
1102 #ifdef DEBUG_IDE_ATAPI
1105 printf("ATAPI limit=0x%x packet:", s->lcyl | (s->hcyl << 8));
1106 for(i = 0; i < ATAPI_PACKET_SIZE; i++) {
1107 printf(" %02x", packet[i]);
1112 switch(s->io_buffer[0]) {
1113 case GPCMD_TEST_UNIT_READY:
1114 if (bdrv_is_inserted(s->bs)) {
1115 ide_atapi_cmd_ok(s);
1117 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1118 ASC_MEDIUM_NOT_PRESENT);
1121 case GPCMD_MODE_SENSE_10:
1124 max_len = ube16_to_cpu(packet + 7);
1125 action = packet[2] >> 6;
1126 code = packet[2] & 0x3f;
1128 case 0: /* current values */
1130 case 0x01: /* error recovery */
1131 cpu_to_ube16(&buf[0], 16 + 6);
1147 ide_atapi_cmd_reply(s, 16, max_len);
1150 cpu_to_ube16(&buf[0], 28 + 6);
1165 buf[14] = (1 << 0) | (1 << 3) | (1 << 5);
1166 if (bdrv_is_locked(s->bs))
1169 cpu_to_ube16(&buf[16], 706);
1172 cpu_to_ube16(&buf[20], 512);
1173 cpu_to_ube16(&buf[22], 706);
1178 ide_atapi_cmd_reply(s, 28, max_len);
1184 case 1: /* changeable values */
1186 case 2: /* default values */
1189 case 3: /* saved values */
1190 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1191 ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
1196 case GPCMD_REQUEST_SENSE:
1197 max_len = packet[4];
1199 buf[0] = 0x70 | (1 << 7);
1200 buf[2] = s->sense_key;
1203 ide_atapi_cmd_reply(s, 18, max_len);
1205 case GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
1206 if (bdrv_is_inserted(s->bs)) {
1207 bdrv_set_locked(s->bs, packet[4] & 1);
1208 ide_atapi_cmd_ok(s);
1210 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1211 ASC_MEDIUM_NOT_PRESENT);
1217 int nb_sectors, lba;
1219 if (!bdrv_is_inserted(s->bs)) {
1220 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1221 ASC_MEDIUM_NOT_PRESENT);
1224 if (packet[0] == GPCMD_READ_10)
1225 nb_sectors = ube16_to_cpu(packet + 7);
1227 nb_sectors = ube32_to_cpu(packet + 6);
1228 lba = ube32_to_cpu(packet + 2);
1229 if (nb_sectors == 0) {
1230 ide_atapi_cmd_ok(s);
1233 if (((int64_t)(lba + nb_sectors) << 2) > s->nb_sectors) {
1234 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1235 ASC_LOGICAL_BLOCK_OOR);
1238 ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1243 int nb_sectors, lba, transfer_request;
1245 if (!bdrv_is_inserted(s->bs)) {
1246 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1247 ASC_MEDIUM_NOT_PRESENT);
1250 nb_sectors = (packet[6] << 16) | (packet[7] << 8) | packet[8];
1251 lba = ube32_to_cpu(packet + 2);
1252 if (nb_sectors == 0) {
1253 ide_atapi_cmd_ok(s);
1256 if (((int64_t)(lba + nb_sectors) << 2) > s->nb_sectors) {
1257 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1258 ASC_LOGICAL_BLOCK_OOR);
1261 transfer_request = packet[9];
1262 switch(transfer_request & 0xf8) {
1265 ide_atapi_cmd_ok(s);
1269 ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1273 ide_atapi_cmd_read(s, lba, nb_sectors, 2352);
1276 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1277 ASC_INV_FIELD_IN_CMD_PACKET);
1285 if (!bdrv_is_inserted(s->bs)) {
1286 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1287 ASC_MEDIUM_NOT_PRESENT);
1290 lba = ube32_to_cpu(packet + 2);
1291 if (((int64_t)lba << 2) > s->nb_sectors) {
1292 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1293 ASC_LOGICAL_BLOCK_OOR);
1296 ide_atapi_cmd_ok(s);
1299 case GPCMD_START_STOP_UNIT:
1302 start = packet[4] & 1;
1303 eject = (packet[4] >> 1) & 1;
1305 if (eject && !start) {
1306 /* eject the disk */
1309 ide_atapi_cmd_ok(s);
1312 case GPCMD_MECHANISM_STATUS:
1314 max_len = ube16_to_cpu(packet + 8);
1315 cpu_to_ube16(buf, 0);
1316 /* no current LBA */
1321 cpu_to_ube16(buf + 6, 0);
1322 ide_atapi_cmd_reply(s, 8, max_len);
1325 case GPCMD_READ_TOC_PMA_ATIP:
1327 int format, msf, start_track, len;
1329 if (!bdrv_is_inserted(s->bs)) {
1330 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1331 ASC_MEDIUM_NOT_PRESENT);
1334 max_len = ube16_to_cpu(packet + 7);
1335 format = packet[9] >> 6;
1336 msf = (packet[1] >> 1) & 1;
1337 start_track = packet[6];
1340 len = cdrom_read_toc(s, buf, msf, start_track);
1343 ide_atapi_cmd_reply(s, len, max_len);
1346 /* multi session : only a single session defined */
1351 ide_atapi_cmd_reply(s, 12, max_len);
1354 len = cdrom_read_toc_raw(s, buf, msf, start_track);
1357 ide_atapi_cmd_reply(s, len, max_len);
1361 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1362 ASC_INV_FIELD_IN_CMD_PACKET);
1367 case GPCMD_READ_CDVD_CAPACITY:
1368 if (!bdrv_is_inserted(s->bs)) {
1369 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1370 ASC_MEDIUM_NOT_PRESENT);
1373 /* NOTE: it is really the number of sectors minus 1 */
1374 cpu_to_ube32(buf, (s->nb_sectors >> 2) - 1);
1375 cpu_to_ube32(buf + 4, 2048);
1376 ide_atapi_cmd_reply(s, 8, 8);
1379 max_len = packet[4];
1380 buf[0] = 0x05; /* CD-ROM */
1381 buf[1] = 0x80; /* removable */
1382 buf[2] = 0x00; /* ISO */
1383 buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
1384 buf[4] = 31; /* additionnal length */
1385 buf[5] = 0; /* reserved */
1386 buf[6] = 0; /* reserved */
1387 buf[7] = 0; /* reserved */
1388 padstr8(buf + 8, 8, "QEMU");
1389 padstr8(buf + 16, 16, "QEMU CD-ROM");
1390 padstr8(buf + 32, 4, QEMU_VERSION);
1391 ide_atapi_cmd_reply(s, 36, max_len);
1394 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1395 ASC_ILLEGAL_OPCODE);
1400 /* called when the inserted state of the media has changed */
1401 static void cdrom_change_cb(void *opaque)
1403 IDEState *s = opaque;
1406 /* XXX: send interrupt too */
1407 bdrv_get_geometry(s->bs, &nb_sectors);
1408 s->nb_sectors = nb_sectors;
1411 static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1413 IDEState *ide_if = opaque;
1418 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1425 /* NOTE: data is written to the two drives */
1426 ide_if[0].feature = val;
1427 ide_if[1].feature = val;
1432 ide_if[0].nsector = val;
1433 ide_if[1].nsector = val;
1436 ide_if[0].sector = val;
1437 ide_if[1].sector = val;
1440 ide_if[0].lcyl = val;
1441 ide_if[1].lcyl = val;
1444 ide_if[0].hcyl = val;
1445 ide_if[1].hcyl = val;
1448 ide_if[0].select = (val & ~0x10) | 0xa0;
1449 ide_if[1].select = (val | 0x10) | 0xa0;
1451 unit = (val >> 4) & 1;
1453 ide_if->cur_drive = s;
1458 #if defined(DEBUG_IDE)
1459 printf("ide: CMD=%02x\n", val);
1461 s = ide_if->cur_drive;
1462 /* ignore commands to non existant slave */
1463 if (s != ide_if && !s->bs)
1467 if (s->bs && !s->is_cdrom) {
1469 s->status = READY_STAT | SEEK_STAT;
1470 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1473 ide_set_signature(s);
1475 ide_abort_command(s);
1482 s->status = READY_STAT | SEEK_STAT;
1486 if (s->nsector > MAX_MULT_SECTORS ||
1488 (s->nsector & (s->nsector - 1)) != 0) {
1489 ide_abort_command(s);
1491 s->mult_sectors = s->nsector;
1492 s->status = READY_STAT;
1497 case WIN_VERIFY_ONCE:
1498 /* do sector number check ? */
1499 s->status = READY_STAT;
1506 s->req_nb_sectors = 1;
1510 case WIN_WRITE_ONCE:
1512 s->status = SEEK_STAT | READY_STAT;
1513 s->req_nb_sectors = 1;
1514 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1517 if (!s->mult_sectors)
1519 s->req_nb_sectors = s->mult_sectors;
1523 if (!s->mult_sectors)
1526 s->status = SEEK_STAT | READY_STAT;
1527 s->req_nb_sectors = s->mult_sectors;
1529 if (n > s->req_nb_sectors)
1530 n = s->req_nb_sectors;
1531 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1534 case WIN_READDMA_ONCE:
1537 ide_sector_read_dma(s);
1540 case WIN_WRITEDMA_ONCE:
1543 ide_sector_write_dma(s);
1545 case WIN_READ_NATIVE_MAX:
1546 ide_set_sector(s, s->nb_sectors - 1);
1547 s->status = READY_STAT;
1550 case WIN_CHECKPOWERMODE1:
1551 s->nsector = 0xff; /* device active or idle */
1552 s->status = READY_STAT;
1555 case WIN_SETFEATURES:
1558 /* XXX: valid for CDROM ? */
1559 switch(s->feature) {
1560 case 0x02: /* write cache enable */
1561 case 0x03: /* set transfer mode */
1562 case 0x82: /* write cache disable */
1563 case 0xaa: /* read look-ahead enable */
1564 case 0x55: /* read look-ahead disable */
1565 s->status = READY_STAT | SEEK_STAT;
1572 case WIN_STANDBYNOW1:
1573 s->status = READY_STAT;
1576 /* ATAPI commands */
1579 ide_atapi_identify(s);
1580 s->status = READY_STAT;
1581 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1583 ide_abort_command(s);
1590 ide_set_signature(s);
1591 s->status = 0x00; /* NOTE: READY is _not_ set */
1597 /* overlapping commands not supported */
1598 if (s->feature & 0x02)
1600 s->atapi_dma = s->feature & 1;
1602 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1607 ide_abort_command(s);
1614 static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1616 IDEState *ide_if = opaque;
1617 IDEState *s = ide_if->cur_drive;
1627 if (!ide_if[0].bs && !ide_if[1].bs)
1633 if (!ide_if[0].bs && !ide_if[1].bs)
1636 ret = s->nsector & 0xff;
1639 if (!ide_if[0].bs && !ide_if[1].bs)
1645 if (!ide_if[0].bs && !ide_if[1].bs)
1651 if (!ide_if[0].bs && !ide_if[1].bs)
1657 if (!ide_if[0].bs && !ide_if[1].bs)
1664 if ((!ide_if[0].bs && !ide_if[1].bs) ||
1665 (s != ide_if && !s->bs))
1671 openpic_set_irq(s->openpic, s->irq, 0);
1675 pci_set_irq(s->pci_dev, 0, 0);
1677 pic_set_irq(s->irq, 0);
1681 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1686 static uint32_t ide_status_read(void *opaque, uint32_t addr)
1688 IDEState *ide_if = opaque;
1689 IDEState *s = ide_if->cur_drive;
1692 if ((!ide_if[0].bs && !ide_if[1].bs) ||
1693 (s != ide_if && !s->bs))
1698 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1703 static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1705 IDEState *ide_if = opaque;
1710 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1712 /* common for both drives */
1713 if (!(ide_if[0].cmd & IDE_CMD_RESET) &&
1714 (val & IDE_CMD_RESET)) {
1715 /* reset low to high */
1716 for(i = 0;i < 2; i++) {
1718 s->status = BUSY_STAT | SEEK_STAT;
1721 } else if ((ide_if[0].cmd & IDE_CMD_RESET) &&
1722 !(val & IDE_CMD_RESET)) {
1724 for(i = 0;i < 2; i++) {
1727 s->status = 0x00; /* NOTE: READY is _not_ set */
1729 s->status = READY_STAT | SEEK_STAT;
1730 ide_set_signature(s);
1734 ide_if[0].cmd = val;
1735 ide_if[1].cmd = val;
1738 static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1740 IDEState *s = ((IDEState *)opaque)->cur_drive;
1744 *(uint16_t *)p = le16_to_cpu(val);
1747 if (p >= s->data_end)
1748 s->end_transfer_func(s);
1751 static uint32_t ide_data_readw(void *opaque, uint32_t addr)
1753 IDEState *s = ((IDEState *)opaque)->cur_drive;
1757 ret = cpu_to_le16(*(uint16_t *)p);
1760 if (p >= s->data_end)
1761 s->end_transfer_func(s);
1765 static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
1767 IDEState *s = ((IDEState *)opaque)->cur_drive;
1771 *(uint32_t *)p = le32_to_cpu(val);
1774 if (p >= s->data_end)
1775 s->end_transfer_func(s);
1778 static uint32_t ide_data_readl(void *opaque, uint32_t addr)
1780 IDEState *s = ((IDEState *)opaque)->cur_drive;
1785 ret = cpu_to_le32(*(uint32_t *)p);
1788 if (p >= s->data_end)
1789 s->end_transfer_func(s);
1793 static void ide_dummy_transfer_stop(IDEState *s)
1795 s->data_ptr = s->io_buffer;
1796 s->data_end = s->io_buffer;
1797 s->io_buffer[0] = 0xff;
1798 s->io_buffer[1] = 0xff;
1799 s->io_buffer[2] = 0xff;
1800 s->io_buffer[3] = 0xff;
1803 static void ide_reset(IDEState *s)
1805 s->mult_sectors = MAX_MULT_SECTORS;
1808 s->status = READY_STAT;
1809 ide_set_signature(s);
1810 /* init the transfer handler so that 0xffff is returned on data
1812 s->end_transfer_func = ide_dummy_transfer_stop;
1813 ide_dummy_transfer_stop(s);
1817 uint8_t boot_ind; /* 0x80 - active */
1818 uint8_t head; /* starting head */
1819 uint8_t sector; /* starting sector */
1820 uint8_t cyl; /* starting cylinder */
1821 uint8_t sys_ind; /* What partition type */
1822 uint8_t end_head; /* end head */
1823 uint8_t end_sector; /* end sector */
1824 uint8_t end_cyl; /* end cylinder */
1825 uint32_t start_sect; /* starting sector counting from 0 */
1826 uint32_t nr_sects; /* nr of sectors in partition */
1827 } __attribute__((packed));
1829 /* try to guess the disk logical geometry from the MSDOS partition table. Return 0 if OK, -1 if could not guess */
1830 static int guess_disk_lchs(IDEState *s,
1831 int *pcylinders, int *pheads, int *psectors)
1834 int ret, i, heads, sectors, cylinders;
1835 struct partition *p;
1838 ret = bdrv_read(s->bs, 0, buf, 1);
1841 /* test msdos magic */
1842 if (buf[510] != 0x55 || buf[511] != 0xaa)
1844 for(i = 0; i < 4; i++) {
1845 p = ((struct partition *)(buf + 0x1be)) + i;
1846 nr_sects = le32_to_cpu(p->nr_sects);
1847 if (nr_sects && p->end_head) {
1848 /* We make the assumption that the partition terminates on
1849 a cylinder boundary */
1850 heads = p->end_head + 1;
1851 sectors = p->end_sector & 63;
1854 cylinders = s->nb_sectors / (heads * sectors);
1855 if (cylinders < 1 || cylinders > 16383)
1858 *psectors = sectors;
1859 *pcylinders = cylinders;
1861 printf("guessed geometry: LCHS=%d %d %d\n",
1862 cylinders, heads, sectors);
1870 static void ide_init2(IDEState *ide_state, int irq,
1871 BlockDriverState *hd0, BlockDriverState *hd1)
1874 static int drive_serial = 1;
1875 int i, cylinders, heads, secs, translation;
1878 for(i = 0; i < 2; i++) {
1885 bdrv_get_geometry(s->bs, &nb_sectors);
1886 s->nb_sectors = nb_sectors;
1887 /* if a geometry hint is available, use it */
1888 bdrv_get_geometry_hint(s->bs, &cylinders, &heads, &secs);
1889 if (cylinders != 0) {
1890 s->cylinders = cylinders;
1894 if (guess_disk_lchs(s, &cylinders, &heads, &secs) == 0) {
1896 /* if heads > 16, it means that a BIOS LBA
1897 translation was active, so the default
1898 hardware geometry is OK */
1899 goto default_geometry;
1901 s->cylinders = cylinders;
1904 /* disable any translation to be in sync with
1905 the logical geometry */
1906 translation = bdrv_get_translation_hint(s->bs);
1907 if (translation == BIOS_ATA_TRANSLATION_AUTO) {
1908 bdrv_set_translation_hint(s->bs,
1909 BIOS_ATA_TRANSLATION_NONE);
1914 /* if no geometry, use a standard physical disk geometry */
1915 cylinders = nb_sectors / (16 * 63);
1916 if (cylinders > 16383)
1918 else if (cylinders < 2)
1920 s->cylinders = cylinders;
1924 bdrv_set_geometry_hint(s->bs, s->cylinders, s->heads, s->sectors);
1926 if (bdrv_get_type_hint(s->bs) == BDRV_TYPE_CDROM) {
1928 bdrv_set_change_cb(s->bs, cdrom_change_cb, s);
1931 s->drive_serial = drive_serial++;
1937 static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2)
1939 register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state);
1940 register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state);
1942 register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
1943 register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
1947 register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
1948 register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
1949 register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state);
1950 register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
1953 /***********************************************************/
1954 /* ISA IDE definitions */
1956 void isa_ide_init(int iobase, int iobase2, int irq,
1957 BlockDriverState *hd0, BlockDriverState *hd1)
1959 IDEState *ide_state;
1961 ide_state = qemu_mallocz(sizeof(IDEState) * 2);
1965 ide_init2(ide_state, irq, hd0, hd1);
1966 ide_init_ioport(ide_state, iobase, iobase2);
1969 /***********************************************************/
1970 /* PCI IDE definitions */
1972 static void ide_map(PCIDevice *pci_dev, int region_num,
1973 uint32_t addr, uint32_t size, int type)
1975 PCIIDEState *d = (PCIIDEState *)pci_dev;
1976 IDEState *ide_state;
1978 if (region_num <= 3) {
1979 ide_state = &d->ide_if[(region_num >> 1) * 2];
1980 if (region_num & 1) {
1981 register_ioport_read(addr + 2, 1, 1, ide_status_read, ide_state);
1982 register_ioport_write(addr + 2, 1, 1, ide_cmd_write, ide_state);
1984 register_ioport_write(addr, 8, 1, ide_ioport_write, ide_state);
1985 register_ioport_read(addr, 8, 1, ide_ioport_read, ide_state);
1988 register_ioport_write(addr, 2, 2, ide_data_writew, ide_state);
1989 register_ioport_read(addr, 2, 2, ide_data_readw, ide_state);
1990 register_ioport_write(addr, 4, 4, ide_data_writel, ide_state);
1991 register_ioport_read(addr, 4, 4, ide_data_readl, ide_state);
1996 /* XXX: full callback usage to prepare non blocking I/Os support -
1998 static void ide_dma_loop(BMDMAState *bm)
2004 target_phys_addr_t cur_addr;
2007 cur_addr = bm->addr;
2008 /* at most one page to avoid hanging if erroneous parameters */
2009 for(i = 0; i < 512; i++) {
2010 cpu_physical_memory_read(cur_addr, (uint8_t *)&prd, 8);
2011 prd.addr = le32_to_cpu(prd.addr);
2012 prd.size = le32_to_cpu(prd.size);
2014 printf("ide: dma: prd: %08x: addr=0x%08x size=0x%08x\n",
2015 (int)cur_addr, prd.addr, prd.size);
2017 len = prd.size & 0xfffe;
2021 len1 = bm->dma_cb(bm->ide_if, prd.addr, len);
2027 /* end of transfer */
2028 if (prd.size & 0x80000000)
2032 /* end of transfer */
2034 bm->status &= ~BM_STATUS_DMAING;
2035 bm->status |= BM_STATUS_INT;
2040 static void ide_dma_start(IDEState *s, IDEDMAFunc *dma_cb)
2042 BMDMAState *bm = s->bmdma;
2046 bm->dma_cb = dma_cb;
2047 if (bm->status & BM_STATUS_DMAING) {
2052 static uint32_t bmdma_cmd_readb(void *opaque, uint32_t addr)
2054 BMDMAState *bm = opaque;
2058 printf("%s: 0x%08x\n", __func__, val);
2063 static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
2065 BMDMAState *bm = opaque;
2067 printf("%s: 0x%08x\n", __func__, val);
2069 if (!(val & BM_CMD_START)) {
2070 /* XXX: do it better */
2071 bm->status &= ~BM_STATUS_DMAING;
2072 bm->cmd = val & 0x09;
2074 bm->status |= BM_STATUS_DMAING;
2075 bm->cmd = val & 0x09;
2076 /* start dma transfer if possible */
2082 static uint32_t bmdma_status_readb(void *opaque, uint32_t addr)
2084 BMDMAState *bm = opaque;
2088 printf("%s: 0x%08x\n", __func__, val);
2093 static void bmdma_status_writeb(void *opaque, uint32_t addr, uint32_t val)
2095 BMDMAState *bm = opaque;
2097 printf("%s: 0x%08x\n", __func__, val);
2099 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
2102 static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
2104 BMDMAState *bm = opaque;
2108 printf("%s: 0x%08x\n", __func__, val);
2113 static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
2115 BMDMAState *bm = opaque;
2117 printf("%s: 0x%08x\n", __func__, val);
2119 bm->addr = val & ~3;
2122 static void bmdma_map(PCIDevice *pci_dev, int region_num,
2123 uint32_t addr, uint32_t size, int type)
2125 PCIIDEState *d = (PCIIDEState *)pci_dev;
2128 for(i = 0;i < 2; i++) {
2129 BMDMAState *bm = &d->bmdma[i];
2130 d->ide_if[2 * i].bmdma = bm;
2131 d->ide_if[2 * i + 1].bmdma = bm;
2133 register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
2134 register_ioport_read(addr, 1, 1, bmdma_cmd_readb, bm);
2136 register_ioport_write(addr + 2, 1, 1, bmdma_status_writeb, bm);
2137 register_ioport_read(addr + 2, 1, 1, bmdma_status_readb, bm);
2139 register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
2140 register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
2145 /* hd_table must contain 4 block drivers */
2146 void pci_ide_init(PCIBus *bus, BlockDriverState **hd_table)
2152 d = (PCIIDEState *)pci_register_device(bus, "IDE", sizeof(PCIIDEState),
2155 pci_conf = d->dev.config;
2156 pci_conf[0x00] = 0x86; // Intel
2157 pci_conf[0x01] = 0x80;
2158 pci_conf[0x02] = 0x00; // fake
2159 pci_conf[0x03] = 0x01; // fake
2160 pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2161 pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2162 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
2164 pci_conf[0x2c] = 0x86; // subsys vendor
2165 pci_conf[0x2d] = 0x80; // subsys vendor
2166 pci_conf[0x2e] = 0x00; // fake
2167 pci_conf[0x2f] = 0x01; // fake
2169 pci_register_io_region((PCIDevice *)d, 0, 0x8,
2170 PCI_ADDRESS_SPACE_IO, ide_map);
2171 pci_register_io_region((PCIDevice *)d, 1, 0x4,
2172 PCI_ADDRESS_SPACE_IO, ide_map);
2173 pci_register_io_region((PCIDevice *)d, 2, 0x8,
2174 PCI_ADDRESS_SPACE_IO, ide_map);
2175 pci_register_io_region((PCIDevice *)d, 3, 0x4,
2176 PCI_ADDRESS_SPACE_IO, ide_map);
2177 pci_register_io_region((PCIDevice *)d, 4, 0x10,
2178 PCI_ADDRESS_SPACE_IO, bmdma_map);
2180 pci_conf[0x3d] = 0x01; // interrupt on pin 1
2182 for(i = 0; i < 4; i++)
2183 d->ide_if[i].pci_dev = (PCIDevice *)d;
2184 ide_init2(&d->ide_if[0], 16, hd_table[0], hd_table[1]);
2185 ide_init2(&d->ide_if[2], 16, hd_table[2], hd_table[3]);
2188 /* hd_table must contain 4 block drivers */
2189 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
2190 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table)
2195 /* register a function 1 of PIIX3 */
2196 d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
2197 sizeof(PCIIDEState),
2198 ((PCIDevice *)piix3_state)->devfn + 1,
2200 pci_conf = d->dev.config;
2201 pci_conf[0x00] = 0x86; // Intel
2202 pci_conf[0x01] = 0x80;
2203 pci_conf[0x02] = 0x10;
2204 pci_conf[0x03] = 0x70;
2205 pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2206 pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2207 pci_conf[0x0e] = 0x00; // header_type
2209 pci_register_io_region((PCIDevice *)d, 4, 0x10,
2210 PCI_ADDRESS_SPACE_IO, bmdma_map);
2212 ide_init2(&d->ide_if[0], 14, hd_table[0], hd_table[1]);
2213 ide_init2(&d->ide_if[2], 15, hd_table[2], hd_table[3]);
2214 ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
2215 ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
2218 /***********************************************************/
2219 /* MacIO based PowerPC IDE */
2221 /* PowerMac IDE memory IO */
2222 static void pmac_ide_writeb (void *opaque,
2223 target_phys_addr_t addr, uint32_t val)
2225 addr = (addr & 0xFFF) >> 4;
2228 ide_ioport_write(opaque, addr, val);
2232 ide_cmd_write(opaque, 0, val);
2239 static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
2243 addr = (addr & 0xFFF) >> 4;
2246 retval = ide_ioport_read(opaque, addr);
2250 retval = ide_status_read(opaque, 0);
2259 static void pmac_ide_writew (void *opaque,
2260 target_phys_addr_t addr, uint32_t val)
2262 addr = (addr & 0xFFF) >> 4;
2263 #ifdef TARGET_WORDS_BIGENDIAN
2267 ide_data_writew(opaque, 0, val);
2271 static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
2275 addr = (addr & 0xFFF) >> 4;
2277 retval = ide_data_readw(opaque, 0);
2281 #ifdef TARGET_WORDS_BIGENDIAN
2282 retval = bswap16(retval);
2287 static void pmac_ide_writel (void *opaque,
2288 target_phys_addr_t addr, uint32_t val)
2290 addr = (addr & 0xFFF) >> 4;
2291 #ifdef TARGET_WORDS_BIGENDIAN
2295 ide_data_writel(opaque, 0, val);
2299 static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
2303 addr = (addr & 0xFFF) >> 4;
2305 retval = ide_data_readl(opaque, 0);
2307 retval = 0xFFFFFFFF;
2309 #ifdef TARGET_WORDS_BIGENDIAN
2310 retval = bswap32(retval);
2315 static CPUWriteMemoryFunc *pmac_ide_write[] = {
2321 static CPUReadMemoryFunc *pmac_ide_read[] = {
2327 /* hd_table must contain 4 block drivers */
2328 /* PowerMac uses memory mapped registers, not I/O. Return the memory
2329 I/O index to access the ide. */
2330 int pmac_ide_init (BlockDriverState **hd_table,
2331 openpic_t *openpic, int irq)
2334 int pmac_ide_memory;
2336 ide_if = qemu_mallocz(sizeof(IDEState) * 2);
2337 ide_init2(&ide_if[0], irq, hd_table[0], hd_table[1]);
2338 ide_if[0].openpic = openpic;
2339 ide_if[1].openpic = openpic;
2341 pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
2342 pmac_ide_write, &ide_if[0]);
2343 return pmac_ide_memory;