ArDrone SDK 1.8 added
[mardrone] / mardrone / ARDrone_SDK_Version_1_8_20110726 / ARDroneLib / VLIB / Platform / arm9 / video_dct_p5p.h
1 #ifndef _VIDEO_DCT_P5P_H_
2 #define _VIDEO_DCT_P5P_H_
3
4 // #include <VP_Os/vp_os_types.h>
5 #include <VLIB/video_dct.h>
6
7 ////////////////////////////////////////////////////
8 // Parrot proprietary DCT registers
9 ////////////////////////////////////////////////////
10
11 // Parrot DCT address: 0xD00B0000
12 #define DCT_STATUS              0x000       // Status Register
13 #define DCT_ITEN                0x004       // Interrupt Enable Register
14 #define DCT_ITACK               0x008       // Interrupt Acknowledge Register
15 #define DCT_CONTROL             0x00C       // Control Register
16 #define DCT_DMA                 0x010       // Dma Register
17 #define DCT_ORIG_Y_ADDR         0x014       // Address Register
18 #define DCT_ORIG_CU_ADDR        0x018       // Address Register
19 #define DCT_ORIG_CV_ADDR        0x01C       // Address Register
20 #define DCT_DEST_Y_ADDR         0x020       // Address Register
21 #define DCT_DEST_CU_ADDR        0x024       // Address Register
22 #define DCT_DEST_CV_ADDR        0x028       // Address Register
23 #define DCT_LINEOFFSET          0x02C       // Line size
24 #define DCT_DEBUG               0x030       // Debug register
25 #define DCT_SIGNATURE           0x034       // Signature Register
26
27
28 // Registers bitwise definitions
29 // Status register
30 #define DCT_STATUS_END_OK    (1<<0)        // DCT Done
31 #define DCT_STATUS_ERROR     (1<<1)        // DCT Error
32
33 // Interrupt enable register
34 #define DCT_ITEN_END_OK      (1<<0)        // IT Done enable
35 #define DCT_ITEN_ERROR       (1<<1)        // IT Error enable
36
37 // Interrupt Acknowledge register
38 #define DCT_ITACK_END_OK     (1<<0)        // IT Done acknowledge
39 #define DCT_ITACK_ERROR      (1<<1)        // IT Error acknowledge
40
41 // DCT control mode (forward or inverse dct)
42 #define DCT_CTRLMODE_FDCT     0
43 #define DCT_CTRLMODE_IDCT     1
44
45
46 //! write to a DCT register
47 #define dct_write_reg( _reg_, _value_ ) \
48  (*((volatile CYG_WORD32 *)(PARROT5_DCT +(_reg_))) = (CYG_WORD32)(_value_))
49
50 //! read a DCT register
51 #define dct_read_reg(_reg_ ) \
52  (*((volatile CYG_WORD32 *)(PARROT5_DCT+(_reg_))))
53
54 typedef enum {
55   DCT_DMA_INCR    = 0,                    //!<  4 bytes DMA burst
56   DCT_DMA_INCR4   = 1,                    //!< 16 bytes DMA burst
57   DCT_DMA_INCR8   = 2,                    //!< 32 bytes DMA burst
58   DCT_DMA_INCR16  = 3,                    //!< 64 bytes DMA burst
59 } DCT_DMA_BURST_MODE;
60
61 C_RESULT video_dct_p5p_init(void);
62
63 int16_t* video_fdct_compute(int16_t* in, int16_t* out, int32_t num_macro_blocks);
64 int16_t* video_idct_compute(int16_t* in, int16_t* out, int32_t num_macro_blocks);
65
66 #endif // ! _VIDEO_DCT_P5P_H_