vcs.maemo.org Git - kernel-bfs/blob - kernel-bfs-2.6.28/debian/patches/nokia-20101501+0m5.diff

   1 --- kernel-power-2.6.28.orig/arch/arm/mach-omap2/board-rx51-camera.c
   2 +++ kernel-power-2.6.28/arch/arm/mach-omap2/board-rx51-camera.c
   3 @@ -561,7 +561,7 @@
   4         gpio_set_value(ADP1653_GPIO_ENABLE, 1);
   5
   6         /* Some delay is apparently required. */
   7 -       udelay(20);
   8 +       udelay(400);
   9
  10         return 0;
  11  }
  12 --- kernel-power-2.6.28.orig/arch/arm/mach-omap2/pm34xx.c
  13 +++ kernel-power-2.6.28/arch/arm/mach-omap2/pm34xx.c
  14 @@ -45,6 +45,7 @@
  15  #include <mach/dma.h>
  16  #include <mach/vrfb.h>
  17  #include <mach/ssi.h>
  18 +#include <mach/omap-pm.h>
  19
  20  #include <asm/tlbflush.h>
  21
  22 @@ -102,6 +103,8 @@
  23  #define CONTROL_PADCONF_MCBSP4_DX      0x158
  24  #define CONTROL_PADCONF_UART1_TX       0x14c
  25
  26 +#define VSEL_1200      0x30
  27 +
  28  static u16 ssi_rx_rdy;
  29  static u16 ssi_tx_dat;
  30  static u16 ssi_tx_flag;
  31 @@ -520,6 +523,7 @@
  32         u32 sdrc_pwr = 0;
  33         int per_state_modified = 0;
  34         int core_saved_state = PWRDM_POWER_ON;
  35 +       static int prev_dpll3_div = 0;
  36
  37         if (!_omap_sram_idle)
  38                 return;
  39 @@ -551,7 +555,7 @@
  40         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) {
  41                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
  42                 neon_next_state = mpu_next_state;
  43 -               if (neon_next_state == PWRDM_POWER_OFF)
  44 +               if (neon_next_state == PWRDM_POWER_OFF)
  45                         omap3_save_neon_context();
  46         }
  47
  48 @@ -562,6 +566,12 @@
  49         usb_state = pwrdm_read_pwrst(usb_pwrdm);
  50         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
  51
  52 +       if (dss_state == PWRDM_POWER_ON &&
  53 +               core_next_state < PWRDM_POWER_INACTIVE) {
  54 +               core_next_state = PWRDM_POWER_INACTIVE;
  55 +               pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
  56 +       }
  57 +
  58         /* Check if PER domain can enter OFF or not */
  59         if (per_next_state == PWRDM_POWER_OFF) {
  60                 if ((cm_read_mod_reg(OMAP3430_PER_MOD, CM_IDLEST) &
  61 @@ -679,6 +689,33 @@
  62                                   OMAP3_PRM_CLKSETUP_OFFSET);
  63         }
  64
  65 +       if (core_next_state < PWRDM_POWER_INACTIVE) {
  66 +               u32 clksel1_pll, v;
  67 +
  68 +               clksel1_pll = cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
  69 +               prev_dpll3_div = clksel1_pll >> 28;
  70 +               if (prev_dpll3_div == 1) {
  71 +                       /* L3 @ 166Mhz */
  72 +                       struct omap_sdrc_params *sdrc_cs0;
  73 +                       struct omap_sdrc_params *sdrc_cs1;
  74 +
  75 +                       omap2_sdrc_get_params(83*1000*1000, &sdrc_cs0, &sdrc_cs1);
  76 +                       /* scale down to 83Mhz, use worst case delay for clock stabilization */
  77 +                       omap3_configure_core_dpll(4, 0, 28, 0, sdrc_cs0->rfr_ctrl, sdrc_cs0->mr, 0, 0);
  78 +
  79 +                       /* increase voltage to 1.2V */
  80 +                       sr_voltagescale_vcbypass(PRCM_VDD2_OPP3, PRCM_VDD2_OPP2, VSEL_1200, l3_opps[3].vsel);
  81 +               } else {
  82 +                       /* L3 @ 83Mhz, increase voltage to 1.2V  */
  83 +                       sr_voltagescale_vcbypass(PRCM_VDD2_OPP3, PRCM_VDD2_OPP2, VSEL_1200, l3_opps[2].vsel);
  84 +               }
  85 +
  86 +               /* enable DPLL3 autoidle */
  87 +               v = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
  88 +               v |= 1;
  89 +               cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
  90 +       }
  91 +
  92         memcpy(save_sdrc_counters, _sdrc_counters, sizeof(save_sdrc_counters));
  93
  94         /*
  95 @@ -701,6 +738,51 @@
  96         if (neon_next_state == PWRDM_POWER_OFF)
  97                 omap3_restore_neon_context();
  98
  99 +       if (core_next_state < PWRDM_POWER_INACTIVE) {
 100 +               if (pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
 101 +                       u32 clksel1_pll;
 102 +
 103 +                       /* ROM code restored the scratchpad settings. So DPLL3 autoidle is
 104 +                        * disabled and L3 clock is back to the value before entering this function.
 105 +                        * This means we only have to lower the voltage if L3 runs at 83Mhz
 106 +                        */
 107 +                       clksel1_pll = cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
 108 +                       if ((clksel1_pll >> 28) == 2) {
 109 +                               /* restore VDD2 OPP2 voltage */
 110 +                               sr_voltagescale_vcbypass(PRCM_VDD2_OPP2, PRCM_VDD2_OPP3, l3_opps[2].vsel, VSEL_1200);
 111 +                       }
 112 +                       else {
 113 +                               /* restore VDD2 OPP3 voltage */
 114 +                               sr_voltagescale_vcbypass(PRCM_VDD2_OPP2, PRCM_VDD2_OPP3, l3_opps[3].vsel, VSEL_1200);
 115 +                       }
 116 +               }
 117 +               else {
 118 +                       u32 v;
 119 +
 120 +                       /* disable DPLL3 autoidle */
 121 +                       v = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
 122 +                       v &= ~0x7;
 123 +                       cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
 124 +
 125 +                       if (prev_dpll3_div == 1) {
 126 +                               /* restore L3 to 166Mhz */
 127 +                               struct omap_sdrc_params *sdrc_cs0;
 128 +                               struct omap_sdrc_params *sdrc_cs1;
 129 +
 130 +                               omap2_sdrc_get_params(166*1000*1000, &sdrc_cs0, &sdrc_cs1);
 131 +                               /* scale up to 166Mhz, use worst case delay for clock stabilization */
 132 +                               omap3_configure_core_dpll(2, 0, 28, 1, sdrc_cs0->rfr_ctrl, sdrc_cs0->mr, 0, 0);
 133 +
 134 +                               /* restore VDD2 OPP3 voltage */
 135 +                               sr_voltagescale_vcbypass(PRCM_VDD2_OPP2, PRCM_VDD2_OPP3, l3_opps[3].vsel, VSEL_1200);
 136 +                       }
 137 +                       else {
 138 +                               /* restore VDD2 OPP2 voltage */
 139 +                               sr_voltagescale_vcbypass(PRCM_VDD2_OPP2, PRCM_VDD2_OPP3, l3_opps[2].vsel, VSEL_1200);
 140 +                       }
 141 +               }
 142 +       }
 143 +
 144         /* CORE */
 145         if (core_next_state < PWRDM_POWER_ON) {
 146                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 147 @@ -1136,7 +1218,7 @@
 148                          MPU_MOD,
 149                          CM_AUTOIDLE2);
 150         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 151 -                        (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 152 +                        (0 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 153                          PLL_MOD,
 154                          CM_AUTOIDLE);
 155         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 156 --- kernel-power-2.6.28.orig/arch/arm/mach-omap2/ssi.c
 157 +++ kernel-power-2.6.28/arch/arm/mach-omap2/ssi.c
 158 @@ -378,7 +378,7 @@
 159         u32 v;
 160
 161         v = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
 162 -       v |= 1;
 163 +       v |= 0;
 164         cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
 165  }
 166
 167 --- kernel-power-2.6.28.orig/drivers/mmc/host/omap_hsmmc.c
 168 +++ kernel-power-2.6.28/drivers/mmc/host/omap_hsmmc.c
 169 @@ -28,6 +28,7 @@
 170  #include <linux/clk.h>
 171  #include <linux/mmc/host.h>
 172  #include <linux/mmc/core.h>
 173 +#include <linux/mmc/card.h>
 174  #include <linux/io.h>
 175  #include <linux/semaphore.h>
 176  #include <asm/dma.h>
 177 @@ -97,6 +98,8 @@
 178  #define SOFTRESET              (1 << 1)
 179  #define RESETDONE              (1 << 0)
 180
 181 +#define SAMSUNG_MANUF_ID       0x15
 182 +
 183  /*
 184   * FIXME: Most likely all the data using these _DEVID defines should come
 185   * from the platform_data, or implemented in controller and slot specific
 186 @@ -1283,10 +1286,24 @@
 187         return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
 188  }
 189
 190 +/* JEDEC specification says the nand core voltage can be shut off while the
 191 +   card is sleeping. Some cards are known not to be JEDEC compatible with
 192 +   this respect */
 193 +static int omap_hsmmc_full_sleep(struct mmc_card *card)
 194 +{
 195 +       if (card->cid.manfid == SAMSUNG_MANUF_ID) {
 196 +               unsigned int gbytes = card->ext_csd.sectors >> (30 - 9);
 197 +               if (gbytes > 24 && gbytes < 48)
 198 +                       return 0;
 199 +       }
 200 +
 201 +       return 1;
 202 +}
 203 +
 204  /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
 205  static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
 206  {
 207 -       int err, new_state;
 208 +       int err, new_state, sleep;
 209
 210         if (!mmc_try_claim_host(host->mmc))
 211                 return 0;
 212 @@ -1304,9 +1321,12 @@
 213         } else {
 214                 new_state = REGSLEEP;
 215         }
 216 +
 217 +       sleep = omap_hsmmc_full_sleep(host->mmc->card) &&
 218 +               (new_state == CARDSLEEP);
 219         if (mmc_slot(host).set_sleep)
 220                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
 221 -                                        new_state == CARDSLEEP);
 222 +                                       sleep);
 223         /* FIXME: turn off bus power and perhaps interrupts too */
 224         clk_disable(host->fclk);
 225         host->dpm_state = new_state;
 226 @@ -1376,14 +1396,18 @@
 227
 228  static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
 229  {
 230 +       int asleep;
 231 +
 232         if (!mmc_try_claim_host(host->mmc))
 233                 return 0;
 234
 235         clk_enable(host->fclk);
 236         omap_hsmmc_context_restore(host);
 237 +       asleep = omap_hsmmc_full_sleep(host->mmc->card) &&
 238 +               (host->dpm_state == CARDSLEEP);
 239         if (mmc_slot(host).set_sleep)
 240                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
 241 -                        host->vdd, host->dpm_state == CARDSLEEP);
 242 +                                       host->vdd, asleep);
 243         if (mmc_card_can_sleep(host->mmc))
 244                 mmc_card_awake(host->mmc);
 245
 246 --- kernel-power-2.6.28.orig/drivers/net/wireless/wl12xx/wl1251_main.c
 247 +++ kernel-power-2.6.28/drivers/net/wireless/wl12xx/wl1251_main.c
 248 @@ -1611,6 +1611,7 @@
 249         }
 250
 251  out:
 252 +       kfree(trigger);
 253         kfree(params);
 254         return ret;
 255
 256 --- kernel-power-2.6.28.orig/drivers/net/wireless/wl12xx/wl1251_spi.c
 257 +++ kernel-power-2.6.28/drivers/net/wireless/wl12xx/wl1251_spi.c
 258 @@ -92,6 +92,8 @@
 259         spi_sync(wl->spi, &m);
 260
 261         wl1251_dump(DEBUG_SPI, "spi reset -> ", cmd, WSPI_INIT_CMD_LEN);
 262 +
 263 +       kfree(cmd);
 264  }
 265
 266  void wl1251_spi_init(struct wl1251 *wl)
 267 @@ -146,6 +148,8 @@
 268         spi_sync(wl->spi, &m);
 269
 270         wl1251_dump(DEBUG_SPI, "spi init -> ", cmd, WSPI_INIT_CMD_LEN);
 271 +
 272 +       kfree(cmd);
 273  }
 274
 275  /* Set the SPI partitions to access the chip addresses
 276 --- kernel-power-2.6.28.orig/net/mac80211/mlme.c
 277 +++ kernel-power-2.6.28/net/mac80211/mlme.c
 278 @@ -1624,6 +1624,7 @@
 279                         memcpy(pos, &bss->supp_rates[8], rates);
 280                 }
 281
 282 +               kfree_skb(ifsta->probe_resp);
 283                 ifsta->probe_resp = skb;
 284
 285                 ieee80211_if_config(sdata, IEEE80211_IFCC_BEACON);