2 /****************************************************************
3 ****************************************************************/
5 .equiv ASM_SPC700, 1 ;@ 1 = use notaz's ASM_SPC700 core
7 /****************************************************************
9 ****************************************************************/
13 rstatus .req R4 @ format : 0xff800000
14 reg_d_bank .req R4 @ format : 0x000000ll
15 reg_a .req R5 @ format : 0xhhll0000 or 0xll000000
16 reg_d .req R6 @ format : 0xhhll0000
17 reg_p_bank .req R6 @ format : 0x000000ll
18 reg_x .req R7 @ format : 0xhhll0000 or 0xll000000
19 reg_s .req R8 @ format : 0x0000hhll
20 reg_y .req R9 @ format : 0xhhll0000 or 0xll000000
22 rpc .req R10 @ 32bits address
23 reg_cycles .req R11 @ 32bits counter
24 regpcbase .req R12 @ 32bits address
26 rscratch .req R0 @ format : 0xhhll0000 if data and calculation or return of S9XREADBYTE or WORD
27 regopcode .req R0 @ format : 0x000000ll
28 rscratch2 .req R1 @ format : 0xhhll for calculation and value
30 rscratch4 .req R3 @ ??????
33 rscratch9 .req R10 @ ??????
39 @ R13 @ Pointer 32 bit on a struct.
43 .equ STATUS_SHIFTER, 24
44 .equ MASK_EMUL, (1<<(STATUS_SHIFTER-1))
45 .equ MASK_SHIFTER_CARRY, (STATUS_SHIFTER+1)
46 .equ MASK_CARRY, (1<<(STATUS_SHIFTER)) @ 0
47 .equ MASK_ZERO, (2<<(STATUS_SHIFTER)) @ 1
48 .equ MASK_IRQ, (4<<(STATUS_SHIFTER)) @ 2
49 .equ MASK_DECIMAL, (8<<(STATUS_SHIFTER)) @ 3
50 .equ MASK_INDEX, (16<<(STATUS_SHIFTER)) @ 4 @ 1
51 .equ MASK_MEM, (32<<(STATUS_SHIFTER)) @ 5 @ 2
52 .equ MASK_OVERFLOW, (64<<(STATUS_SHIFTER)) @ 6 @ 4
53 .equ MASK_NEG, (128<<(STATUS_SHIFTER))@ 7 @ 8
56 .equ SLOW_ONE_CYCLE, 8
58 .equ NMI_FLAG, (1 << 7)
59 .equ IRQ_PENDING_FLAG, (1 << 11)
60 .equ SCAN_KEYS_FLAG, (1 << 4)
63 .equ MEMMAP_BLOCK_SIZE, (0x1000)
65 .equ MEMMAP_MASK, (0xFFF)
67 /****************************************************************
69 ****************************************************************/
71 @ #include "os9x_65c816_mac_gen.h"
72 /*****************************************************************/
73 /* Offset in SCPUState structure */
74 /*****************************************************************/
76 .equ BranchSkip_ofs, 4
79 .equ WaitingForInterrupt_ofs, 7
96 .equ PCAtOpcodeStart_ofs, 36
97 .equ WaitAddress_ofs, 40
98 .equ WaitCounter_ofs, 44
99 .equ NextEvent_ofs, 48
100 .equ V_Counter_ofs, 52
101 .equ MemSpeed_ofs, 56
102 .equ MemSpeedx2_ofs, 60
103 .equ FastROMSpeed_ofs, 64
104 .equ AutoSaveTimer_ofs, 68
105 .equ NMITriggerPoint_ofs, 72
106 .equ NMICycleCount_ofs, 76
107 .equ IRQCycleCount_ofs, 80
111 .equ SRAMModified_ofs, 86
112 .equ BRKTriggered_ofs, 87
113 .equ asm_OPTABLE_ofs, 88
114 .equ TriedInterleavedMode2_ofs, 92
117 .equ WriteMap_ofs, 100
118 .equ MemorySpeed_ofs, 104
119 .equ BlockIsRAM_ofs, 108
124 .equ APUExecuting_ofs, 122
128 /*****************************************************************/
131 .macro PREPARE_C_CALL
134 .macro PREPARE_C_CALL_R0
135 STMFD R13!,{R0,R12,R14}
137 .macro PREPARE_C_CALL_R0R1
138 STMFD R13!,{R0,R1,R12,R14}
140 .macro PREPARE_C_CALL_LIGHT
143 .macro PREPARE_C_CALL_LIGHTR12
147 .macro RESTORE_C_CALL
150 .macro RESTORE_C_CALL_R0
151 LDMFD R13!,{R0,R12,R14}
153 .macro RESTORE_C_CALL_R1
154 LDMFD R13!,{R1,R12,R14}
156 .macro RESTORE_C_CALL_LIGHT
159 .macro RESTORE_C_CALL_LIGHTR12
167 add r0,reg_cpu_var,#8
168 ldmia r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
169 @ rstatus (P) & reg_d_bank
170 mov reg_d_bank,r1,lsl #16
171 mov reg_d_bank,reg_d_bank,lsr #24
173 orrs rstatus, rstatus, r0,lsl #STATUS_SHIFTER @ 24
174 @ if Carry set, then EMULATION bit was set
175 orrcs rstatus,rstatus,#MASK_EMUL
177 mov reg_d,reg_a,lsr #16
178 mov reg_d,reg_d,lsl #8
179 orr reg_d,reg_d,r1,lsl #24
180 mov reg_d,reg_d,ror #24 @ 0xdddd00pb
182 mov reg_s,reg_x,lsr #16
183 @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
184 tst rstatus,#MASK_INDEX
185 movne reg_x,reg_x,lsl #24
186 movne reg_y,reg_y,lsl #24
187 moveq reg_x,reg_x,lsl #16
188 moveq reg_y,reg_y,lsl #16
189 tst rstatus,#MASK_MEM
190 movne reg_a,reg_a,lsl #24
191 moveq reg_a,reg_a,lsl #16
194 @ reg_d & reg_p_bank share the same register
195 LDRB reg_p_bank,[reg_cpu_var,#RPB_ofs]
196 LDRH rscratch,[reg_cpu_var,#RD_ofs]
197 ORR reg_d,reg_d,rscratch, LSL #16
198 @ rstatus & reg_d_bank share the same register
199 LDRB reg_d_bank,[reg_cpu_var,#RDB_ofs]
200 LDRH rscratch,[reg_cpu_var,#RP_ofs]
201 ORRS rstatus, rstatus, rscratch,LSL #STATUS_SHIFTER @ 24
202 @ if Carry set, then EMULATION bit was set
203 ORRCS rstatus,rstatus,#MASK_EMUL
205 LDRH reg_a,[reg_cpu_var,#RA_ofs]
206 LDRH reg_x,[reg_cpu_var,#RX_ofs]
207 LDRH reg_y,[reg_cpu_var,#RY_ofs]
208 LDRH reg_s,[reg_cpu_var,#RS_ofs]
209 @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
210 TST rstatus,#MASK_INDEX
211 MOVNE reg_x,reg_x,LSL #24
212 MOVNE reg_y,reg_y,LSL #24
213 MOVEQ reg_x,reg_x,LSL #16
214 MOVEQ reg_y,reg_y,LSL #16
215 TST rstatus,#MASK_MEM
216 MOVNE reg_a,reg_a,LSL #24
217 MOVEQ reg_a,reg_a,LSL #16
219 LDR regpcbase,[reg_cpu_var,#PCBase_ofs]
220 LDR rpc,[reg_cpu_var,#PC_ofs]
221 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs]
228 @ reg_p_bank, reg_d_bank and rstatus
229 mov r1, rstatus, lsr #16
230 orr r1, r1, reg_p_bank, lsl #24
232 orrcs r1, r1, #0x100 @ EMULATION bit
233 orr r1, r1, reg_d_bank, lsl #24
236 tst rstatus,#MASK_MEM
237 ldrneh r0, [reg_cpu_var,#RA_ofs]
239 orrne reg_a, r0, reg_a,lsr #24
240 moveq reg_a, reg_a, lsr #16
241 mov reg_d, reg_d, lsr #16
242 orr reg_a, reg_a, reg_d, lsl #16
243 @ Shift X&Y according to the current mode (INDEX, MEMORY bits)
244 tst rstatus,#MASK_INDEX
245 movne reg_x,reg_x,LSR #24
246 movne reg_y,reg_y,LSR #24
247 moveq reg_x,reg_x,LSR #16
248 moveq reg_y,reg_y,LSR #16
250 orr reg_x, reg_x, reg_s, lsl #16
252 add r0,reg_cpu_var,#8
253 stmia r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
256 @ reg_d & reg_p_bank is same register
257 STRB reg_p_bank,[reg_cpu_var,#RPB_ofs]
258 MOV rscratch,reg_d, LSR #16
259 STRH rscratch,[reg_cpu_var,#RD_ofs]
260 @ rstatus & reg_d_bank is same register
261 STRB reg_d_bank,[reg_cpu_var,#RDB_ofs]
262 MOVS rscratch, rstatus, LSR #STATUS_SHIFTER
263 ORRCS rscratch,rscratch,#0x100 @ EMULATION bit
264 STRH rscratch,[reg_cpu_var,#RP_ofs]
266 @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
267 TST rstatus,#MASK_INDEX
268 MOVNE rscratch,reg_x,LSR #24
269 MOVNE rscratch2,reg_y,LSR #24
270 MOVEQ rscratch,reg_x,LSR #16
271 MOVEQ rscratch2,reg_y,LSR #16
272 STRH rscratch,[reg_cpu_var,#RX_ofs]
273 STRH rscratch2,[reg_cpu_var,#RY_ofs]
274 TST rstatus,#MASK_MEM
275 LDRNEH rscratch,[reg_cpu_var,#RA_ofs]
276 BICNE rscratch,rscratch,#0xFF
277 ORRNE rscratch,rscratch,reg_a,LSR #24
278 MOVEQ rscratch,reg_a,LSR #16
279 STRH rscratch,[reg_cpu_var,#RA_ofs]
281 STRH reg_s,[reg_cpu_var,#RS_ofs]
282 STR regpcbase,[reg_cpu_var,#PCBase_ofs]
283 STR rpc,[reg_cpu_var,#PC_ofs]
285 STR reg_cycles,[reg_cpu_var,#Cycles_ofs]
289 /*****************************************************************/
291 add reg_cycles,reg_cycles, #ONE_CYCLE
294 addne reg_cycles,reg_cycles, #ONE_CYCLE
297 addeq reg_cycles,reg_cycles, #ONE_CYCLE
301 add reg_cycles,reg_cycles, #(ONE_CYCLE*2)
304 addne reg_cycles,reg_cycles, #(ONE_CYCLE*2)
307 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
308 add reg_cycles,reg_cycles, #(ONE_CYCLE*2)
309 add reg_cycles, reg_cycles, rscratch, LSL #1
312 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
313 add reg_cycles,reg_cycles, #(ONE_CYCLE*2)
314 add reg_cycles, reg_cycles, rscratch
318 add reg_cycles,reg_cycles, #(ONE_CYCLE*3)
322 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
323 add reg_cycles,reg_cycles, #ONE_CYCLE
324 add reg_cycles, reg_cycles, rscratch
328 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
329 add reg_cycles,reg_cycles, #ONE_CYCLE
330 add reg_cycles, reg_cycles, rscratch, lsl #1
334 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
335 add reg_cycles, reg_cycles, rscratch
339 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
340 add reg_cycles, reg_cycles, rscratch, lsl #1
344 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
345 add reg_cycles, rscratch, reg_cycles
346 add reg_cycles, reg_cycles, rscratch, lsl #1
351 BIC rstatus,rstatus,#MASK_DECIMAL
354 ORR rstatus,rstatus,#MASK_DECIMAL
357 ORR rstatus,rstatus,#MASK_IRQ
360 BIC rstatus,rstatus,#MASK_IRQ
364 @ if (Settings.Shutdown && CPU.PC == CPU.WaitAddress)
365 LDR rscratch,[reg_cpu_var,#WaitAddress_ofs]
368 @ if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG)))
369 LDR rscratch,[reg_cpu_var,#Flags_ofs]
370 LDR rscratch2,[reg_cpu_var,#WaitCounter_ofs]
371 TST rscratch,#(IRQ_PENDING_FLAG|NMI_FLAG)
373 MOVS rscratch2,rscratch2
375 @ CPU.WaitAddress = NULL;
377 STR rscratch,[reg_cpu_var,#WaitAddress_ofs]
379 @ S9xSA1ExecuteDuringSleep (); : TODO
381 @ CPU.Cycles = CPU.NextEvent;
382 LDR reg_cycles,[reg_cpu_var,#NextEvent_ofs]
383 LDRB r0,[reg_cpu_var,#APUExecuting_ofs]
386 @ if (IAPU.APUExecuting)
388 ICPU.CPUExecuting = FALSE;
392 } while (APU.Cycles < CPU.NextEvent);
393 ICPU.CPUExecuting = TRUE;
401 if (CPU.WaitCounter >= 2)
408 @ SUBLS rscratch2,rscratch2,#1
410 STR rscratch2,[reg_cpu_var,#WaitCounter_ofs]
415 /*in rsctach : OpAddress
416 /*destroy rscratch2*/
417 LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
418 MOVS rscratch2,rscratch2
421 STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
422 SUB rscratch2,rpc,regpcbase
423 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
424 CMP rscratch2,rscratch
429 /*in rsctach : OpAddress
430 /*destroy rscratch2*/
431 LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
432 MOVS rscratch2,rscratch2
435 STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
436 SUB rscratch2,rpc,regpcbase
437 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
438 CMP rscratch2,rscratch
443 /*in rsctach : OpAddress
444 /*destroy rscratch2*/
445 LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
446 MOVS rscratch2,rscratch2
449 STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
450 SUB rscratch2,rpc,regpcbase
451 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
452 CMP rscratch2,rscratch
458 @ in : rscratch (0x00hhmmll)
462 LDR rpc,[reg_cpu_var,#PC_ofs]
463 LDR regpcbase,[reg_cpu_var,#PCBase_ofs]
467 TST rstatus,#MASK_EMUL
468 LDRNE rscratch, = jumptable1 @ Mode 0 : M=1,X=1
471 TST rstatus,#MASK_MEM
474 TST rstatus,#MASK_INDEX
475 @ INDEX=1 @ Mode 0 : M=1,X=1
476 LDRNE rscratch, = jumptable1
477 @ INDEX=0 @ Mode 1 : M=1,X=0
478 LDREQ rscratch, = jumptable2
481 TST rstatus,#MASK_INDEX
482 @ INDEX=1 @ Mode 3 : M=0,X=1
483 LDRNE rscratch, = jumptable4
484 @ INDEX=0 @ Mode 2 : M=0,X=0
485 LDREQ rscratch, = jumptable3
487 STR rscratch,[reg_cpu_var,#asm_OPTABLE_ofs]
505 .macro S9xDoHBlankProcessing
508 @ BL asm_S9xDoHBlankProcessing
509 BL S9xDoHBlankProcessing
514 /********************************/
516 LDR R1,[reg_cpu_var,#asm_OPTABLE_ofs]
517 STR rpc,[reg_cpu_var,#PCAtOpcodeStart_ofs]
521 LDR PC, [R1,R0, LSL #2]
524 LDR rscratch,[reg_cpu_var,#NextEvent_ofs]
525 CMP reg_cycles,rscratch
527 S9xDoHBlankProcessing
531 .macro asmAPU_EXECUTE
532 LDRB R0,[reg_cpu_var,#APUExecuting_ofs]
533 CMP R0,#1 @ spc700 enabled, hack mode off
535 LDR R0,[reg_cpu_var,#APU_Cycles]
536 SUBS R0,reg_cycles,R0
539 PREPARE_C_CALL_LIGHTR12
541 RESTORE_C_CALL_LIGHTR12
542 SUB R0,reg_cycles,R0 @ sub cycles left
543 STR R0,[reg_cpu_var,#APU_Cycles]
546 STR reg_cycles,[reg_cpu_var,#Cycles_ofs]
547 PREPARE_C_CALL_LIGHTR12
549 RESTORE_C_CALL_LIGHTR12
550 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs]
557 .macro asmAPU_EXECUTE2
559 LDRB R0,[reg_cpu_var,#APUExecuting_ofs]
560 CMP R0,#1 @ spc700 enabled, hack mode off
562 LDR R0,[reg_cpu_var,#APU_Cycles]
563 SUBS R0,reg_cycles,R0 @ reg_cycles == NextEvent
565 PREPARE_C_CALL_LIGHTR12
567 RESTORE_C_CALL_LIGHTR12
568 SUB R0,reg_cycles,R0 @ sub cycles left
569 STR R0,[reg_cpu_var,#APU_Cycles]
573 STR reg_cycles,[reg_cpu_var,#Cycles_ofs]
574 PREPARE_C_CALL_LIGHTR12
576 RESTORE_C_CALL_LIGHTR12
577 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs]
583 @ in : rscratch (0x00hhmmll)
584 @ out : rscratch (0xhhll0000)
585 STMFD R13!,{PC} @ Push return address
591 @ in : rscratch (0x00hhmmll)
592 @ out : rscratch (0x0000hhll)
593 STMFD R13!,{PC} @ Push return address
597 .macro S9xGetWordRegStatus reg
598 @ in : rscratch (0x00hhmmll)
599 @ out : reg (0xhhll0000)
600 @ flags have to be updated with read value
601 STMFD R13!,{PC} @ Push return address
604 MOVS \reg, R0, LSL #16
606 .macro S9xGetWordRegNS reg
607 @ in : rscratch (0x00hhmmll)
608 @ out : reg (0xhhll0000)
609 @ DOES NOT DESTROY rscratch (R0)
611 STMFD R13!,{PC} @ Push return address
614 MOV \reg, R0, LSL #16
617 .macro S9xGetWordLowRegNS reg
618 @ in : rscratch (0x00hhmmll)
619 @ out : reg (0xhhll0000)
620 @ DOES NOT DESTROY rscratch (R0)
622 STMFD R13!,{PC} @ Push return address
630 @ in : rscratch (0x00hhmmll)
631 @ out : rscratch (0xll000000)
632 STMFD R13!,{PC} @ Push return address
638 @ in : rscratch (0x00hhmmll)
639 @ out : rscratch (0x000000ll)
644 .macro S9xGetByteRegStatus reg
645 @ in : rscratch (0x00hhmmll)
646 @ out : reg (0xll000000)
647 @ flags have to be updated with read value
648 STMFD R13!,{PC} @ Push return address
651 MOVS \reg, R0, LSL #24
653 .macro S9xGetByteRegNS reg
654 @ in : rscratch (0x00hhmmll)
655 @ out : reg (0xll000000)
656 @ DOES NOT DESTROY rscratch (R0)
658 STMFD R13!,{PC} @ Push return address
661 MOVS \reg, R0, LSL #24
664 .macro S9xGetByteLowRegNS reg
665 @ in : rscratch (0x00hhmmll)
666 @ out : reg (0x000000ll)
667 @ DOES NOT DESTROY rscratch (R0)
669 STMFD R13!,{PC} @ Push return address
676 .macro S9xSetWord regValue
677 @ in : regValue (0xhhll0000)
678 @ in : rscratch=address (0x00hhmmll)
679 MOV R1,\regValue, LSR #16
680 STMFD R13!,{PC} @ Push return address
684 .macro S9xSetWordZero
685 @ in : rscratch=address (0x00hhmmll)
687 STMFD R13!,{PC} @ Push return address
691 .macro S9xSetWordLow regValue
692 @ in : regValue (0x0000hhll)
693 @ in : rscratch=address (0x00hhmmll)
695 STMFD R13!,{PC} @ Push return address
699 .macro S9xSetByte regValue
700 @ in : regValue (0xll000000)
701 @ in : rscratch=address (0x00hhmmll)
702 MOV R1,\regValue, LSR #24
703 STMFD R13!,{PC} @ Push return address
707 .macro S9xSetByteZero
708 @ in : rscratch=address (0x00hhmmll)
710 STMFD R13!,{PC} @ Push return address
714 .macro S9xSetByteLow regValue
715 @ in : regValue (0x000000ll)
716 @ in : rscratch=address (0x00hhmmll)
718 STMFD R13!,{PC} @ Push return address
724 @ ===========================================
725 @ ===========================================
727 @ ===========================================
728 @ ===========================================
733 LDRB rscratch2 , [rpc, #1]
734 LDRB rscratch , [rpc],#2
735 ORR rscratch , rscratch, rscratch2, LSL #8
736 ORR rscratch , rscratch, reg_d_bank, LSL #16
738 .macro AbsoluteIndexedIndirectX0
740 LDRB rscratch2 , [rpc, #1]
741 LDRB rscratch , [rpc], #2
742 ORR rscratch , rscratch, rscratch2, LSL #8
743 ADD rscratch , reg_x, rscratch, LSL #16
744 MOV rscratch , rscratch, LSR #16
745 ORR rscratch , rscratch, reg_p_bank, LSL #16
749 .macro AbsoluteIndexedIndirectX1
751 LDRB rscratch2 , [rpc, #1]
752 LDRB rscratch , [rpc], #2
753 ORR rscratch , rscratch, rscratch2, LSL #8
754 ADD rscratch , rscratch, reg_x, LSR #24
755 BIC rscratch , rscratch, #0x00FF0000
756 ORR rscratch , rscratch, reg_p_bank, LSL #16
760 .macro AbsoluteIndirectLong
762 LDRB rscratch2 , [rpc, #1]
763 LDRB rscratch , [rpc], #2
764 ORR rscratch , rscratch, rscratch2, LSL #8
765 S9xGetWordLowRegNS rscratch2
766 ADD rscratch , rscratch, #2
767 STMFD r13!,{rscratch2}
769 LDMFD r13!,{rscratch2}
770 ORR rscratch , rscratch2, rscratch, LSL #16
772 .macro AbsoluteIndirect
774 LDRB rscratch2 , [rpc,#1]
775 LDRB rscratch , [rpc], #2
776 ORR rscratch , rscratch, rscratch2, LSL #8
778 ORR rscratch , rscratch, reg_p_bank, LSL #16
780 .macro AbsoluteIndexedX0
782 LDRB rscratch2 , [rpc, #1]
783 LDRB rscratch , [rpc], #2
784 ORR rscratch , rscratch, rscratch2, LSL #8
785 ORR rscratch , rscratch, reg_d_bank, LSL #16
786 ADD rscratch , rscratch, reg_x, LSR #16
788 .macro AbsoluteIndexedX1
790 LDRB rscratch2 , [rpc, #1]
791 LDRB rscratch , [rpc], #2
792 ORR rscratch , rscratch, rscratch2, LSL #8
793 ORR rscratch , rscratch, reg_d_bank, LSL #16
794 ADD rscratch , rscratch, reg_x, LSR #24
798 .macro AbsoluteIndexedY0
800 LDRB rscratch2 , [rpc, #1]
801 LDRB rscratch , [rpc], #2
802 ORR rscratch , rscratch, rscratch2, LSL #8
803 ORR rscratch , rscratch, reg_d_bank, LSL #16
804 ADD rscratch , rscratch, reg_y, LSR #16
806 .macro AbsoluteIndexedY1
808 LDRB rscratch2 , [rpc, #1]
809 LDRB rscratch , [rpc], #2
810 ORR rscratch , rscratch, rscratch2, LSL #8
811 ORR rscratch , rscratch, reg_d_bank, LSL #16
812 ADD rscratch , rscratch, reg_y, LSR #24
816 LDRB rscratch2 , [rpc, #1]
817 LDRB rscratch , [rpc], #2
818 ORR rscratch , rscratch, rscratch2, LSL #8
819 LDRB rscratch2 , [rpc], #1
820 ORR rscratch , rscratch, rscratch2, LSL #16
824 .macro AbsoluteLongIndexedX0
826 LDRB rscratch2 , [rpc, #1]
827 LDRB rscratch , [rpc], #2
828 ORR rscratch , rscratch, rscratch2, LSL #8
829 LDRB rscratch2 , [rpc], #1
830 ORR rscratch , rscratch, rscratch2, LSL #16
831 ADD rscratch , rscratch, reg_x, LSR #16
832 BIC rscratch, rscratch, #0xFF000000
834 .macro AbsoluteLongIndexedX1
836 LDRB rscratch2 , [rpc, #1]
837 LDRB rscratch , [rpc], #2
838 ORR rscratch , rscratch, rscratch2, LSL #8
839 LDRB rscratch2 , [rpc], #1
840 ORR rscratch , rscratch, rscratch2, LSL #16
841 ADD rscratch , rscratch, reg_x, LSR #24
842 BIC rscratch, rscratch, #0xFF000000
846 LDRB rscratch , [rpc], #1
847 ADD rscratch , reg_d, rscratch, LSL #16
848 MOV rscratch, rscratch, LSR #16
850 .macro DirectIndirect
852 LDRB rscratch , [rpc], #1
853 ADD rscratch , reg_d, rscratch, LSL #16
854 MOV rscratch, rscratch, LSR #16
856 ORR rscratch , rscratch, reg_d_bank, LSL #16
858 .macro DirectIndirectLong
860 LDRB rscratch , [rpc], #1
861 ADD rscratch , reg_d, rscratch, LSL #16
862 MOV rscratch, rscratch, LSR #16
863 S9xGetWordLowRegNS rscratch2
864 ADD rscratch , rscratch,#2
865 STMFD r13!,{rscratch2}
867 LDMFD r13!,{rscratch2}
868 ORR rscratch , rscratch2, rscratch, LSL #16
870 .macro DirectIndirectIndexed0
872 LDRB rscratch , [rpc], #1
873 ADD rscratch , reg_d, rscratch, LSL #16
874 MOV rscratch, rscratch, LSR #16
876 ORR rscratch, rscratch,reg_d_bank, LSL #16
877 ADD rscratch, rscratch,reg_y, LSR #16
879 .macro DirectIndirectIndexed1
881 LDRB rscratch , [rpc], #1
882 ADD rscratch , reg_d, rscratch, LSL #16
883 MOV rscratch, rscratch, LSR #16
885 ORR rscratch, rscratch,reg_d_bank, LSL #16
886 ADD rscratch, rscratch,reg_y, LSR #24
888 .macro DirectIndirectIndexedLong0
890 LDRB rscratch , [rpc], #1
891 ADD rscratch , reg_d, rscratch, LSL #16
892 MOV rscratch, rscratch, LSR #16
893 S9xGetWordLowRegNS rscratch2
894 ADD rscratch , rscratch,#2
895 STMFD r13!,{rscratch2}
897 LDMFD r13!,{rscratch2}
898 ORR rscratch , rscratch2, rscratch, LSL #16
899 ADD rscratch, rscratch,reg_y, LSR #16
901 .macro DirectIndirectIndexedLong1
903 LDRB rscratch , [rpc], #1
904 ADD rscratch , reg_d, rscratch, LSL #16
905 MOV rscratch, rscratch, LSR #16
906 S9xGetWordLowRegNS rscratch2
907 ADD rscratch , rscratch,#2
908 STMFD r13!,{rscratch2}
910 LDMFD r13!,{rscratch2}
911 ORR rscratch , rscratch2, rscratch, LSL #16
912 ADD rscratch, rscratch,reg_y, LSR #24
914 .macro DirectIndexedIndirect0
916 LDRB rscratch , [rpc], #1
917 ADD rscratch2 , reg_d , reg_x
918 ADD rscratch , rscratch2 , rscratch, LSL #16
919 MOV rscratch, rscratch, LSR #16
921 ORR rscratch , rscratch , reg_d_bank, LSL #16
923 .macro DirectIndexedIndirect1
925 LDRB rscratch , [rpc], #1
926 ADD rscratch2 , reg_d , reg_x, LSR #8
927 ADD rscratch , rscratch2 , rscratch, LSL #16
928 MOV rscratch, rscratch, LSR #16
930 ORR rscratch , rscratch , reg_d_bank, LSL #16
932 .macro DirectIndexedX0
934 LDRB rscratch , [rpc], #1
935 ADD rscratch2 , reg_d , reg_x
936 ADD rscratch , rscratch2 , rscratch, LSL #16
937 MOV rscratch, rscratch, LSR #16
939 .macro DirectIndexedX1
941 LDRB rscratch , [rpc], #1
942 ADD rscratch2 , reg_d , reg_x, LSR #8
943 ADD rscratch , rscratch2 , rscratch, LSL #16
944 MOV rscratch, rscratch, LSR #16
946 .macro DirectIndexedY0
948 LDRB rscratch , [rpc], #1
949 ADD rscratch2 , reg_d , reg_y
950 ADD rscratch , rscratch2 , rscratch, LSL #16
951 MOV rscratch, rscratch, LSR #16
953 .macro DirectIndexedY1
955 LDRB rscratch , [rpc], #1
956 ADD rscratch2 , reg_d , reg_y, LSR #8
957 ADD rscratch , rscratch2 , rscratch, LSL #16
958 MOV rscratch, rscratch, LSR #16
961 ADD rscratch, rpc, reg_p_bank, LSL #16
962 SUB rscratch, rscratch, regpcbase
966 ADD rscratch, rpc, reg_p_bank, LSL #16
967 SUB rscratch, rscratch, regpcbase
972 LDRSB rscratch , [rpc],#1
973 ADD rscratch , rscratch , rpc
974 SUB rscratch , rscratch, regpcbase
975 UXTH rscratch,rscratch
977 .macro asmRelativeLong
979 LDRB rscratch2 , [rpc, #1]
980 LDRB rscratch , [rpc], #2
981 ORR rscratch , rscratch, rscratch2, LSL #8
982 SUB rscratch2 , rpc, regpcbase
983 ADD rscratch , rscratch2, rscratch
984 BIC rscratch,rscratch,#0x00FF0000
988 .macro StackasmRelative
990 LDRB rscratch , [rpc], #1
991 ADD rscratch , rscratch, reg_s
992 BIC rscratch,rscratch,#0x00FF0000
994 .macro StackasmRelativeIndirectIndexed0
996 LDRB rscratch , [rpc], #1
997 ADD rscratch , rscratch, reg_s
998 BIC rscratch,rscratch,#0x00FF0000
1000 ORR rscratch , rscratch, reg_d_bank, LSL #16
1001 ADD rscratch , rscratch, reg_y, LSR #16
1002 BIC rscratch, rscratch, #0xFF000000
1004 .macro StackasmRelativeIndirectIndexed1
1006 LDRB rscratch , [rpc], #1
1007 ADD rscratch , rscratch, reg_s
1008 BIC rscratch,rscratch,#0x00FF0000
1010 ORR rscratch , rscratch, reg_d_bank, LSL #16
1011 ADD rscratch , rscratch, reg_y, LSR #24
1012 BIC rscratch, rscratch, #0xFF000000
1016 /****************************************/
1028 SUB rscratch,reg_s,#1
1033 MOV rscratch2,rscratch
1034 SUB rscratch,reg_s,#1
1035 S9xSetWordLow rscratch2
1039 SUB rscratch,reg_s,#1
1047 ADD rscratch,reg_s,#1
1050 MOV \reg,rscratch,LSL #24
1053 ADD rscratch,reg_s,#1
1058 ADD rscratch,reg_s,#1
1064 ADD rscratch,reg_s,#1
1069 ADD rscratch,reg_s,#1
1072 MOV \reg,rscratch,LSL #16
1076 ADD rscratch,reg_s,#1
1085 ADD rscratch,reg_s,#1
1088 MOVS \reg,rscratch,LSL #24
1091 ADD rscratch,reg_s,#1
1094 MOVS rscratch,rscratch,LSL #24
1096 .macro PullBLowS reg
1097 ADD rscratch,reg_s,#1
1103 ADD rscratch,reg_s,#1
1106 MOVS rscratch,rscratch
1109 ADD rscratch,reg_s,#1
1112 MOVS \reg,rscratch, LSL #16
1115 ADD rscratch,reg_s,#1
1118 MOVS rscratch,rscratch, LSL #16
1120 .macro PullWLowS reg
1121 ADD rscratch,reg_s,#1
1127 ADD rscratch,reg_s,#1
1130 MOVS rscratch,rscratch
1133 @ START OF PROGRAM CODE
1139 .globl asmS9xGetByte
1140 .globl asmS9xGetWord
1141 .globl asmS9xSetByte
1142 .globl asmS9xSetWord
1144 @ uint8 aaS9xGetByte(uint32 address);
1146 @ in : R0 = 0x00hhmmll
1147 @ out : R0 = 0x000000ll
1148 @ DESTROYED : R1,R2,R3
1149 @ UPDATE : reg_cycles
1151 MOV R1,R0,LSR #MEMMAP_SHIFT
1152 @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1153 @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1154 @ so AND MEMMAP_MASK is BIC 0xFF000
1156 @ R2 <= Map[block] (GetAddress)
1157 LDR R2,[reg_cpu_var,#Map_ofs]
1158 LDR R2,[R2,R1,LSL #2]
1160 BLO GBSpecial @ special
1161 @ Direct ROM/RAM acess
1162 @ R2 <= GetAddress + Address & 0xFFFF
1163 @ R3 <= MemorySpeed[block]
1164 LDR R3,[reg_cpu_var,#MemorySpeed_ofs]
1167 ADD R2,R2,R0,LSR #16
1169 ADD reg_cycles,reg_cycles,R3
1170 @ R3 = BlockIsRAM[block]
1171 LDR R3,[reg_cpu_var,#BlockIsRAM_ofs]
1172 @ Get value to return
1176 @ if BlockIsRAM => update for CPUShutdown
1177 LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1178 STRNE R1,[reg_cpu_var,#WaitAddress_ofs]
1180 LDMFD R13!,{PC} @ Return
1183 LDR PC,[PC,R2,LSL #2]
1184 MOV R0,R0 @ nop, for align
1202 LDRB R1,[reg_cpu_var,#InDMA_ofs]
1204 ADDEQ reg_cycles,reg_cycles,#ONE_CYCLE @ No -> update Cycles
1205 MOV R0,R0,LSL #16 @ S9xGetPPU(Address&0xFFFF);
1206 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1211 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1212 LDMFD R13!,{PC} @ Return
1214 ADD reg_cycles,reg_cycles,#ONE_CYCLE @ update Cycles
1215 MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1216 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1221 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1222 LDMFD R13!,{PC} @ Return
1224 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1225 MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1226 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1231 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1232 LDMFD R13!,{PC} @ Return
1234 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1235 LDRH R2,[reg_cpu_var,#SRAMMask]
1236 LDR R1,[reg_cpu_var,#SRAM]
1237 AND R0,R2,R0 @ Address&SRAMMask
1238 LDRB R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask
1242 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1246 MOV R1,R1,LSR #17 @ Address&0x7FFF
1247 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1249 LDRH R2,[reg_cpu_var,#SRAMMask]
1250 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1251 LDR R1,[reg_cpu_var,#SRAM]
1252 AND R0,R2,R0 @ Address&SRAMMask
1253 LDRB R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask
1254 LDMFD R13!,{PC} @ return
1259 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1263 /*ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1267 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1268 MOV R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1269 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1274 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1275 LDMFD R13!,{PC} @ Return
1279 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1280 MOV R0,R0,LSR #17 @ Address&0x7FFF
1281 LDR R1,[reg_cpu_var,#BWRAM]
1282 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1283 LDRB R0,[R0,R1] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1287 @ uint16 aaS9xGetWord(uint32 address);
1289 @ in : R0 = 0x00hhmmll
1290 @ out : R0 = 0x000000ll
1291 @ DESTROYED : R1,R2,R3
1292 @ UPDATE : reg_cycles
1317 MOV R1,R0,LSR #MEMMAP_SHIFT
1318 @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1319 @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1320 @ so AND MEMMAP_MASK is BIC 0xFF000
1322 @ R2 <= Map[block] (GetAddress)
1323 LDR R2,[reg_cpu_var,#Map_ofs]
1324 LDR R2,[R2,R1,LSL #2]
1326 BLO GWSpecial @ special
1327 @ Direct ROM/RAM acess
1331 @ R2 <= GetAddress + Address & 0xFFFF
1332 @ R3 <= MemorySpeed[block]
1333 LDR R3,[reg_cpu_var,#MemorySpeed_ofs]
1338 ADD reg_cycles,reg_cycles,R3, LSL #1
1339 @ R3 = BlockIsRAM[block]
1340 LDR R3,[reg_cpu_var,#BlockIsRAM_ofs]
1341 @ Get value to return
1345 @ if BlockIsRAM => update for CPUShutdown
1346 LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1347 STRNE R1,[reg_cpu_var,#WaitAddress_ofs]
1349 LDMFD R13!,{PC} @ Return
1354 LDRB R3,[R2,R3,LSR #16] @ GetAddress+ (Address+1)&0xFFFF
1355 LDRB R0,[R2,R0,LSR #16] @ GetAddress+ Address&0xFFFF
1358 @ if BlockIsRAM => update for CPUShutdown
1359 LDR R3,[reg_cpu_var,#BlockIsRAM_ofs]
1360 LDR R2,[reg_cpu_var,#MemorySpeed_ofs]
1361 LDRB R3,[R3,R1] @ R3 = BlockIsRAM[block]
1362 LDRB R2,[R2,R1] @ R2 <= MemorySpeed[block]
1363 MOVS R3,R3 @ IsRAM ? CPUShutdown stuff
1364 LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1365 STRNE R1,[reg_cpu_var,#WaitAddress_ofs]
1366 ADD reg_cycles,reg_cycles,R2, LSL #1 @ Update CPU.Cycles
1367 LDMFD R13!,{PC} @ Return
1369 LDR PC,[PC,R2,LSL #2]
1370 MOV R0,R0 @ nop, for align
1386 /* MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM,
1387 MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP,
1388 MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/
1392 LDRB R1,[reg_cpu_var,#InDMA_ofs]
1394 ADDEQ reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ No -> update Cycles
1395 MOV R0,R0,LSL #16 @ S9xGetPPU(Address&0xFFFF);
1396 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1403 @ BIC R0,R0,#0x10000
1407 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1408 LDMFD R13!,{PC} @ Return
1410 ADD reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ update Cycles
1411 MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1412 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1419 @ BIC R0,R0,#0x10000
1423 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1424 LDMFD R13!,{PC} @ Return
1426 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1427 MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1428 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1435 @ BIC R0,R0,#0x10000
1439 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1440 LDMFD R13!,{PC} @ Return
1442 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1446 LDRH R2,[reg_cpu_var,#SRAMMask]
1447 LDR R1,[reg_cpu_var,#SRAM]
1448 AND R3,R2,R0 @ Address&SRAMMask
1449 LDRH R0,[R3,R1] @ *Memory.SRAM + Address&SRAMMask
1450 LDMFD R13!,{PC} @ return
1452 LDRH R2,[reg_cpu_var,#SRAMMask]
1453 LDR R1,[reg_cpu_var,#SRAM]
1454 AND R3,R2,R0 @ Address&SRAMMask
1456 AND R2,R0,R2 @ Address&SRAMMask
1457 LDRB R3,[R1,R3] @ *Memory.SRAM + Address&SRAMMask
1458 LDRB R2,[R1,R2] @ *Memory.SRAM + Address&SRAMMask
1460 LDMFD R13!,{PC} @ return
1463 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1470 MOV R1,R1,LSR #17 @ Address&0x7FFF
1471 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1473 LDRH R2,[reg_cpu_var,#SRAMMask]
1474 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1475 LDR R1,[reg_cpu_var,#SRAM]
1476 AND R0,R2,R0 @ Address&SRAMMask
1477 LDRH R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask
1478 LDMFD R13!,{PC} @ return
1483 MOV R3,R3,LSR #17 @ Address&0x7FFF
1484 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1487 SUB R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1490 MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF
1491 MOV R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1493 LDRH R3,[reg_cpu_var,#SRAMMask] @ reload mask
1494 SUB R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1495 AND R2,R3,R2 @ Address...&SRAMMask
1496 AND R0,R3,R0 @ (Address+1...)&SRAMMask
1498 LDR R3,[reg_cpu_var,#SRAM]
1499 LDRB R0,[R0,R3] @ *Memory.SRAM + (Address...)&SRAMMask
1500 LDRB R2,[R2,R3] @ *Memory.SRAM + (Address+1...)&SRAMMask
1503 LDMFD R13!,{PC} @ return
1508 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1513 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1517 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1518 MOV R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1519 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1526 @ BIC R0,R0,#0x10000
1530 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1531 LDMFD R13!,{PC} @ Return
1536 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1537 MOV R0,R0,LSR #17 @ Address&0x7FFF
1538 LDR R1,[reg_cpu_var,#BWRAM]
1539 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1540 LDRH R0,[R1,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1541 LDMFD R13!,{PC} @ return
1544 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1546 MOV R0,R0,LSR #17 @ Address&0x7FFF
1547 MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF
1548 LDR R1,[reg_cpu_var,#BWRAM]
1549 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1550 SUB R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
1551 LDRB R0,[R1,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1552 LDRB R3,[R1,R3] @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
1554 LDMFD R13!,{PC} @ return
1559 @ void aaS9xSetByte(uint32 address,uint8 val);
1561 @ in : R0=0x00hhmmll R1=0x000000ll
1562 @ DESTROYED : R0,R1,R2,R3
1563 @ UPDATE : reg_cycles
1566 STR R2,[reg_cpu_var,#WaitAddress_ofs]
1570 MOV R3,R0,LSR #MEMMAP_SHIFT
1571 @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1572 @ R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1573 @ so AND MEMMAP_MASK is BIC 0xFF000
1575 @ R2 <= Map[block] (SetAddress)
1576 LDR R2,[reg_cpu_var,#WriteMap_ofs]
1577 LDR R2,[R2,R3,LSL #2]
1579 BLO SBSpecial @ special
1580 @ Direct ROM/RAM acess
1582 @ R2 <= SetAddress + Address & 0xFFFF
1584 ADD R2,R2,R0,LSR #16
1585 LDR R0,[reg_cpu_var,#MemorySpeed_ofs]
1588 @ R0 <= MemorySpeed[block]
1591 ADD reg_cycles,reg_cycles,R0
1593 @ only SA1 here : TODO
1597 LDR PC,[PC,R2,LSL #2]
1598 MOV R0,R0 @ nop, for align
1616 LDRB R2,[reg_cpu_var,#InDMA_ofs]
1618 ADDEQ reg_cycles,reg_cycles,#ONE_CYCLE @ No -> update Cycles
1620 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1628 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1629 LDMFD R13!,{PC} @ Return
1631 ADD reg_cycles,reg_cycles,#ONE_CYCLE @ update Cycles
1633 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1634 MOV R0,R0,LSR #16 @ Address&0xFFFF
1641 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1642 LDMFD R13!,{PC} @ Return
1644 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1646 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1647 MOV R0,R0,LSR #16 @ Address&0xFFFF
1654 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1655 LDMFD R13!,{PC} @ Return
1657 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1658 LDRH R2,[reg_cpu_var,#SRAMMask]
1660 LDMEQFD R13!,{PC} @ return if SRAMMask=0
1661 LDR R3,[reg_cpu_var,#SRAM]
1662 AND R0,R2,R0 @ Address&SRAMMask
1663 STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask
1666 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1667 LDMFD R13!,{PC} @ return
1670 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1674 MOV R3,R3,LSR #17 @ Address&0x7FFF
1675 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1678 LDRH R2,[reg_cpu_var,#SRAMMask]
1680 LDMEQFD R13!,{PC} @ return if SRAMMask=0
1682 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1683 LDR R3,[reg_cpu_var,#SRAM]
1684 AND R0,R2,R0 @ Address&SRAMMask
1685 STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask
1688 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1689 LDMFD R13!,{PC} @ return
1694 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1697 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1699 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1700 MOV R0,R0,LSR #16 @ Address&0xFFFF
1707 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1708 LDMFD R13!,{PC} @ Return
1711 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1712 MOV R0,R0,LSR #17 @ Address&0x7FFF
1713 LDR R2,[reg_cpu_var,#BWRAM]
1714 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1715 STRB R1,[R0,R2] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1718 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1724 @ void aaS9xSetWord(uint32 address,uint16 val);
1726 @ in : R0 = 0x00hhmmll R1=0x0000hhll
1727 @ DESTROYED : R0,R1,R2,R3
1728 @ UPDATE : reg_cycles
1752 STR R2,[reg_cpu_var,#WaitAddress_ofs]
1755 MOV R3,R0,LSR #MEMMAP_SHIFT
1756 @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1757 @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1758 @ so AND MEMMAP_MASK is BIC 0xFF000
1760 @ R2 <= Map[block] (SetAddress)
1761 LDR R2,[reg_cpu_var,#WriteMap_ofs]
1762 LDR R2,[R2,R3,LSL #2]
1764 BLO SWSpecial @ special
1765 @ Direct ROM/RAM acess
1768 @ check if address is 16bits aligned or not
1773 ADD R2,R2,R0,LSR #16 @ address & 0xFFFF + SetAddress
1774 LDR R0,[reg_cpu_var,#MemorySpeed_ofs]
1777 @ R1 <= MemorySpeed[block]
1780 ADD reg_cycles,reg_cycles,R0, LSL #1
1782 @ only SA1 here : TODO
1787 @ R1 = (Address&0xFFFF)<<16
1789 @ First write @address
1790 STRB R1,[R2,R0,LSR #16]
1793 @ Second write @address+1
1794 STRB R1,[R2,R0,LSR #16]
1795 @ R1 <= MemorySpeed[block]
1796 LDR R0,[reg_cpu_var,#MemorySpeed_ofs]
1799 ADD reg_cycles,reg_cycles,R0,LSL #1
1801 @ only SA1 here : TODO
1805 LDR PC,[PC,R2,LSL #2]
1806 MOV R0,R0 @ nop, for align
1824 LDRB R2,[reg_cpu_var,#InDMA_ofs]
1826 ADDEQ reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ No -> update Cycles
1828 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1842 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1843 LDMFD R13!,{PC} @ Return
1845 ADD reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ update Cycles
1847 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1848 MOV R0,R0,LSR #16 @ Address&0xFFFF
1857 UXTB R0,R0,ROR #8 @ ((R0 >> 8) & 0xFF)
1861 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1862 LDMFD R13!,{PC} @ Return
1864 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1866 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1867 MOV R0,R0,LSR #16 @ Address&0xFFFF
1880 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1881 LDMFD R13!,{PC} @ Return
1883 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1884 LDRH R2,[reg_cpu_var,#SRAMMask]
1886 LDMEQFD R13!,{PC} @ return if SRAMMask=0
1888 AND R3,R2,R0 @ Address&SRAMMask
1892 LDR R0,[reg_cpu_var,#SRAM]
1893 STRH R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask
1895 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1896 LDMFD R13!,{PC} @ return
1900 AND R2,R2,R0 @ (Address+1)&SRAMMask
1901 LDR R0,[reg_cpu_var,#SRAM]
1902 STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask
1904 STRB R1,[R0,R2] @ *Memory.SRAM + (Address+1)&SRAMMask
1906 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1907 LDMFD R13!,{PC} @ return
1910 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1912 LDRH R2,[reg_cpu_var,#SRAMMask]
1914 LDMEQFD R13!,{PC} @ return if SRAMMask=0
1921 MOV R3,R3,LSR #17 @ Address&0x7FFF
1922 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1924 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1925 LDRH R2,[reg_cpu_var,#SRAMMask]
1926 LDR R3,[reg_cpu_var,#SRAM]
1927 AND R0,R2,R0 @ Address&SRAMMask
1928 STRH R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask
1930 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1931 LDMFD R13!,{PC} @ return
1935 MOV R3,R3,LSR #17 @ Address&0x7FFF
1936 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1938 SUB R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1943 MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF
1944 MOV R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1946 LDRH R3,[reg_cpu_var,#SRAMMask] @ reload mask
1947 SUB R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1948 AND R2,R3,R2 @ Address...&SRAMMask
1949 AND R0,R3,R0 @ (Address+1...)&SRAMMask
1951 LDR R3,[reg_cpu_var,#SRAM]
1952 STRB R1,[R2,R3] @ *Memory.SRAM + (Address...)&SRAMMask
1954 STRB R1,[R0,R3] @ *Memory.SRAM + (Address+1...)&SRAMMask
1957 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1958 LDMFD R13!,{PC} @ return
1963 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1964 LDMFD R13!,{PC} @ return
1966 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1968 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1969 MOV R0,R0,LSR #16 @ Address&0xFFFF
1982 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1983 LDMFD R13!,{PC} @ Return
1985 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1990 LDR R2,[reg_cpu_var,#BWRAM]
1991 MOV R0,R0,LSR #17 @ Address&0x7FFF
1992 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1994 STRH R1,[R0,R2] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1995 STRB R3,[reg_cpu_var,#SRAMModified_ofs]
1996 LDMFD R13!,{PC} @ return
2000 MOV R0,R0,LSR #17 @ Address&0x7FFF
2001 MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF
2002 LDR R2,[reg_cpu_var,#BWRAM]
2003 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
2004 SUB R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
2005 STRB R1,[R2,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
2007 STRB R1,[R2,R3] @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
2009 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
2010 LDMFD R13!,{PC} @ return
2016 /*****************************************************************
2018 *****************************************************************/
2021 @ CC : ARM Carry Clear
2022 BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero
2023 @ CS : ARM Carry Set
2024 ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2027 @ NE : ARM Zero Clear
2028 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2030 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2033 @ NE : ARM Zero Clear
2034 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2036 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2037 @ PL : ARM Neg Clear
2038 BICPL rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2040 ORRMI rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set N to one
2043 /*****************************************************************
2045 *****************************************************************/
2051 TST rstatus, #MASK_DECIMAL
2056 STMFD R13!,{rscratch}
2057 MOV rscratch4,#0x0F000000
2058 @ rscratch2=xxW1xxxxxxxxxxxx
2059 AND rscratch2, rscratch, rscratch4
2060 @ rscratch=xxW2xxxxxxxxxxxx
2061 AND rscratch, rscratch4, rscratch, LSR #4
2062 @ rscratch3=xxA2xxxxxxxxxxxx
2063 AND rscratch3, rscratch4, reg_a, LSR #4
2064 @ rscratch4=xxA1xxxxxxxxxxxx
2065 AND rscratch4,reg_a,rscratch4
2067 TST rstatus, #MASK_CARRY
2068 ADDNE rscratch2, rscratch2, #0x01000000
2069 ADD rscratch2,rscratch2,rscratch4
2071 CMP rscratch2, #0x09000000
2073 SUBGT rscratch2, rscratch2, #0x0A000000
2075 ADDGT rscratch3, rscratch3, #0x01000000
2077 ADD rscratch3, rscratch3, rscratch
2079 CMP rscratch3, #0x09000000
2081 SUBGT rscratch3, rscratch3, #0x0A000000
2083 ORRGT rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2085 BICLE rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero
2086 @ gather rscratch3 and rscratch2 into ans8
2087 @ rscratch3 : 0R2000000
2088 @ rscratch2 : 0R1000000
2090 ORR rscratch2, rscratch2, rscratch3, LSL #4
2091 LDMFD R13!,{rscratch}
2093 AND rscratch,rscratch,#0x80000000
2094 @ (register.AL ^ Work8)
2095 EORS rscratch3, reg_a, rscratch
2096 BICNE rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2099 EORS rscratch3, rscratch2, rscratch
2101 TSTNE rscratch3,#0x80000000
2102 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2103 ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one
2105 MOVS reg_a, rscratch2
2110 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2111 SUBCS rscratch, rscratch, #0x100
2112 ADCS reg_a, reg_a, rscratch, ROR #8
2114 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2115 BICVC rstatus, rstatus, #MASK_OVERFLOW
2119 ANDS reg_a, reg_a, #0xFF000000
2126 TST rstatus, #MASK_DECIMAL
2130 @ rscratch = W3W2W1W0........
2131 LDR rscratch4, = 0x0F0F0000
2132 @ rscratch2 = xxW2xxW0xxxxxx
2133 @ rscratch3 = xxW3xxW1xxxxxx
2134 AND rscratch2, rscratch4, rscratch
2135 AND rscratch3, rscratch4, rscratch, LSR #4
2136 @ rscratch2 = xxW3xxW1xxW2xxW0
2137 ORR rscratch2, rscratch3, rscratch2, LSR #16
2138 @ rscratch3 = xxA2xxA0xxxxxx
2139 @ rscratch4 = xxA3xxA1xxxxxx
2140 @ rscratch2 = xxA3xxA1xxA2xxA0
2141 AND rscratch3, rscratch4, reg_a
2142 AND rscratch4, rscratch4, reg_a, LSR #4
2143 ORR rscratch3, rscratch4, rscratch3, LSR #16
2144 ADD rscratch2, rscratch3, rscratch2
2145 LDR rscratch4, = 0x0F0F0000
2147 TST rstatus, #MASK_CARRY
2148 ADDNE rscratch2, rscratch2, #0x1
2149 @ rscratch2 = A + W + C
2151 AND rscratch3, rscratch2, #0x0000001F
2152 CMP rscratch3, #0x00000009
2153 ADDHI rscratch2, rscratch2, #0x00010000
2154 SUBHI rscratch2, rscratch2, #0x0000000A
2156 AND rscratch3, rscratch2, #0x001F0000
2157 CMP rscratch3, #0x00090000
2158 ADDHI rscratch2, rscratch2, #0x00000100
2159 SUBHI rscratch2, rscratch2, #0x000A0000
2161 AND rscratch3, rscratch2, #0x00001F00
2162 CMP rscratch3, #0x00000900
2163 SUBHI rscratch2, rscratch2, #0x00000A00
2164 ADDHI rscratch2, rscratch2, #0x01000000
2166 AND rscratch3, rscratch2, #0x1F000000
2167 CMP rscratch3, #0x09000000
2168 SUBHI rscratch2, rscratch2, #0x0A000000
2170 ORRHI rstatus, rstatus, #MASK_CARRY
2172 BICLS rstatus, rstatus, #MASK_CARRY
2173 @ rscratch2 = xxR3xxR1xxR2xxR0
2175 @ rscratch3 = xxR3xxR1xxxxxxxx
2176 AND rscratch3, rscratch4, rscratch2
2177 @ rscratch2 = xxR2xxR0xxxxxxxx
2178 AND rscratch2, rscratch4, rscratch2,LSL #16
2179 @ rscratch2 = R3R2R1R0xxxxxxxx
2180 ORR rscratch2, rscratch2,rscratch3,LSL #4
2182 AND rscratch,rscratch,#0x80000000
2183 @ (register.AL ^ Work8)
2184 EORS rscratch3, reg_a, rscratch
2185 BICNE rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2188 EORS rscratch3, rscratch2, rscratch
2189 TSTNE rscratch3,#0x80000000
2190 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2191 ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one
2193 MOVS reg_a, rscratch2
2198 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2199 SUBCS rscratch, rscratch, #0x10000
2200 ADCS reg_a, reg_a,rscratch, ROR #16
2202 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2203 BICVC rstatus, rstatus, #MASK_OVERFLOW
2204 MOV reg_a, reg_a, LSR #16
2208 MOVS reg_a, reg_a, LSL #16
2217 ANDS reg_a, reg_a, rscratch
2222 ANDS reg_a, reg_a, rscratch
2227 MOVS reg_a, reg_a, LSL #1
2234 MOVS reg_a, reg_a, LSL #1
2240 S9xGetWordRegNS rscratch2 @ do not destroy Opadress in rscratch
2241 MOVS rscratch2, rscratch2, LSL #1
2244 S9xSetWord rscratch2
2248 S9xGetByteRegNS rscratch2 @ do not destroy Opadress in rscratch
2249 MOVS rscratch2, rscratch2, LSL #1
2252 S9xSetByte rscratch2
2257 MOVS rscratch2, rscratch, LSL #1
2258 @ Trick in ASM : shift one more bit : ARM C = Snes N
2260 @ If Carry Set, then Set Neg in SNES
2261 BICCC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set C to zero
2262 ORRCS rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set C to one
2263 @ If Neg Set, then Set Overflow in SNES
2264 BICPL rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set N to zero
2265 ORRMI rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set N to one
2267 @ Now do a real AND with A register
2268 @ Set Zero Flag, bit test
2269 ANDS rscratch2, reg_a, rscratch
2270 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2271 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2276 MOVS rscratch2, rscratch, LSL #1
2277 @ Trick in ASM : shift one more bit : ARM C = Snes N
2279 @ If Carry Set, then Set Neg in SNES
2280 BICCC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2281 ORRCS rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set N to one
2282 @ If Neg Set, then Set Overflow in SNES
2283 BICPL rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2284 ORRMI rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one
2285 @ Now do a real AND with A register
2286 @ Set Zero Flag, bit test
2287 ANDS rscratch2, reg_a, rscratch
2288 @ Bit set ->Z=0->xxxNE Clear flag
2289 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2290 @ Bit clear->Z=1->xxxEQ Set flag
2291 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2295 SUBS rscratch2,reg_a,rscratch
2296 BICCC rstatus, rstatus, #MASK_CARRY
2297 ORRCS rstatus, rstatus, #MASK_CARRY
2303 SUBS rscratch2,reg_a,rscratch
2304 BICCC rstatus, rstatus, #MASK_CARRY
2305 ORRCS rstatus, rstatus, #MASK_CARRY
2311 SUBS rscratch2,reg_x,rscratch
2312 BICCC rstatus, rstatus, #MASK_CARRY
2313 ORRCS rstatus, rstatus, #MASK_CARRY
2318 SUBS rscratch2,reg_x,rscratch
2319 BICCC rstatus, rstatus, #MASK_CARRY
2320 ORRCS rstatus, rstatus, #MASK_CARRY
2325 SUBS rscratch2,reg_y,rscratch
2326 BICCC rstatus, rstatus, #MASK_CARRY
2327 ORRCS rstatus, rstatus, #MASK_CARRY
2332 SUBS rscratch2,reg_y,rscratch
2333 BICCC rstatus, rstatus, #MASK_CARRY
2334 ORRCS rstatus, rstatus, #MASK_CARRY
2339 SUBS reg_a, reg_a, #0x01000000
2340 STR rscratch,[reg_cpu_var,#WaitAddress_ofs]
2346 SUBS reg_a, reg_a, #0x00010000
2347 STR rscratch,[reg_cpu_var,#WaitAddress_ofs]
2352 S9xGetWordRegNS rscratch2 @ do not destroy Opadress in rscratch
2354 SUBS rscratch2, rscratch2, #0x00010000
2355 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2357 S9xSetWord rscratch2
2361 S9xGetByteRegNS rscratch2 @ do not destroy Opadress in rscratch
2363 SUBS rscratch2, rscratch2, #0x01000000
2364 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2366 S9xSetByte rscratch2
2371 EORS reg_a, reg_a, rscratch
2376 EORS reg_a, reg_a, rscratch
2381 ADDS reg_a, reg_a, #0x01000000
2382 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2388 ADDS reg_a, reg_a, #0x00010000
2389 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2394 S9xGetWordRegNS rscratch2
2396 ADDS rscratch2, rscratch2, #0x00010000
2397 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2399 S9xSetWord rscratch2
2403 S9xGetByteRegNS rscratch2
2405 ADDS rscratch2, rscratch2, #0x01000000
2406 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2408 S9xSetByte rscratch2
2412 S9xGetWordRegStatus reg_a
2416 S9xGetByteRegStatus reg_a
2420 S9xGetWordRegStatus reg_x
2424 S9xGetByteRegStatus reg_x
2428 S9xGetWordRegStatus reg_y
2432 S9xGetByteRegStatus reg_y
2436 BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2437 MOVS reg_a, reg_a, LSR #17 @ hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll
2439 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2440 MOV reg_a, reg_a, LSL #16 @ -> 0lllllll 00000000 00000000 00000000
2441 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2442 @ Note : the two MOV are included between instruction, to optimize
2448 BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2449 MOVS reg_a, reg_a, LSR #25 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
2451 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2452 MOV reg_a, reg_a, LSL #24 @ -> 00000000 00000000 00000000 0lllllll
2453 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2454 @ Note : the two MOV are included between instruction, to optimize
2460 S9xGetWordRegNS rscratch2
2461 @ N set to zero by >> 1 LSR
2462 BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2463 MOVS rscratch2, rscratch2, LSR #17 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
2465 BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero
2466 ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2468 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2469 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2470 S9xSetWordLow rscratch2
2474 S9xGetByteRegNS rscratch2
2475 @ N set to zero by >> 1 LSR
2476 BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2477 MOVS rscratch2, rscratch2, LSR #25 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
2479 BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero
2480 ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2482 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2483 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2484 S9xSetByteLow rscratch2
2489 ORRS reg_a, reg_a, rscratch
2494 ORRS reg_a, reg_a, rscratch
2498 TST rstatus, #MASK_CARRY
2499 ORRNE reg_a, reg_a, #0x00008000
2500 MOVS reg_a, reg_a, LSL #1
2506 TST rstatus, #MASK_CARRY
2507 ORRNE reg_a, reg_a, #0x00800000
2508 MOVS reg_a, reg_a, LSL #1
2514 S9xGetWordRegNS rscratch2
2515 TST rstatus, #MASK_CARRY
2516 ORRNE rscratch2, rscratch2, #0x00008000
2517 MOVS rscratch2, rscratch2, LSL #1
2520 S9xSetWord rscratch2
2524 S9xGetByteRegNS rscratch2
2525 TST rstatus, #MASK_CARRY
2526 ORRNE rscratch2, rscratch2, #0x00800000
2527 MOVS rscratch2, rscratch2, LSL #1
2530 S9xSetByte rscratch2
2534 MOV reg_a,reg_a, LSR #16
2535 TST rstatus, #MASK_CARRY
2536 ORRNE reg_a, reg_a, #0x00010000
2537 ORRNE rstatus,rstatus,#MASK_NEG
2538 BICEQ rstatus,rstatus,#MASK_NEG
2539 MOVS reg_a,reg_a,LSR #1
2542 MOV reg_a,reg_a, LSL #16
2546 MOV reg_a,reg_a, LSR #24
2547 TST rstatus, #MASK_CARRY
2548 ORRNE reg_a, reg_a, #0x00000100
2549 ORRNE rstatus,rstatus,#MASK_NEG
2550 BICEQ rstatus,rstatus,#MASK_NEG
2551 MOVS reg_a,reg_a,LSR #1
2554 MOV reg_a,reg_a, LSL #24
2558 S9xGetWordLowRegNS rscratch2
2559 TST rstatus, #MASK_CARRY
2560 ORRNE rscratch2, rscratch2, #0x00010000
2561 ORRNE rstatus,rstatus,#MASK_NEG
2562 BICEQ rstatus,rstatus,#MASK_NEG
2563 MOVS rscratch2,rscratch2,LSR #1
2566 S9xSetWordLow rscratch2
2571 S9xGetByteLowRegNS rscratch2
2572 TST rstatus, #MASK_CARRY
2573 ORRNE rscratch2, rscratch2, #0x00000100
2574 ORRNE rstatus,rstatus,#MASK_NEG
2575 BICEQ rstatus,rstatus,#MASK_NEG
2576 MOVS rscratch2,rscratch2,LSR #1
2579 S9xSetByteLow rscratch2
2584 TST rstatus, #MASK_DECIMAL
2589 STMFD R13!,{rscratch9}
2590 MOV rscratch9,#0x000F0000
2591 @ rscratch2 - result
2592 @ rscratch3 - scratch
2593 @ rscratch4 - scratch
2594 @ rscratch9 - pattern
2596 AND rscratch2, rscratch, #0x000F0000
2597 TST rstatus, #MASK_CARRY
2598 ADDEQ rscratch2, rscratch2, #0x00010000 @ W1=W1+!Carry
2599 AND rscratch4, reg_a, #0x000F0000
2600 SUB rscratch2, rscratch4,rscratch2 @ R1=A1-W1-!Carry
2601 CMP rscratch2, #0x00090000 @ if R1 > 9
2602 ADDHI rscratch2, rscratch2, #0x000A0000 @ then R1 += 10
2603 AND rscratch2, rscratch2, #0x000F0000
2605 AND rscratch3, rscratch9, rscratch, LSR #4
2606 ADDHI rscratch3, rscratch3, #0x00010000 @ then (W2++)
2608 AND rscratch4, rscratch9, reg_a, LSR #4
2609 SUB rscratch3, rscratch4, rscratch3 @ R2=A2-W2
2610 CMP rscratch3, #0x00090000 @ if R2 > 9
2611 ADDHI rscratch3, rscratch3, #0x000A0000 @ then R2 += 10
2612 AND rscratch3, rscratch3, #0x000F0000
2613 ORR rscratch2, rscratch2, rscratch3,LSL #4
2615 AND rscratch3, rscratch9, rscratch, LSR #8
2616 ADDHI rscratch3, rscratch3, #0x00010000 @ then (W3++)
2618 AND rscratch4, rscratch9, reg_a, LSR #8
2619 SUB rscratch3, rscratch4, rscratch3 @ R3=A3-W3
2620 CMP rscratch3, #0x00090000 @ if R3 > 9
2621 ADDHI rscratch3, rscratch3, #0x000A0000 @ then R3 += 10
2622 AND rscratch3, rscratch3, #0x000F0000
2623 ORR rscratch2, rscratch2, rscratch3,LSL #8
2625 AND rscratch3, rscratch9, rscratch, LSR #12
2626 ADDHI rscratch3, rscratch3, #0x00010000 @ then (W3++)
2628 AND rscratch4, rscratch9, reg_a, LSR #12
2629 SUB rscratch3, rscratch4, rscratch3 @ R4=A4-W4
2630 CMP rscratch3, #0x00090000 @ if R4 > 9
2631 ADDHI rscratch3, rscratch3, #0x000A0000 @ then R4 += 10
2632 BICHI rstatus, rstatus, #MASK_CARRY @ then ClearCarry
2633 ORRLS rstatus, rstatus, #MASK_CARRY @ else SetCarry
2635 AND rscratch3,rscratch3,#0x000F0000
2636 ORR rscratch2,rscratch2,rscratch3,LSL #12
2638 LDMFD R13!,{rscratch9}
2640 AND reg_a,reg_a,#0x80000000
2641 @ (register.A.W ^ Work8)
2642 EORS rscratch3, reg_a, rscratch
2643 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2645 @ (register.A.W ^ Ans8)
2646 EORS rscratch3, reg_a, rscratch2
2648 TSTNE rscratch3,#0x80000000
2649 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2650 ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one
2652 MOVS reg_a, rscratch2
2657 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2658 SBCS reg_a, reg_a, rscratch, LSL #16
2660 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2661 BICVC rstatus, rstatus, #MASK_OVERFLOW
2662 MOV reg_a, reg_a, LSR #16
2665 MOVS reg_a, reg_a, LSL #16
2672 TST rstatus, #MASK_DECIMAL
2675 STMFD R13!,{rscratch}
2676 MOV rscratch4,#0x0F000000
2677 @ rscratch2=xxW1xxxxxxxxxxxx
2678 AND rscratch2, rscratch, rscratch4
2679 @ rscratch=xxW2xxxxxxxxxxxx
2680 AND rscratch, rscratch4, rscratch, LSR #4
2681 @ rscratch3=xxA2xxxxxxxxxxxx
2682 AND rscratch3, rscratch4, reg_a, LSR #4
2683 @ rscratch4=xxA1xxxxxxxxxxxx
2684 AND rscratch4,reg_a,rscratch4
2686 TST rstatus, #MASK_CARRY
2687 ADDEQ rscratch2, rscratch2, #0x01000000
2688 SUB rscratch2,rscratch4,rscratch2
2690 CMP rscratch2, #0x09000000
2692 ADDHI rscratch2, rscratch2, #0x0A000000
2694 ADDHI rscratch, rscratch, #0x01000000
2696 SUB rscratch3, rscratch3, rscratch
2698 CMP rscratch3, #0x09000000
2700 ADDHI rscratch3, rscratch3, #0x0A000000
2702 BICHI rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2704 ORRLS rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero
2705 @ gather rscratch3 and rscratch2 into ans8
2706 AND rscratch3,rscratch3,#0x0F000000
2707 AND rscratch2,rscratch2,#0x0F000000
2708 @ rscratch3 : 0R2000000
2709 @ rscratch2 : 0R1000000
2711 ORR rscratch2, rscratch2, rscratch3, LSL #4
2712 LDMFD R13!,{rscratch}
2714 AND reg_a,reg_a,#0x80000000
2715 @ (register.AL ^ Work8)
2716 EORS rscratch3, reg_a, rscratch
2717 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2719 @ (register.AL ^ Ans8)
2720 EORS rscratch3, reg_a, rscratch2
2722 TSTNE rscratch3,#0x80000000
2723 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2724 ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one
2726 MOVS reg_a, rscratch2
2731 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2732 SBCS reg_a, reg_a, rscratch, LSL #24
2734 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2735 BICVC rstatus, rstatus, #MASK_OVERFLOW
2739 ANDS reg_a, reg_a, #0xFF000000
2769 S9xGetWordRegNS rscratch2
2770 TST reg_a, rscratch2
2771 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2772 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2773 ORR rscratch2, reg_a, rscratch2
2774 S9xSetWord rscratch2
2778 S9xGetByteRegNS rscratch2
2779 TST reg_a, rscratch2
2780 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2781 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2782 ORR rscratch2, reg_a, rscratch2
2783 S9xSetByte rscratch2
2787 S9xGetWordRegNS rscratch2
2788 TST reg_a, rscratch2
2789 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2790 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2791 MVN rscratch3, reg_a
2792 AND rscratch2, rscratch3, rscratch2
2793 S9xSetWord rscratch2
2797 S9xGetByteRegNS rscratch2
2798 TST reg_a, rscratch2
2799 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2800 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2801 MVN rscratch3, reg_a
2802 AND rscratch2, rscratch3, rscratch2
2803 S9xSetByte rscratch2
2806 /**************************************************************************/
2809 /**************************************************************************/
2811 .macro Op09M0 /*ORA*/
2812 LDRB rscratch2, [rpc,#1]
2813 LDRB rscratch, [rpc], #2
2814 ORR rscratch2,rscratch,rscratch2,LSL #8
2815 ORRS reg_a,reg_a,rscratch2,LSL #16
2819 .macro Op09M1 /*ORA*/
2820 LDRB rscratch, [rpc], #1
2821 ORRS reg_a,reg_a,rscratch,LSL #24
2825 /***********************************************************************/
2829 TST rstatus, #MASK_CARRY
2831 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
2839 TST rstatus, #MASK_CARRY
2841 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
2849 TST rstatus, #MASK_ZERO
2851 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
2859 TST rstatus, #MASK_ZERO
2861 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
2869 TST rstatus, #MASK_NEG
2871 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
2879 TST rstatus, #MASK_NEG @ neg, z!=0, NE
2881 ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase
2889 TST rstatus, #MASK_OVERFLOW @ neg, z!=0, NE
2891 ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase
2899 TST rstatus, #MASK_OVERFLOW @ neg, z!=0, NE
2901 ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase
2908 ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase
2913 /*******************************************************************************************/
2914 /************************************************************/
2915 /* SetFlag Instructions ********************************************************************** */
2917 ORR rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2930 /****************************************************************************************/
2931 /* ClearFlag Instructions ******************************************************************** */
2933 BIC rstatus, rstatus, #MASK_CARRY
2946 BIC rstatus, rstatus, #MASK_OVERFLOW
2950 /******************************************************************************************/
2951 /* DEX/DEY *********************************************************************************** */
2953 .macro OpCAX1 /*DEX*/
2955 SUBS reg_x, reg_x, #0x01000000
2956 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2960 .macro OpCAX0 /*DEX*/
2962 SUBS reg_x, reg_x, #0x00010000
2963 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2967 .macro Op88X1 /*DEY*/
2969 SUBS reg_y, reg_y, #0x01000000
2970 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2974 .macro Op88X0 /*DEY*/
2976 SUBS reg_y, reg_y, #0x00010000
2977 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2982 /******************************************************************************************/
2983 /* INX/INY *********************************************************************************** */
2986 ADDS reg_x, reg_x, #0x01000000
2987 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2993 ADDS reg_x, reg_x, #0x00010000
2994 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3000 ADDS reg_y, reg_y, #0x01000000
3001 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3007 ADDS reg_y, reg_y, #0x00010000
3008 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3013 /**********************************************************************************************/
3015 /* NOP *************************************************************************************** */
3020 /**************************************************************************/
3021 /* PUSH Instructions **************************************************** */
3043 AND rscratch2, reg_d_bank, #0xFF
3075 /**************************************************************************/
3076 /* PULL Instructions **************************************************** */
3088 BIC reg_d_bank,reg_d_bank, #0xFF
3090 ORR reg_d_bank,reg_d_bank,rscratch, LSR #24
3097 ORR reg_d,rscratch,reg_d
3101 .macro Op28X1M1 /*PLP*/
3102 @ INDEX set, MEMORY set
3103 BIC rstatus,rstatus,#0xFF000000
3105 ORR rstatus,rscratch,rstatus
3106 TST rstatus, #MASK_INDEX
3107 @ INDEX clear & was set : 8->16
3108 MOVEQ reg_x,reg_x,LSR #8
3109 MOVEQ reg_y,reg_y,LSR #8
3110 TST rstatus, #MASK_MEM
3111 @ MEMORY cleared & was set : 8->16
3112 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
3113 MOVEQ reg_a,reg_a,LSR #8
3114 ORREQ reg_a,reg_a,rscratch, LSL #24
3118 .macro Op28X0M1 /*PLP*/
3119 @ INDEX cleared, MEMORY set
3120 BIC rstatus,rstatus,#0xFF000000
3122 ORR rstatus,rscratch,rstatus
3123 TST rstatus, #MASK_INDEX
3124 @ INDEX set & was cleared : 16->8
3125 MOVNE reg_x,reg_x,LSL #8
3126 MOVNE reg_y,reg_y,LSL #8
3127 TST rstatus, #MASK_MEM
3128 @ MEMORY cleared & was set : 8->16
3129 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
3130 MOVEQ reg_a,reg_a,LSR #8
3131 ORREQ reg_a,reg_a,rscratch, LSL #24
3135 .macro Op28X1M0 /*PLP*/
3136 @ INDEX set, MEMORY set
3137 BIC rstatus,rstatus,#0xFF000000
3139 ORR rstatus,rscratch,rstatus
3140 TST rstatus, #MASK_INDEX
3141 @ INDEX clear & was set : 8->16
3142 MOVEQ reg_x,reg_x,LSR #8
3143 MOVEQ reg_y,reg_y,LSR #8
3144 TST rstatus, #MASK_MEM
3145 @ MEMORY set & was cleared : 16->8
3146 MOVNE rscratch,reg_a,LSR #24
3147 MOVNE reg_a,reg_a,LSL #8
3148 STRNEB rscratch,[reg_cpu_var,#RAH_ofs]
3152 .macro Op28X0M0 /*PLP*/
3153 @ INDEX set, MEMORY set
3154 BIC rstatus,rstatus,#0xFF000000
3156 ORR rstatus,rscratch,rstatus
3157 TST rstatus, #MASK_INDEX
3158 @ INDEX set & was cleared : 16->8
3159 MOVNE reg_x,reg_x,LSL #8
3160 MOVNE reg_y,reg_y,LSL #8
3161 TST rstatus, #MASK_MEM
3162 @ MEMORY set & was cleared : 16->8
3163 MOVNE rscratch,reg_a,LSR #24
3164 MOVNE reg_a,reg_a,LSL #8
3165 STRNEB rscratch,[reg_cpu_var,#RAH_ofs]
3190 /**********************************************************************************************/
3191 /* Transfer Instructions ********************************************************************* */
3192 .macro OpAAX1M1 /*TAX8*/
3197 .macro OpAAX0M1 /*TAX16*/
3198 LDRB reg_x, [reg_cpu_var,#RAH_ofs]
3199 MOV reg_x, reg_x,LSL #24
3200 ORRS reg_x, reg_x,reg_a, LSR #8
3204 .macro OpAAX1M0 /*TAX8*/
3205 MOVS reg_x, reg_a, LSL #8
3209 .macro OpAAX0M0 /*TAX16*/
3214 .macro OpA8X1M1 /*TAY8*/
3219 .macro OpA8X0M1 /*TAY16*/
3220 LDRB reg_y, [reg_cpu_var,#RAH_ofs]
3221 MOV reg_y, reg_y,LSL #24
3222 ORRS reg_y, reg_y,reg_a, LSR #8
3226 .macro OpA8X1M0 /*TAY8*/
3227 MOVS reg_y, reg_a, LSL #8
3231 .macro OpA8X0M0 /*TAY16*/
3237 LDRB rscratch, [reg_cpu_var,#RAH_ofs]
3238 MOV reg_d,reg_d,LSL #16
3239 MOV rscratch,rscratch,LSL #24
3240 ORRS rscratch,rscratch,reg_a, LSR #8
3242 ORR reg_d,rscratch,reg_d,LSR #16
3246 MOV reg_d,reg_d,LSL #16
3249 ORR reg_d,reg_a,reg_d,LSR #16
3253 TST rstatus, #MASK_EMUL
3254 MOVNE reg_s, reg_a, LSR #24
3255 ORRNE reg_s, reg_s, #0x100
3256 LDREQB reg_s, [reg_cpu_var,#RAH_ofs]
3257 ORREQ reg_s, reg_s, reg_a
3258 MOVEQ reg_s, reg_s, ROR #24
3262 MOV reg_s, reg_a, LSR #16
3266 MOVS reg_a, reg_d, ASR #16
3268 MOV rscratch,reg_a,LSR #8
3269 MOV reg_a,reg_a, LSL #24
3270 STRB rscratch, [reg_cpu_var,#RAH_ofs]
3274 MOVS reg_a, reg_d, ASR #16
3276 MOV reg_a,reg_a, LSL #16
3280 MOV rscratch,reg_s, LSR #8
3281 MOVS reg_a, reg_s, LSL #16
3282 STRB rscratch, [reg_cpu_var,#RAH_ofs]
3284 MOV reg_a,reg_a, LSL #8
3288 MOVS reg_a, reg_s, LSL #16
3293 MOVS reg_x, reg_s, LSL #24
3298 MOVS reg_x, reg_s, LSL #16
3308 MOVS reg_a, reg_x, LSL #8
3313 MOVS reg_a, reg_x, LSR #8
3323 MOV reg_s, reg_x, LSR #24
3324 TST rstatus, #MASK_EMUL
3325 ORRNE reg_s, reg_s, #0x100
3329 MOV reg_s, reg_x, LSR #16
3348 MOVS reg_a, reg_y, LSL #8
3353 MOVS reg_a, reg_y, LSR #8
3373 /**********************************************************************************************/
3374 /* XCE *************************************************************************************** */
3377 TST rstatus,#MASK_CARRY
3380 TST rstatus,#MASK_EMUL
3383 BIC rstatus,rstatus,#(MASK_CARRY)
3384 TST rstatus,#MASK_INDEX
3385 @ X & Y were 16bits before
3386 MOVEQ reg_x,reg_x,LSL #8
3387 MOVEQ reg_y,reg_y,LSL #8
3388 TST rstatus,#MASK_MEM
3389 @ A was 16bits before
3391 MOVEQ rscratch,reg_a,LSR #24
3392 STREQB rscratch,[reg_cpu_var,#RAH_ofs]
3393 MOVEQ reg_a,reg_a,LSL #8
3394 ORR rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX)
3395 AND reg_s,reg_s,#0xFF
3396 ORR reg_s,reg_s,#0x100
3400 TST rstatus,#MASK_INDEX
3401 @ X & Y were 16bits before
3402 MOVEQ reg_x,reg_x,LSL #8
3403 MOVEQ reg_y,reg_y,LSL #8
3404 TST rstatus,#MASK_MEM
3405 @ A was 16bits before
3407 MOVEQ rscratch,reg_a,LSR #24
3408 STREQB rscratch,[reg_cpu_var,#RAH_ofs]
3409 MOVEQ reg_a,reg_a,LSL #8
3410 ORR rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX)
3411 AND reg_s,reg_s,#0xFF
3412 ORR reg_s,reg_s,#0x100
3416 TST rstatus,#MASK_EMUL
3418 @ EMUL was set : X,Y & A were 8bits
3419 @ Now have to check MEMORY & INDEX for potential conversions to 16bits
3420 TST rstatus,#MASK_INDEX
3421 @ X & Y are now 16bits
3422 MOVEQ reg_x,reg_x,LSR #8
3423 MOVEQ reg_y,reg_y,LSR #8
3424 TST rstatus,#MASK_MEM
3426 MOVEQ reg_a,reg_a,LSR #8
3428 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
3429 ORREQ reg_a,reg_a,rscratch,LSL #24
3431 BIC rstatus,rstatus,#(MASK_EMUL)
3432 ORR rstatus,rstatus,#(MASK_CARRY)
3438 /*******************************************************************************/
3439 /* BRK *************************************************************************/
3442 STRB rscratch,[reg_cpu_var,#BRKTriggered_ofs]
3444 TST rstatus, #MASK_EMUL
3445 @ EQ is flag to zero (!CheckEmu)
3448 SUB rscratch, rpc, regpcbase
3449 ADD rscratch2, rscratch, #1
3455 BIC reg_p_bank, reg_p_bank, #0xFF
3457 ORR rscratch, rscratch, #0xFF00
3463 SUB rscratch2, rpc, regpcbase
3469 BIC reg_p_bank,reg_p_bank, #0xFF
3471 ORR rscratch, rscratch, #0xFF00
3479 /**********************************************************************************************/
3480 /* BRL ************************************************************************************** */
3483 ORR rscratch, rscratch, reg_p_bank, LSL #16
3486 /**********************************************************************************************/
3487 /* IRQ *************************************************************************************** */
3488 @ void S9xOpcode_IRQ (void)
3489 .macro S9xOpcode_IRQ @ IRQ
3490 TST rstatus, #MASK_EMUL
3491 @ EQ is flag to zero (!CheckEmu)
3494 SUB rscratch2, rpc, regpcbase
3500 BIC reg_p_bank, reg_p_bank,#0xFF
3502 ORR rscratch, rscratch, #0xFF00
3508 SUB rscratch2, rpc, regpcbase
3514 BIC reg_p_bank,reg_p_bank, #0xFF
3516 ORR rscratch, rscratch, #0xFF00
3524 void asm_S9xOpcode_IRQ(void)
3526 if (!CheckEmulation())
3528 PushB (Registers.PB);
3529 PushW (CPU.PC - CPU.PCBase);
3530 PushB (Registers.PL);
3535 S9xSetPCBase (S9xGetWord (0xFFEE));
3536 CPU.Cycles += TWO_CYCLES;
3540 PushW (CPU.PC - CPU.PCBase);
3541 PushB (Registers.PL);
3546 S9xSetPCBase (S9xGetWord (0xFFFE));
3547 CPU.Cycles += ONE_CYCLE;
3552 /**********************************************************************************************/
3553 /* NMI *************************************************************************************** */
3554 @ void S9xOpcode_NMI (void)
3555 .macro S9xOpcode_NMI @ NMI
3556 TST rstatus, #MASK_EMUL
3557 @ EQ is flag to zero (!CheckEmu)
3560 SUB rscratch2, rpc, regpcbase
3566 BIC reg_p_bank, reg_p_bank,#0xFF
3568 ORR rscratch, rscratch, #0xFF00
3574 SUB rscratch2, rpc, regpcbase
3580 BIC reg_p_bank,reg_p_bank, #0xFF
3582 ORR rscratch, rscratch, #0xFF00
3589 void asm_S9xOpcode_NMI(void)
3591 if (!CheckEmulation())
3593 PushB (Registers.PB);
3594 PushW (CPU.PC - CPU.PCBase);
3595 PushB (Registers.PL);
3600 S9xSetPCBase (S9xGetWord (0xFFEA));
3601 CPU.Cycles += TWO_CYCLES;
3605 PushW (CPU.PC - CPU.PCBase);
3606 PushB (Registers.PL);
3611 S9xSetPCBase (S9xGetWord (0xFFFA));
3612 CPU.Cycles += ONE_CYCLE;
3617 /**********************************************************************************************/
3618 /* COP *************************************************************************************** */
3620 TST rstatus, #MASK_EMUL
3621 @ EQ is flag to zero (!CheckEmu)
3624 SUB rscratch, rpc, regpcbase
3625 ADD rscratch2, rscratch, #1
3631 BIC reg_p_bank, reg_p_bank,#0xFF
3633 ORR rscratch, rscratch, #0xFF00
3639 SUB rscratch2, rpc, regpcbase
3645 BIC reg_p_bank,reg_p_bank, #0xFF
3647 ORR rscratch, rscratch, #0xFF00
3654 /**********************************************************************************************/
3655 /* JML *************************************************************************************** */
3657 AbsoluteIndirectLong
3658 BIC reg_p_bank,reg_p_bank,#0xFF
3659 ORR reg_p_bank,reg_p_bank, rscratch, LSR #16
3665 BIC reg_p_bank,reg_p_bank,#0xFF
3666 ORR reg_p_bank,reg_p_bank, rscratch, LSR #16
3670 /**********************************************************************************************/
3671 /* JMP *************************************************************************************** */
3674 BIC rscratch, rscratch, #0xFF0000
3675 ORR rscratch, rscratch, reg_p_bank, LSL #16
3681 BIC rscratch, rscratch, #0xFF0000
3682 ORR rscratch, rscratch, reg_p_bank, LSL #16
3686 ADD rscratch, rscratch, reg_p_bank, LSL #16
3691 /**********************************************************************************************/
3692 /* JSL/RTL *********************************************************************************** */
3695 SUB rscratch, rpc, regpcbase
3696 @ SUB rscratch2, rscratch2, #1
3697 ADD rscratch2, rscratch, #2
3700 BIC reg_p_bank,reg_p_bank,#0xFF
3701 ORR reg_p_bank, reg_p_bank, rscratch, LSR #16
3706 BIC reg_p_bank,reg_p_bank,#0xFF
3708 ORR reg_p_bank, reg_p_bank, rscratch
3709 ADD rscratch, rpc, #1
3710 BIC rscratch, rscratch,#0xFF0000
3711 ORR rscratch, rscratch, reg_p_bank, LSL #16
3715 /**********************************************************************************************/
3716 /* JSR/RTS *********************************************************************************** */
3718 SUB rscratch, rpc, regpcbase
3719 @ SUB rscratch2, rscratch2, #1
3720 ADD rscratch2, rscratch, #1
3723 BIC rscratch, rscratch, #0xFF0000
3724 ORR rscratch, rscratch, reg_p_bank, LSL #16
3729 SUB rscratch, rpc, regpcbase
3730 @ SUB rscratch2, rscratch2, #1
3731 ADD rscratch2, rscratch, #1
3733 AbsoluteIndexedIndirectX0
3734 ORR rscratch, rscratch, reg_p_bank, LSL #16
3739 SUB rscratch, rpc, regpcbase
3740 @ SUB rscratch2, rscratch2, #1
3741 ADD rscratch2, rscratch, #1
3743 AbsoluteIndexedIndirectX1
3744 ORR rscratch, rscratch, reg_p_bank, LSL #16
3750 ADD rscratch, rpc, #1
3751 BIC rscratch, rscratch,#0x10000
3752 ORR rscratch, rscratch, reg_p_bank, LSL #16
3757 /**********************************************************************************************/
3758 /* MVN/MVP *********************************************************************************** */
3760 @ Save RegStatus = reg_d_bank >> 24
3761 MOV rscratch, reg_d_bank, LSR #16
3762 LDRB reg_d_bank , [rpc], #1
3763 LDRB rscratch2 , [rpc], #1
3764 @ Restore RegStatus = reg_d_bank >> 24
3765 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3766 MOV rscratch , reg_x, LSR #24
3767 ORR rscratch , rscratch, rscratch2, LSL #16
3769 MOV rscratch2, rscratch
3770 MOV rscratch , reg_y, LSR #24
3771 ORR rscratch , rscratch, reg_d_bank, LSL #16
3772 S9xSetByteLow rscratch2
3774 LDRB rscratch,[reg_cpu_var,#RAH_ofs]
3775 MOV reg_a,reg_a,LSR #8
3776 ORR reg_a,reg_a,rscratch, LSL #24
3777 ADD reg_x, reg_x, #0x01000000
3778 SUB reg_a, reg_a, #0x00010000
3779 ADD reg_y, reg_y, #0x01000000
3780 CMP reg_a, #0xFFFF0000
3783 MOV rscratch, reg_a, LSR #24
3784 MOV reg_a,reg_a,LSL #8
3785 STRB rscratch,[reg_cpu_var,#RAH_ofs]
3789 @ Save RegStatus = reg_d_bank >> 24
3790 MOV rscratch, reg_d_bank, LSR #16
3791 LDRB reg_d_bank , [rpc], #1
3792 LDRB rscratch2 , [rpc], #1
3793 @ Restore RegStatus = reg_d_bank >> 24
3794 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3795 MOV rscratch , reg_x, LSR #24
3796 ORR rscratch , rscratch, rscratch2, LSL #16
3798 MOV rscratch2, rscratch
3799 MOV rscratch , reg_y, LSR #24
3800 ORR rscratch , rscratch, reg_d_bank, LSL #16
3801 S9xSetByteLow rscratch2
3802 ADD reg_x, reg_x, #0x01000000
3803 SUB reg_a, reg_a, #0x00010000
3804 ADD reg_y, reg_y, #0x01000000
3805 CMP reg_a, #0xFFFF0000
3810 @ Save RegStatus = reg_d_bank >> 24
3811 MOV rscratch, reg_d_bank, LSR #16
3812 LDRB reg_d_bank , [rpc], #1
3813 LDRB rscratch2 , [rpc], #1
3814 @ Restore RegStatus = reg_d_bank >> 24
3815 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3816 MOV rscratch , reg_x, LSR #16
3817 ORR rscratch , rscratch, rscratch2, LSL #16
3819 MOV rscratch2, rscratch
3820 MOV rscratch , reg_y, LSR #16
3821 ORR rscratch , rscratch, reg_d_bank, LSL #16
3822 S9xSetByteLow rscratch2
3824 LDRB rscratch,[reg_cpu_var,#RAH_ofs]
3825 MOV reg_a,reg_a,LSR #8
3826 ORR reg_a,reg_a,rscratch, LSL #24
3827 ADD reg_x, reg_x, #0x00010000
3828 SUB reg_a, reg_a, #0x00010000
3829 ADD reg_y, reg_y, #0x00010000
3830 CMP reg_a, #0xFFFF0000
3833 MOV rscratch, reg_a, LSR #24
3834 MOV reg_a,reg_a,LSL #8
3835 STRB rscratch,[reg_cpu_var,#RAH_ofs]
3839 @ Save RegStatus = reg_d_bank >> 24
3840 MOV rscratch, reg_d_bank, LSR #16
3841 LDRB reg_d_bank , [rpc], #1
3842 LDRB rscratch2 , [rpc], #1
3843 @ Restore RegStatus = reg_d_bank >> 24
3844 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3845 MOV rscratch , reg_x, LSR #16
3846 ORR rscratch , rscratch, rscratch2, LSL #16
3848 MOV rscratch2, rscratch
3849 MOV rscratch , reg_y, LSR #16
3850 ORR rscratch , rscratch, reg_d_bank, LSL #16
3851 S9xSetByteLow rscratch2
3852 ADD reg_x, reg_x, #0x00010000
3853 SUB reg_a, reg_a, #0x00010000
3854 ADD reg_y, reg_y, #0x00010000
3855 CMP reg_a, #0xFFFF0000
3861 @ Save RegStatus = reg_d_bank >> 24
3862 MOV rscratch, reg_d_bank, LSR #16
3863 LDRB reg_d_bank , [rpc], #1
3864 LDRB rscratch2 , [rpc], #1
3865 @ Restore RegStatus = reg_d_bank >> 24
3866 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3867 MOV rscratch , reg_x, LSR #24
3868 ORR rscratch , rscratch, rscratch2, LSL #16
3870 MOV rscratch2, rscratch
3871 MOV rscratch , reg_y, LSR #24
3872 ORR rscratch , rscratch, reg_d_bank, LSL #16
3873 S9xSetByteLow rscratch2
3875 LDRB rscratch,[reg_cpu_var,#RAH_ofs]
3876 MOV reg_a,reg_a,LSR #8
3877 ORR reg_a,reg_a,rscratch, LSL #24
3878 SUB reg_x, reg_x, #0x01000000
3879 SUB reg_a, reg_a, #0x00010000
3880 SUB reg_y, reg_y, #0x01000000
3881 CMP reg_a, #0xFFFF0000
3884 MOV rscratch, reg_a, LSR #24
3885 MOV reg_a,reg_a,LSL #8
3886 STRB rscratch,[reg_cpu_var,#RAH_ofs]
3890 @ Save RegStatus = reg_d_bank >> 24
3891 MOV rscratch, reg_d_bank, LSR #16
3892 LDRB reg_d_bank , [rpc], #1
3893 LDRB rscratch2 , [rpc], #1
3894 @ Restore RegStatus = reg_d_bank >> 24
3895 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3896 MOV rscratch , reg_x, LSR #24
3897 ORR rscratch , rscratch, rscratch2, LSL #16
3899 MOV rscratch2, rscratch
3900 MOV rscratch , reg_y, LSR #24
3901 ORR rscratch , rscratch, reg_d_bank, LSL #16
3902 S9xSetByteLow rscratch2
3903 SUB reg_x, reg_x, #0x01000000
3904 SUB reg_a, reg_a, #0x00010000
3905 SUB reg_y, reg_y, #0x01000000
3906 CMP reg_a, #0xFFFF0000
3911 @ Save RegStatus = reg_d_bank >> 24
3912 MOV rscratch, reg_d_bank, LSR #16
3913 LDRB reg_d_bank , [rpc], #1
3914 LDRB rscratch2 , [rpc], #1
3915 @ Restore RegStatus = reg_d_bank >> 24
3916 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3917 MOV rscratch , reg_x, LSR #16
3918 ORR rscratch , rscratch, rscratch2, LSL #16
3920 MOV rscratch2, rscratch
3921 MOV rscratch , reg_y, LSR #16
3922 ORR rscratch , rscratch, reg_d_bank, LSL #16
3923 S9xSetByteLow rscratch2
3925 LDRB rscratch,[reg_cpu_var,#RAH_ofs]
3926 MOV reg_a,reg_a,LSR #8
3927 ORR reg_a,reg_a,rscratch, LSL #24
3928 SUB reg_x, reg_x, #0x00010000
3929 SUB reg_a, reg_a, #0x00010000
3930 SUB reg_y, reg_y, #0x00010000
3931 CMP reg_a, #0xFFFF0000
3934 MOV rscratch, reg_a, LSR #24
3935 MOV reg_a,reg_a,LSL #8
3936 STRB rscratch,[reg_cpu_var,#RAH_ofs]
3940 @ Save RegStatus = reg_d_bank >> 24
3941 MOV rscratch, reg_d_bank, LSR #16
3942 LDRB reg_d_bank , [rpc], #1
3943 LDRB rscratch2 , [rpc], #1
3944 @ Restore RegStatus = reg_d_bank >> 24
3945 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3946 MOV rscratch , reg_x, LSR #16
3947 ORR rscratch , rscratch, rscratch2, LSL #16
3949 MOV rscratch2, rscratch
3950 MOV rscratch , reg_y, LSR #16
3951 ORR rscratch , rscratch, reg_d_bank, LSL #16
3952 S9xSetByteLow rscratch2
3953 SUB reg_x, reg_x, #0x00010000
3954 SUB reg_a, reg_a, #0x00010000
3955 SUB reg_y, reg_y, #0x00010000
3956 CMP reg_a, #0xFFFF0000
3961 /**********************************************************************************************/
3962 /* REP/SEP *********************************************************************************** */
3964 @ status&=~(*rpc++);
3965 @ so possible changes are :
3966 @ INDEX = 1 -> 0 : X,Y 8bits -> 16bits
3967 @ MEM = 1 -> 0 : A 8bits -> 16bits
3968 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
3969 MOV rscratch3, rstatus
3970 LDRB rscratch, [rpc], #1
3971 MVN rscratch, rscratch
3972 AND rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER)
3973 TST rstatus,#MASK_EMUL
3975 @ emulation mode on : no changes since it was on before opcode
3976 @ just be sure to reset MEM & INDEX accordingly
3977 ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
3980 @ NOT in Emulation mode, check INDEX & MEMORY bits
3982 TST rscratch3,#MASK_INDEX
3984 @ X & Y were 8bit before
3985 TST rstatus,#MASK_INDEX
3987 @ X & Y are now 16bits
3988 MOV reg_x,reg_x,LSR #8
3989 MOV reg_y,reg_y,LSR #8
3990 1113: @ X & Y still in 16bits
3992 TST rscratch3,#MASK_MEM
3995 TST rstatus,#MASK_MEM
3998 MOV reg_a,reg_a,LSR #8
4000 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
4001 ORREQ reg_a,reg_a,rscratch,LSL #24
4008 @ so possible changes are :
4009 @ INDEX = 0 -> 1 : X,Y 16bits -> 8bits
4010 @ MEM = 0 -> 1 : A 16bits -> 8bits
4011 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
4012 MOV rscratch3, rstatus
4013 LDRB rscratch, [rpc], #1
4014 ORR rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER
4015 TST rstatus,#MASK_EMUL
4017 @ emulation mode on : no changes sinc eit was on before opcode
4018 @ just be sure to have mem & index set accordingly
4019 ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
4022 @ NOT in Emulation mode, check INDEX & MEMORY bits
4024 TST rscratch3,#MASK_INDEX
4026 @ X & Y were 16bit before
4027 TST rstatus,#MASK_INDEX
4029 @ X & Y are now 8bits
4030 MOV reg_x,reg_x,LSL #8
4031 MOV reg_y,reg_y,LSL #8
4032 10113: @ X & Y still in 16bits
4034 TST rscratch3,#MASK_MEM
4036 @ A was 16bit before
4037 TST rstatus,#MASK_MEM
4041 MOV rscratch,reg_a,LSR #24
4042 MOV reg_a,reg_a,LSL #8
4043 STRB rscratch,[reg_cpu_var,#RAH_ofs]
4049 /**********************************************************************************************/
4050 /* XBA *************************************************************************************** */
4053 ADD rscratch,reg_cpu_var,#RAH_ofs
4054 MOV reg_a,reg_a, LSR #24
4055 SWPB reg_a,reg_a,[rscratch]
4056 MOVS reg_a,reg_a, LSL #24
4062 MOV rscratch, reg_a, ROR #24 @ ll0000hh
4063 ORR rscratch, rscratch, reg_a, LSR #8@ ll0000hh + 00hhll00 -> llhhllhh
4064 MOV reg_a, rscratch, LSL #16@ llhhllhh -> llhh0000
4065 MOVS rscratch,rscratch,LSL #24 @ to set Z & N flags with AL
4071 /**********************************************************************************************/
4072 /* RTI *************************************************************************************** */
4074 @ INDEX set, MEMORY set
4075 BIC rstatus,rstatus,#0xFF000000
4077 ORR rstatus,rscratch,rstatus
4079 TST rstatus, #MASK_EMUL
4080 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4083 BIC reg_p_bank,reg_p_bank,#0xFF
4084 ORR reg_p_bank,reg_p_bank,rscratch
4086 ADD rscratch, rpc, reg_p_bank, LSL #16
4088 TST rstatus, #MASK_INDEX
4089 @ INDEX cleared & was set : 8->16
4090 MOVEQ reg_x,reg_x,LSR #8
4091 MOVEQ reg_y,reg_y,LSR #8
4092 TST rstatus, #MASK_MEM
4093 @ MEMORY cleared & was set : 8->16
4094 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
4095 MOVEQ reg_a,reg_a,LSR #8
4096 ORREQ reg_a,reg_a,rscratch, LSL #24
4101 @ INDEX cleared, MEMORY set
4102 BIC rstatus,rstatus,#0xFF000000
4104 ORR rstatus,rscratch,rstatus
4106 TST rstatus, #MASK_EMUL
4107 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4110 BIC reg_p_bank,reg_p_bank,#0xFF
4111 ORR reg_p_bank,reg_p_bank,rscratch
4113 ADD rscratch, rpc, reg_p_bank, LSL #16
4115 TST rstatus, #MASK_INDEX
4116 @ INDEX set & was cleared : 16->8
4117 MOVNE reg_x,reg_x,LSL #8
4118 MOVNE reg_y,reg_y,LSL #8
4119 TST rstatus, #MASK_MEM
4120 @ MEMORY cleared & was set : 8->16
4121 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
4122 MOVEQ reg_a,reg_a,LSR #8
4123 ORREQ reg_a,reg_a,rscratch, LSL #24
4128 @ INDEX set, MEMORY cleared
4129 BIC rstatus,rstatus,#0xFF000000
4131 ORR rstatus,rscratch,rstatus
4133 TST rstatus, #MASK_EMUL
4134 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4137 BIC reg_p_bank,reg_p_bank,#0xFF
4138 ORR reg_p_bank,reg_p_bank,rscratch
4140 ADD rscratch, rpc, reg_p_bank, LSL #16
4142 TST rstatus, #MASK_INDEX
4143 @ INDEX cleared & was set : 8->16
4144 MOVEQ reg_x,reg_x,LSR #8
4145 MOVEQ reg_y,reg_y,LSR #8
4146 TST rstatus, #MASK_MEM
4147 @ MEMORY set & was cleared : 16->8
4148 MOVNE rscratch,reg_a,LSR #24
4149 MOVNE reg_a,reg_a,LSL #8
4150 STRNEB rscratch,[reg_cpu_var,#RAH_ofs]
4155 @ INDEX cleared, MEMORY cleared
4156 BIC rstatus,rstatus,#0xFF000000
4158 ORR rstatus,rscratch,rstatus
4160 TST rstatus, #MASK_EMUL
4161 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4164 BIC reg_p_bank,reg_p_bank,#0xFF
4165 ORR reg_p_bank,reg_p_bank,rscratch
4167 ADD rscratch, rpc, reg_p_bank, LSL #16
4169 TST rstatus, #MASK_INDEX
4170 @ INDEX set & was cleared : 16->8
4171 MOVNE reg_x,reg_x,LSL #8
4172 MOVNE reg_y,reg_y,LSL #8
4173 TST rstatus, #MASK_MEM
4174 @ MEMORY set & was cleared : 16->8
4175 @ MEMORY set & was cleared : 16->8
4176 MOVNE rscratch,reg_a,LSR #24
4177 MOVNE reg_a,reg_a,LSL #8
4178 STRNEB rscratch,[reg_cpu_var,#RAH_ofs]
4184 /**********************************************************************************************/
4185 /* STP/WAI/DB ******************************************************************************** */
4188 LDRB rscratch,[reg_cpu_var,#IRQActive_ofs]
4189 MOVS rscratch,rscratch
4194 CPU.WaitingForInterrupt = TRUE;
4200 CPU.Cycles = CPU.NextEvent;
4202 STRB rscratch,[reg_cpu_var,#WaitingForInterrupt_ofs]
4203 LDR reg_cycles,[reg_cpu_var,#NextEvent_ofs]
4205 if (IAPU.APUExecuting)
4207 ICPU.CPUExecuting = FALSE;
4211 } while (APU.Cycles < CPU.NextEvent);
4212 ICPU.CPUExecuting = TRUE;
4215 LDRB rscratch,[reg_cpu_var,#APUExecuting_ofs]
4216 MOVS rscratch,rscratch
4224 @ CPU.Flags |= DEBUG_MODE_FLAG;
4226 .macro Op42 /*Reserved Snes9X: SNESAdvance SpeedHack */
4227 @ Explanation: this is a reserved opcode turned into special "idle"/hlt opcode.
4228 @ This means we should do an hblank now.
4230 CPU.Cycles = CPU.NextEvent;
4231 */ ldr reg_cycles, [reg_cpu_var,#NextEvent_ofs]
4232 @ Now execute the shadowed branch
4233 @ Equivalent to "asmRelative":
4235 ldrb rscratch, [rpc], #1
4236 and rscratch2, rscratch, #0xf0 @branch type
4237 orr rscratch, rscratch, #0xf0 @branch dest (always negative, so sign ext)
4238 sxtb rscratch, rscratch
4239 add rscratch, rscratch, rpc
4240 sub rscratch, rscratch, regpcbase
4241 uxth rscratch, rscratch
4242 @ TODO: Do something with rscratch2 before BranchCheck clobbers it.
4243 @ Currently hardcoded to BEQ
4245 TST rstatus, #MASK_ZERO
4247 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
4252 /**********************************************************************************************/
4253 /* AND ******************************************************************************** */
4255 LDRB rscratch , [rpc], #1
4256 ANDS reg_a , reg_a, rscratch, LSL #24
4261 LDRB rscratch2 , [rpc,#1]
4262 LDRB rscratch , [rpc], #2
4263 ORR rscratch, rscratch, rscratch2, LSL #8
4264 ANDS reg_a , reg_a, rscratch, LSL #16
4283 /**********************************************************************************************/
4284 /* EOR ******************************************************************************** */
4286 LDRB rscratch2 , [rpc, #1]
4287 LDRB rscratch , [rpc], #2
4288 ORR rscratch, rscratch, rscratch2,LSL #8
4289 EORS reg_a, reg_a, rscratch,LSL #16
4296 LDRB rscratch , [rpc], #1
4297 EORS reg_a, reg_a, rscratch,LSL #24
4303 /**********************************************************************************************/
4304 /* STA *************************************************************************************** */
4307 @ TST rstatus, #MASK_INDEX
4312 @ TST rstatus, #MASK_INDEX
4317 /**********************************************************************************************/
4318 /* BIT *************************************************************************************** */
4320 LDRB rscratch , [rpc], #1
4321 TST reg_a, rscratch, LSL #24
4326 LDRB rscratch2 , [rpc, #1]
4327 LDRB rscratch , [rpc], #2
4328 ORR rscratch, rscratch, rscratch2, LSL #8
4329 TST reg_a, rscratch, LSL #16
4339 /**********************************************************************************************/
4340 /* LDY *************************************************************************************** */
4342 LDRB rscratch , [rpc], #1
4343 MOVS reg_y, rscratch, LSL #24
4348 LDRB rscratch2 , [rpc, #1]
4349 LDRB rscratch , [rpc], #2
4350 ORR rscratch, rscratch, rscratch2, LSL #8
4351 MOVS reg_y, rscratch, LSL #16
4356 /**********************************************************************************************/
4357 /* LDX *************************************************************************************** */
4359 LDRB rscratch , [rpc], #1
4360 MOVS reg_x, rscratch, LSL #24
4365 LDRB rscratch2 , [rpc, #1]
4366 LDRB rscratch , [rpc], #2
4367 ORR rscratch, rscratch, rscratch2, LSL #8
4368 MOVS reg_x, rscratch, LSL #16
4373 /**********************************************************************************************/
4374 /* LDA *************************************************************************************** */
4376 LDRB rscratch , [rpc], #1
4377 MOVS reg_a, rscratch, LSL #24
4382 LDRB rscratch2 , [rpc, #1]
4383 LDRB rscratch , [rpc], #2
4384 ORR rscratch, rscratch, rscratch2, LSL #8
4385 MOVS reg_a, rscratch, LSL #16
4390 /**********************************************************************************************/
4391 /* CMY *************************************************************************************** */
4393 LDRB rscratch , [rpc], #1
4394 SUBS rscratch2 , reg_y , rscratch, LSL #24
4395 BICCC rstatus, rstatus, #MASK_CARRY
4396 ORRCS rstatus, rstatus, #MASK_CARRY
4401 LDRB rscratch2 , [rpc, #1]
4402 LDRB rscratch , [rpc], #2
4403 ORR rscratch, rscratch, rscratch2, LSL #8
4404 SUBS rscratch2 , reg_y, rscratch, LSL #16
4405 BICCC rstatus, rstatus, #MASK_CARRY
4406 ORRCS rstatus, rstatus, #MASK_CARRY
4415 /**********************************************************************************************/
4416 /* CMP *************************************************************************************** */
4418 LDRB rscratch , [rpc], #1
4419 SUBS rscratch2 , reg_a , rscratch, LSL #24
4420 BICCC rstatus, rstatus, #MASK_CARRY
4421 ORRCS rstatus, rstatus, #MASK_CARRY
4426 LDRB rscratch2 , [rpc,#1]
4427 LDRB rscratch , [rpc], #2
4428 ORR rscratch, rscratch, rscratch2, LSL #8
4429 SUBS rscratch2 , reg_a, rscratch, LSL #16
4430 BICCC rstatus, rstatus, #MASK_CARRY
4431 ORRCS rstatus, rstatus, #MASK_CARRY
4436 /**********************************************************************************************/
4437 /* CMX *************************************************************************************** */
4439 LDRB rscratch , [rpc], #1
4440 SUBS rscratch2 , reg_x , rscratch, LSL #24
4441 BICCC rstatus, rstatus, #MASK_CARRY
4442 ORRCS rstatus, rstatus, #MASK_CARRY
4447 LDRB rscratch2 , [rpc,#1]
4448 LDRB rscratch , [rpc], #2
4449 ORR rscratch, rscratch, rscratch2, LSL #8
4450 SUBS rscratch2 , reg_x, rscratch, LSL #16
4451 BICCC rstatus, rstatus, #MASK_CARRY
4452 ORRCS rstatus, rstatus, #MASK_CARRY
4458 /****************************************************************
4460 ****************************************************************/
4462 .type asmMainLoop, function
4464 @ void asmMainLoop(asm_cpu_var_t *asmcpuPtr);
4467 STMFD R13!,{R4-R11, LR}
4468 @ init pointer to CPUvar structure
4472 @ get cpu mode from flag and init jump table
4480 LDR rscratch,[reg_cpu_var,#Flags_ofs]
4481 MOVS rscratch,rscratch
4482 BNE CPUFlags_set @ If flags => check for irq/nmi/scan_keys...
4484 EXEC_OP @ Execute next opcode
4486 CPUFlags_set: @ Check flags (!=0)
4487 TST rscratch,#NMI_FLAG @ Check NMI
4488 BEQ CPUFlagsNMI_FLAG_cleared
4489 LDR rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4490 SUBS rscratch2,rscratch2,#1
4491 STR rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4492 BNE CPUFlagsNMI_FLAG_cleared
4493 BIC rscratch,rscratch,#NMI_FLAG
4494 STR rscratch,[reg_cpu_var,#Flags_ofs]
4495 LDRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4496 MOVS rscratch2,rscratch2
4497 BEQ NotCPUaitingForInterruptNMI
4500 STRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4501 NotCPUaitingForInterruptNMI:
4503 LDR rscratch,[reg_cpu_var,#Flags_ofs]
4504 CPUFlagsNMI_FLAG_cleared:
4505 TST rscratch,#IRQ_PENDING_FLAG @ Check IRQ_PENDING_FLAG
4506 BEQ CPUFlagsIRQ_PENDING_FLAG_cleared
4507 LDR rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4508 MOVS rscratch2,rscratch2
4509 BNE CPUIRQCycleCount_NotZero
4510 LDRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4511 MOVS rscratch2,rscratch2
4512 BEQ NotCPUaitingForInterruptIRQ
4515 STRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4516 NotCPUaitingForInterruptIRQ:
4517 LDRB rscratch2,[reg_cpu_var,#IRQActive_ofs]
4518 MOVS rscratch2,rscratch2
4519 BEQ CPUIRQActive_cleared
4520 TST rstatus,#MASK_IRQ
4521 BNE CPUFlagsIRQ_PENDING_FLAG_cleared
4523 LDR rscratch,[reg_cpu_var,#Flags_ofs]
4524 B CPUFlagsIRQ_PENDING_FLAG_cleared
4525 CPUIRQActive_cleared:
4526 BIC rscratch,rscratch,#IRQ_PENDING_FLAG
4527 STR rscratch,[reg_cpu_var,#Flags_ofs]
4528 B CPUFlagsIRQ_PENDING_FLAG_cleared
4529 CPUIRQCycleCount_NotZero:
4530 SUB rscratch2,rscratch2,#1
4531 STR rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4532 CPUFlagsIRQ_PENDING_FLAG_cleared:
4534 TST rscratch,#SCAN_KEYS_FLAG @ Check SCAN_KEYS_FLAG
4537 EXEC_OP @ Execute next opcode
4540 /*Registers.PC = CPU.PC - CPU.PCBase;
4542 APURegisters.PC = IAPU.PC - IAPU.RAM;
4543 S9xAPUPackStatus ();
4545 if (CPU.Flags & SCAN_KEYS_FLAG)
4548 CPU.Flags &= ~SCAN_KEYS_FLAG;
4552 LDMFD R13!,{R4-R11, LR}
4555 .size asmMainLoop, asmMainLoop-.
4557 @ void test_opcode(struct asm_cpu_var *asm_var);
4560 STMFD R13!,{R4-R11,LR}
4561 @ init pointer to CPUvar structure
4565 @ get cpu mode from flag and init jump table
4571 /*****************************************************************
4573 *****************************************************************/
4576 jumptable1: .long Op00mod1
4837 lbl01mod1a: DirectIndexedIndirect1
4844 lbl03mod1a: StackasmRelative
4860 lbl07mod1a: DirectIndirectLong
4876 lbl0Cmod1a: Absolute
4880 lbl0Dmod1a: Absolute
4884 lbl0Emod1a: Absolute
4888 lbl0Fmod1a: AbsoluteLong
4895 lbl11mod1a: DirectIndirectIndexed1
4899 lbl12mod1a: DirectIndirect
4903 lbl13mod1a: StackasmRelativeIndirectIndexed1
4911 lbl15mod1a: DirectIndexedX1
4915 lbl16mod1a: DirectIndexedX1
4919 lbl17mod1a: DirectIndirectIndexedLong1
4926 lbl19mod1a: AbsoluteIndexedY1
4936 lbl1Cmod1a: Absolute
4940 lbl1Dmod1a: AbsoluteIndexedX1
4944 lbl1Emod1a: AbsoluteIndexedX1
4948 lbl1Fmod1a: AbsoluteLongIndexedX1
4955 lbl21mod1a: DirectIndexedIndirect1
4962 lbl23mod1a: StackasmRelative
4978 lbl27mod1a: DirectIndirectLong
4995 lbl2Cmod1a: Absolute
4999 lbl2Dmod1a: Absolute
5003 lbl2Emod1a: Absolute
5007 lbl2Fmod1a: AbsoluteLong
5014 lbl31mod1a: DirectIndirectIndexed1
5018 lbl32mod1a: DirectIndirect
5022 lbl33mod1a: StackasmRelativeIndirectIndexed1
5026 lbl34mod1a: DirectIndexedX1
5030 lbl35mod1a: DirectIndexedX1
5034 lbl36mod1a: DirectIndexedX1
5038 lbl37mod1a: DirectIndirectIndexedLong1
5045 lbl39mod1a: AbsoluteIndexedY1
5055 lbl3Cmod1a: AbsoluteIndexedX1
5059 lbl3Dmod1a: AbsoluteIndexedX1
5063 lbl3Emod1a: AbsoluteIndexedX1
5067 lbl3Fmod1a: AbsoluteLongIndexedX1
5075 lbl41mod1a: DirectIndexedIndirect1
5082 lbl43mod1a: StackasmRelative
5097 lbl47mod1a: DirectIndirectLong
5116 lbl4Dmod1a: Absolute
5120 lbl4Emod1a: Absolute
5124 lbl4Fmod1a: AbsoluteLong
5131 lbl51mod1a: DirectIndirectIndexed1
5135 lbl52mod1a: DirectIndirect
5139 lbl53mod1a: StackasmRelativeIndirectIndexed1
5146 lbl55mod1a: DirectIndexedX1
5150 lbl56mod1a: DirectIndexedX1
5154 lbl57mod1a: DirectIndirectIndexedLong1
5161 lbl59mod1a: AbsoluteIndexedY1
5174 lbl5Dmod1a: AbsoluteIndexedX1
5178 lbl5Emod1a: AbsoluteIndexedX1
5182 lbl5Fmod1a: AbsoluteLongIndexedX1
5189 lbl61mod1a: DirectIndexedIndirect1
5196 lbl63mod1a: StackasmRelative
5212 lbl67mod1a: DirectIndirectLong
5219 lbl69mod1a: Immediate8
5232 lbl6Dmod1a: Absolute
5236 lbl6Emod1a: Absolute
5240 lbl6Fmod1a: AbsoluteLong
5247 lbl71mod1a: DirectIndirectIndexed1
5251 lbl72mod1a: DirectIndirect
5255 lbl73mod1a: StackasmRelativeIndirectIndexed1
5260 lbl74mod1a: DirectIndexedX1
5264 lbl75mod1a: DirectIndexedX1
5268 lbl76mod1a: DirectIndexedX1
5272 lbl77mod1a: DirectIndirectIndexedLong1
5279 lbl79mod1a: AbsoluteIndexedY1
5289 lbl7Cmod1: AbsoluteIndexedIndirectX1
5293 lbl7Dmod1a: AbsoluteIndexedX1
5297 lbl7Emod1a: AbsoluteIndexedX1
5301 lbl7Fmod1a: AbsoluteLongIndexedX1
5310 lbl81mod1a: DirectIndexedIndirect1
5317 lbl83mod1a: StackasmRelative
5333 lbl87mod1a: DirectIndirectLong
5349 lbl8Cmod1a: Absolute
5353 lbl8Dmod1a: Absolute
5357 lbl8Emod1a: Absolute
5361 lbl8Fmod1a: AbsoluteLong
5368 lbl91mod1a: DirectIndirectIndexed1
5372 lbl92mod1a: DirectIndirect
5376 lbl93mod1a: StackasmRelativeIndirectIndexed1
5380 lbl94mod1a: DirectIndexedX1
5384 lbl95mod1a: DirectIndexedX1
5388 lbl96mod1a: DirectIndexedY1
5392 lbl97mod1a: DirectIndirectIndexedLong1
5399 lbl99mod1a: AbsoluteIndexedY1
5409 lbl9Cmod1a: Absolute
5413 lbl9Dmod1a: AbsoluteIndexedX1
5417 lbl9Emod1: AbsoluteIndexedX1
5421 lbl9Fmod1a: AbsoluteLongIndexedX1
5428 lblA1mod1a: DirectIndexedIndirect1
5435 lblA3mod1a: StackasmRelative
5451 lblA7mod1a: DirectIndirectLong
5467 lblACmod1a: Absolute
5471 lblADmod1a: Absolute
5475 lblAEmod1a: Absolute
5479 lblAFmod1a: AbsoluteLong
5486 lblB1mod1a: DirectIndirectIndexed1
5490 lblB2mod1a: DirectIndirect
5494 lblB3mod1a: StackasmRelativeIndirectIndexed1
5498 lblB4mod1a: DirectIndexedX1
5502 lblB5mod1a: DirectIndexedX1
5506 lblB6mod1a: DirectIndexedY1
5510 lblB7mod1a: DirectIndirectIndexedLong1
5517 lblB9mod1a: AbsoluteIndexedY1
5527 lblBCmod1a: AbsoluteIndexedX1
5531 lblBDmod1a: AbsoluteIndexedX1
5535 lblBEmod1a: AbsoluteIndexedY1
5539 lblBFmod1a: AbsoluteLongIndexedX1
5546 lblC1mod1a: DirectIndexedIndirect1
5554 lblC3mod1a: StackasmRelative
5570 lblC7mod1a: DirectIndirectLong
5586 lblCCmod1a: Absolute
5590 lblCDmod1a: Absolute
5594 lblCEmod1a: Absolute
5598 lblCFmod1a: AbsoluteLong
5605 lblD1mod1a: DirectIndirectIndexed1
5609 lblD2mod1a: DirectIndirect
5613 lblD3mod1a: StackasmRelativeIndirectIndexed1
5620 lblD5mod1a: DirectIndexedX1
5624 lblD6mod1a: DirectIndexedX1
5628 lblD7mod1a: DirectIndirectIndexedLong1
5635 lblD9mod1a: AbsoluteIndexedY1
5648 lblDDmod1a: AbsoluteIndexedX1
5652 lblDEmod1a: AbsoluteIndexedX1
5656 lblDFmod1a: AbsoluteLongIndexedX1
5663 lblE1mod1a: DirectIndexedIndirect1
5671 lblE3mod1a: StackasmRelative
5687 lblE7mod1a: DirectIndirectLong
5694 lblE9mod1a: Immediate8
5704 lblECmod1a: Absolute
5708 lblEDmod1a: Absolute
5712 lblEEmod1a: Absolute
5716 lblEFmod1a: AbsoluteLong
5723 lblF1mod1a: DirectIndirectIndexed1
5727 lblF2mod1a: DirectIndirect
5731 lblF3mod1a: StackasmRelativeIndirectIndexed1
5738 lblF5mod1a: DirectIndexedX1
5742 lblF6mod1a: DirectIndexedX1
5746 lblF7mod1a: DirectIndirectIndexedLong1
5753 lblF9mod1a: AbsoluteIndexedY1
5766 lblFDmod1a: AbsoluteIndexedX1
5770 lblFEmod1a: AbsoluteIndexedX1
5774 lblFFmod1a: AbsoluteLongIndexedX1
5780 jumptable2: .long Op00mod2
6040 lbl01mod2a: DirectIndexedIndirect0
6047 lbl03mod2a: StackasmRelative
6063 lbl07mod2a: DirectIndirectLong
6079 lbl0Cmod2a: Absolute
6083 lbl0Dmod2a: Absolute
6087 lbl0Emod2a: Absolute
6091 lbl0Fmod2a: AbsoluteLong
6098 lbl11mod2a: DirectIndirectIndexed0
6102 lbl12mod2a: DirectIndirect
6106 lbl13mod2a: StackasmRelativeIndirectIndexed0
6114 lbl15mod2a: DirectIndexedX0
6118 lbl16mod2a: DirectIndexedX0
6122 lbl17mod2a: DirectIndirectIndexedLong0
6129 lbl19mod2a: AbsoluteIndexedY0
6139 lbl1Cmod2a: Absolute
6143 lbl1Dmod2a: AbsoluteIndexedX0
6147 lbl1Emod2a: AbsoluteIndexedX0
6151 lbl1Fmod2a: AbsoluteLongIndexedX0
6158 lbl21mod2a: DirectIndexedIndirect0
6165 lbl23mod2a: StackasmRelative
6181 lbl27mod2a: DirectIndirectLong
6198 lbl2Cmod2a: Absolute
6202 lbl2Dmod2a: Absolute
6206 lbl2Emod2a: Absolute
6210 lbl2Fmod2a: AbsoluteLong
6217 lbl31mod2a: DirectIndirectIndexed0
6221 lbl32mod2a: DirectIndirect
6225 lbl33mod2a: StackasmRelativeIndirectIndexed0
6229 lbl34mod2a: DirectIndexedX0
6233 lbl35mod2a: DirectIndexedX0
6237 lbl36mod2a: DirectIndexedX0
6241 lbl37mod2a: DirectIndirectIndexedLong0
6248 lbl39mod2a: AbsoluteIndexedY0
6258 lbl3Cmod2a: AbsoluteIndexedX0
6262 lbl3Dmod2a: AbsoluteIndexedX0
6266 lbl3Emod2a: AbsoluteIndexedX0
6270 lbl3Fmod2a: AbsoluteLongIndexedX0
6278 lbl41mod2a: DirectIndexedIndirect0
6285 lbl43mod2a: StackasmRelative
6300 lbl47mod2a: DirectIndirectLong
6319 lbl4Dmod2a: Absolute
6323 lbl4Emod2a: Absolute
6327 lbl4Fmod2a: AbsoluteLong
6334 lbl51mod2a: DirectIndirectIndexed0
6338 lbl52mod2a: DirectIndirect
6342 lbl53mod2a: StackasmRelativeIndirectIndexed0
6349 lbl55mod2a: DirectIndexedX0
6353 lbl56mod2a: DirectIndexedX0
6357 lbl57mod2a: DirectIndirectIndexedLong0
6364 lbl59mod2a: AbsoluteIndexedY0
6377 lbl5Dmod2a: AbsoluteIndexedX0
6381 lbl5Emod2a: AbsoluteIndexedX0
6385 lbl5Fmod2a: AbsoluteLongIndexedX0
6392 lbl61mod2a: DirectIndexedIndirect0
6399 lbl63mod2a: StackasmRelative
6415 lbl67mod2a: DirectIndirectLong
6422 lbl69mod2a: Immediate8
6435 lbl6Dmod2a: Absolute
6439 lbl6Emod2a: Absolute
6443 lbl6Fmod2a: AbsoluteLong
6450 lbl71mod2a: DirectIndirectIndexed0
6454 lbl72mod2a: DirectIndirect
6458 lbl73mod2a: StackasmRelativeIndirectIndexed0
6462 lbl74mod2a: DirectIndexedX0
6466 lbl75mod2a: DirectIndexedX0
6470 lbl76mod2a: DirectIndexedX0
6474 lbl77mod2a: DirectIndirectIndexedLong0
6481 lbl79mod2a: AbsoluteIndexedY0
6491 lbl7Cmod2: AbsoluteIndexedIndirectX0
6495 lbl7Dmod2a: AbsoluteIndexedX0
6499 lbl7Emod2a: AbsoluteIndexedX0
6503 lbl7Fmod2a: AbsoluteLongIndexedX0
6512 lbl81mod2a: DirectIndexedIndirect0
6519 lbl83mod2a: StackasmRelative
6535 lbl87mod2a: DirectIndirectLong
6551 lbl8Cmod2a: Absolute
6555 lbl8Dmod2a: Absolute
6559 lbl8Emod2a: Absolute
6563 lbl8Fmod2a: AbsoluteLong
6570 lbl91mod2a: DirectIndirectIndexed0
6574 lbl92mod2a: DirectIndirect
6578 lbl93mod2a: StackasmRelativeIndirectIndexed0
6582 lbl94mod2a: DirectIndexedX0
6586 lbl95mod2a: DirectIndexedX0
6590 lbl96mod2a: DirectIndexedY0
6594 lbl97mod2a: DirectIndirectIndexedLong0
6601 lbl99mod2a: AbsoluteIndexedY0
6611 lbl9Cmod2a: Absolute
6615 lbl9Dmod2a: AbsoluteIndexedX0
6619 lbl9Emod2: AbsoluteIndexedX0
6623 lbl9Fmod2a: AbsoluteLongIndexedX0
6630 lblA1mod2a: DirectIndexedIndirect0
6637 lblA3mod2a: StackasmRelative
6653 lblA7mod2a: DirectIndirectLong
6669 lblACmod2a: Absolute
6673 lblADmod2a: Absolute
6677 lblAEmod2a: Absolute
6681 lblAFmod2a: AbsoluteLong
6688 lblB1mod2a: DirectIndirectIndexed0
6692 lblB2mod2a: DirectIndirect
6696 lblB3mod2a: StackasmRelativeIndirectIndexed0
6700 lblB4mod2a: DirectIndexedX0
6704 lblB5mod2a: DirectIndexedX0
6708 lblB6mod2a: DirectIndexedY0
6712 lblB7mod2a: DirectIndirectIndexedLong0
6719 lblB9mod2a: AbsoluteIndexedY0
6729 lblBCmod2a: AbsoluteIndexedX0
6733 lblBDmod2a: AbsoluteIndexedX0
6737 lblBEmod2a: AbsoluteIndexedY0
6741 lblBFmod2a: AbsoluteLongIndexedX0
6748 lblC1mod2a: DirectIndexedIndirect0
6756 lblC3mod2a: StackasmRelative
6772 lblC7mod2a: DirectIndirectLong
6788 lblCCmod2a: Absolute
6792 lblCDmod2a: Absolute
6796 lblCEmod2a: Absolute
6800 lblCFmod2a: AbsoluteLong
6807 lblD1mod2a: DirectIndirectIndexed0
6811 lblD2mod2a: DirectIndirect
6815 lblD3mod2a: StackasmRelativeIndirectIndexed0
6822 lblD5mod2a: DirectIndexedX0
6826 lblD6mod2a: DirectIndexedX0
6830 lblD7mod2a: DirectIndirectIndexedLong0
6837 lblD9mod2a: AbsoluteIndexedY0
6850 lblDDmod2a: AbsoluteIndexedX0
6854 lblDEmod2a: AbsoluteIndexedX0
6858 lblDFmod2a: AbsoluteLongIndexedX0
6865 lblE1mod2a: DirectIndexedIndirect0
6873 lblE3mod2a: StackasmRelative
6889 lblE7mod2a: DirectIndirectLong
6896 lblE9mod2a: Immediate8
6906 lblECmod2a: Absolute
6910 lblEDmod2a: Absolute
6914 lblEEmod2a: Absolute
6918 lblEFmod2a: AbsoluteLong
6925 lblF1mod2a: DirectIndirectIndexed0
6929 lblF2mod2a: DirectIndirect
6933 lblF3mod2a: StackasmRelativeIndirectIndexed0
6940 lblF5mod2a: DirectIndexedX0
6944 lblF6mod2a: DirectIndexedX0
6948 lblF7mod2a: DirectIndirectIndexedLong0
6955 lblF9mod2a: AbsoluteIndexedY0
6968 lblFDmod2a: AbsoluteIndexedX0
6972 lblFEmod2a: AbsoluteIndexedX0
6976 lblFFmod2a: AbsoluteLongIndexedX0
6983 jumptable3: .long Op00mod3
7243 lbl01mod3a: DirectIndexedIndirect0
7250 lbl03mod3a: StackasmRelative
7266 lbl07mod3a: DirectIndirectLong
7282 lbl0Cmod3a: Absolute
7286 lbl0Dmod3a: Absolute
7290 lbl0Emod3a: Absolute
7294 lbl0Fmod3a: AbsoluteLong
7301 lbl11mod3a: DirectIndirectIndexed0
7305 lbl12mod3a: DirectIndirect
7309 lbl13mod3a: StackasmRelativeIndirectIndexed0
7317 lbl15mod3a: DirectIndexedX0
7321 lbl16mod3a: DirectIndexedX0
7325 lbl17mod3a: DirectIndirectIndexedLong0
7332 lbl19mod3a: AbsoluteIndexedY0
7342 lbl1Cmod3a: Absolute
7346 lbl1Dmod3a: AbsoluteIndexedX0
7350 lbl1Emod3a: AbsoluteIndexedX0
7354 lbl1Fmod3a: AbsoluteLongIndexedX0
7361 lbl21mod3a: DirectIndexedIndirect0
7368 lbl23mod3a: StackasmRelative
7384 lbl27mod3a: DirectIndirectLong
7401 lbl2Cmod3a: Absolute
7405 lbl2Dmod3a: Absolute
7409 lbl2Emod3a: Absolute
7413 lbl2Fmod3a: AbsoluteLong
7420 lbl31mod3a: DirectIndirectIndexed0
7424 lbl32mod3a: DirectIndirect
7428 lbl33mod3a: StackasmRelativeIndirectIndexed0
7432 lbl34mod3a: DirectIndexedX0
7436 lbl35mod3a: DirectIndexedX0
7440 lbl36mod3a: DirectIndexedX0
7444 lbl37mod3a: DirectIndirectIndexedLong0
7451 lbl39mod3a: AbsoluteIndexedY0
7461 lbl3Cmod3a: AbsoluteIndexedX0
7465 lbl3Dmod3a: AbsoluteIndexedX0
7469 lbl3Emod3a: AbsoluteIndexedX0
7473 lbl3Fmod3a: AbsoluteLongIndexedX0
7481 lbl41mod3a: DirectIndexedIndirect0
7488 lbl43mod3a: StackasmRelative
7503 lbl47mod3a: DirectIndirectLong
7522 lbl4Dmod3a: Absolute
7526 lbl4Emod3a: Absolute
7530 lbl4Fmod3a: AbsoluteLong
7537 lbl51mod3a: DirectIndirectIndexed0
7541 lbl52mod3a: DirectIndirect
7545 lbl53mod3a: StackasmRelativeIndirectIndexed0
7552 lbl55mod3a: DirectIndexedX0
7556 lbl56mod3a: DirectIndexedX0
7560 lbl57mod3a: DirectIndirectIndexedLong0
7567 lbl59mod3a: AbsoluteIndexedY0
7580 lbl5Dmod3a: AbsoluteIndexedX0
7584 lbl5Emod3a: AbsoluteIndexedX0
7588 lbl5Fmod3a: AbsoluteLongIndexedX0
7595 lbl61mod3a: DirectIndexedIndirect0
7602 lbl63mod3a: StackasmRelative
7620 lbl67mod3a: DirectIndirectLong
7628 lbl69mod3a: Immediate16
7642 lbl6Dmod3a: Absolute
7646 lbl6Emod3a: Absolute
7650 lbl6Fmod3a: AbsoluteLong
7657 lbl71mod3a: DirectIndirectIndexed0
7661 lbl72mod3a: DirectIndirect
7665 lbl73mod3a: StackasmRelativeIndirectIndexed0
7670 lbl74mod3a: DirectIndexedX0
7674 lbl75mod3a: DirectIndexedX0
7679 lbl76mod3a: DirectIndexedX0
7683 lbl77mod3a: DirectIndirectIndexedLong0
7690 lbl79mod3a: AbsoluteIndexedY0
7700 lbl7Cmod3: AbsoluteIndexedIndirectX0
7704 lbl7Dmod3a: AbsoluteIndexedX0
7708 lbl7Emod3a: AbsoluteIndexedX0
7712 lbl7Fmod3a: AbsoluteLongIndexedX0
7720 lbl81mod3a: DirectIndexedIndirect0
7727 lbl83mod3a: StackasmRelative
7743 lbl87mod3a: DirectIndirectLong
7759 lbl8Cmod3a: Absolute
7763 lbl8Dmod3a: Absolute
7767 lbl8Emod3a: Absolute
7771 lbl8Fmod3a: AbsoluteLong
7778 lbl91mod3a: DirectIndirectIndexed0
7782 lbl92mod3a: DirectIndirect
7786 lbl93mod3a: StackasmRelativeIndirectIndexed0
7790 lbl94mod3a: DirectIndexedX0
7794 lbl95mod3a: DirectIndexedX0
7798 lbl96mod3a: DirectIndexedY0
7802 lbl97mod3a: DirectIndirectIndexedLong0
7809 lbl99mod3a: AbsoluteIndexedY0
7819 lbl9Cmod3a: Absolute
7823 lbl9Dmod3a: AbsoluteIndexedX0
7827 lbl9Emod3: AbsoluteIndexedX0
7831 lbl9Fmod3a: AbsoluteLongIndexedX0
7838 lblA1mod3a: DirectIndexedIndirect0
7845 lblA3mod3a: StackasmRelative
7861 lblA7mod3a: DirectIndirectLong
7877 lblACmod3a: Absolute
7881 lblADmod3a: Absolute
7885 lblAEmod3a: Absolute
7889 lblAFmod3a: AbsoluteLong
7896 lblB1mod3a: DirectIndirectIndexed0
7900 lblB2mod3a: DirectIndirect
7904 lblB3mod3a: StackasmRelativeIndirectIndexed0
7908 lblB4mod3a: DirectIndexedX0
7912 lblB5mod3a: DirectIndexedX0
7916 lblB6mod3a: DirectIndexedY0
7920 lblB7mod3a: DirectIndirectIndexedLong0
7927 lblB9mod3a: AbsoluteIndexedY0
7937 lblBCmod3a: AbsoluteIndexedX0
7941 lblBDmod3a: AbsoluteIndexedX0
7945 lblBEmod3a: AbsoluteIndexedY0
7949 lblBFmod3a: AbsoluteLongIndexedX0
7956 lblC1mod3a: DirectIndexedIndirect0
7964 lblC3mod3a: StackasmRelative
7980 lblC7mod3a: DirectIndirectLong
7996 lblCCmod3a: Absolute
8000 lblCDmod3a: Absolute
8004 lblCEmod3a: Absolute
8008 lblCFmod3a: AbsoluteLong
8015 lblD1mod3a: DirectIndirectIndexed0
8019 lblD2mod3a: DirectIndirect
8023 lblD3mod3a: StackasmRelativeIndirectIndexed0
8030 lblD5mod3a: DirectIndexedX0
8034 lblD6mod3a: DirectIndexedX0
8038 lblD7mod3a: DirectIndirectIndexedLong0
8045 lblD9mod3a: AbsoluteIndexedY0
8058 lblDDmod3a: AbsoluteIndexedX0
8062 lblDEmod3a: AbsoluteIndexedX0
8066 lblDFmod3a: AbsoluteLongIndexedX0
8073 lblE1mod3a: DirectIndexedIndirect0
8081 lblE3mod3a: StackasmRelative
8097 lblE7mod3a: DirectIndirectLong
8104 lblE9mod3a: Immediate16
8114 lblECmod3a: Absolute
8118 lblEDmod3a: Absolute
8122 lblEEmod3a: Absolute
8126 lblEFmod3a: AbsoluteLong
8133 lblF1mod3a: DirectIndirectIndexed0
8137 lblF2mod3a: DirectIndirect
8141 lblF3mod3a: StackasmRelativeIndirectIndexed0
8148 lblF5mod3a: DirectIndexedX0
8152 lblF6mod3a: DirectIndexedX0
8156 lblF7mod3a: DirectIndirectIndexedLong0
8163 lblF9mod3a: AbsoluteIndexedY0
8176 lblFDmod3a: AbsoluteIndexedX0
8180 lblFEmod3a: AbsoluteIndexedX0
8184 lblFFmod3a: AbsoluteLongIndexedX0
8189 jumptable4: .long Op00mod4
8449 lbl01mod4a: DirectIndexedIndirect1
8456 lbl03mod4a: StackasmRelative
8472 lbl07mod4a: DirectIndirectLong
8488 lbl0Cmod4a: Absolute
8492 lbl0Dmod4a: Absolute
8496 lbl0Emod4a: Absolute
8500 lbl0Fmod4a: AbsoluteLong
8507 lbl11mod4a: DirectIndirectIndexed1
8511 lbl12mod4a: DirectIndirect
8515 lbl13mod4a: StackasmRelativeIndirectIndexed1
8523 lbl15mod4a: DirectIndexedX1
8527 lbl16mod4a: DirectIndexedX1
8531 lbl17mod4a: DirectIndirectIndexedLong1
8538 lbl19mod4a: AbsoluteIndexedY1
8548 lbl1Cmod4a: Absolute
8552 lbl1Dmod4a: AbsoluteIndexedX1
8556 lbl1Emod4a: AbsoluteIndexedX1
8560 lbl1Fmod4a: AbsoluteLongIndexedX1
8567 lbl21mod4a: DirectIndexedIndirect1
8574 lbl23mod4a: StackasmRelative
8590 lbl27mod4a: DirectIndirectLong
8607 lbl2Cmod4a: Absolute
8611 lbl2Dmod4a: Absolute
8615 lbl2Emod4a: Absolute
8619 lbl2Fmod4a: AbsoluteLong
8626 lbl31mod4a: DirectIndirectIndexed1
8630 lbl32mod4a: DirectIndirect
8634 lbl33mod4a: StackasmRelativeIndirectIndexed1
8638 lbl34mod4a: DirectIndexedX1
8642 lbl35mod4a: DirectIndexedX1
8646 lbl36mod4a: DirectIndexedX1
8650 lbl37mod4a: DirectIndirectIndexedLong1
8657 lbl39mod4a: AbsoluteIndexedY1
8667 lbl3Cmod4a: AbsoluteIndexedX1
8671 lbl3Dmod4a: AbsoluteIndexedX1
8675 lbl3Emod4a: AbsoluteIndexedX1
8679 lbl3Fmod4a: AbsoluteLongIndexedX1
8687 lbl41mod4a: DirectIndexedIndirect1
8694 lbl43mod4a: StackasmRelative
8709 lbl47mod4a: DirectIndirectLong
8728 lbl4Dmod4a: Absolute
8732 lbl4Emod4a: Absolute
8736 lbl4Fmod4a: AbsoluteLong
8743 lbl51mod4a: DirectIndirectIndexed1
8747 lbl52mod4a: DirectIndirect
8751 lbl53mod4a: StackasmRelativeIndirectIndexed1
8758 lbl55mod4a: DirectIndexedX1
8762 lbl56mod4a: DirectIndexedX1
8766 lbl57mod4a: DirectIndirectIndexedLong1
8773 lbl59mod4a: AbsoluteIndexedY1
8786 lbl5Dmod4a: AbsoluteIndexedX1
8790 lbl5Emod4a: AbsoluteIndexedX1
8794 lbl5Fmod4a: AbsoluteLongIndexedX1
8801 lbl61mod4a: DirectIndexedIndirect1
8808 lbl63mod4a: StackasmRelative
8826 lbl67mod4a: DirectIndirectLong
8834 lbl69mod4a: Immediate16
8848 lbl6Dmod4a: Absolute
8852 lbl6Emod4a: Absolute
8856 lbl6Fmod4a: AbsoluteLong
8863 lbl71mod4a: DirectIndirectIndexed1
8867 lbl72mod4a: DirectIndirect
8871 lbl73mod4a: StackasmRelativeIndirectIndexed1
8876 lbl74mod4a: DirectIndexedX1
8880 lbl75mod4a: DirectIndexedX1
8885 lbl76mod4a: DirectIndexedX1
8889 lbl77mod4a: DirectIndirectIndexedLong1
8896 lbl79mod4a: AbsoluteIndexedY1
8906 lbl7Cmod4: AbsoluteIndexedIndirectX1
8910 lbl7Dmod4a: AbsoluteIndexedX1
8914 lbl7Emod4a: AbsoluteIndexedX1
8918 lbl7Fmod4a: AbsoluteLongIndexedX1
8926 lbl81mod4a: DirectIndexedIndirect1
8933 lbl83mod4a: StackasmRelative
8949 lbl87mod4a: DirectIndirectLong
8965 lbl8Cmod4a: Absolute
8969 lbl8Dmod4a: Absolute
8973 lbl8Emod4a: Absolute
8977 lbl8Fmod4a: AbsoluteLong
8984 lbl91mod4a: DirectIndirectIndexed1
8988 lbl92mod4a: DirectIndirect
8992 lbl93mod4a: StackasmRelativeIndirectIndexed1
8996 lbl94mod4a: DirectIndexedX1
9000 lbl95mod4a: DirectIndexedX1
9004 lbl96mod4a: DirectIndexedY1
9008 lbl97mod4a: DirectIndirectIndexedLong1
9015 lbl99mod4a: AbsoluteIndexedY1
9025 lbl9Cmod4a: Absolute
9029 lbl9Dmod4a: AbsoluteIndexedX1
9033 lbl9Emod4: AbsoluteIndexedX1
9037 lbl9Fmod4a: AbsoluteLongIndexedX1
9044 lblA1mod4a: DirectIndexedIndirect1
9051 lblA3mod4a: StackasmRelative
9067 lblA7mod4a: DirectIndirectLong
9083 lblACmod4a: Absolute
9087 lblADmod4a: Absolute
9091 lblAEmod4a: Absolute
9095 lblAFmod4a: AbsoluteLong
9102 lblB1mod4a: DirectIndirectIndexed1
9106 lblB2mod4a: DirectIndirect
9110 lblB3mod4a: StackasmRelativeIndirectIndexed1
9114 lblB4mod4a: DirectIndexedX1
9118 lblB5mod4a: DirectIndexedX1
9122 lblB6mod4a: DirectIndexedY1
9126 lblB7mod4a: DirectIndirectIndexedLong1
9133 lblB9mod4a: AbsoluteIndexedY1
9143 lblBCmod4a: AbsoluteIndexedX1
9147 lblBDmod4a: AbsoluteIndexedX1
9151 lblBEmod4a: AbsoluteIndexedY1
9155 lblBFmod4a: AbsoluteLongIndexedX1
9162 lblC1mod4a: DirectIndexedIndirect1
9170 lblC3mod4a: StackasmRelative
9186 lblC7mod4a: DirectIndirectLong
9202 lblCCmod4a: Absolute
9206 lblCDmod4a: Absolute
9210 lblCEmod4a: Absolute
9214 lblCFmod4a: AbsoluteLong
9221 lblD1mod4a: DirectIndirectIndexed1
9225 lblD2mod4a: DirectIndirect
9229 lblD3mod4a: StackasmRelativeIndirectIndexed1
9236 lblD5mod4a: DirectIndexedX1
9240 lblD6mod4a: DirectIndexedX1
9244 lblD7mod4a: DirectIndirectIndexedLong1
9251 lblD9mod4a: AbsoluteIndexedY1
9264 lblDDmod4a: AbsoluteIndexedX1
9268 lblDEmod4a: AbsoluteIndexedX1
9272 lblDFmod4a: AbsoluteLongIndexedX1
9279 lblE1mod4a: DirectIndexedIndirect1
9287 lblE3mod4a: StackasmRelative
9303 lblE7mod4a: DirectIndirectLong
9310 lblE9mod4a: Immediate16
9320 lblECmod4a: Absolute
9324 lblEDmod4a: Absolute
9328 lblEEmod4a: Absolute
9332 lblEFmod4a: AbsoluteLong
9339 lblF1mod4a: DirectIndirectIndexed1
9343 lblF2mod4a: DirectIndirect
9347 lblF3mod4a: StackasmRelativeIndirectIndexed1
9354 lblF5mod4a: DirectIndexedX1
9358 lblF6mod4a: DirectIndexedX1
9362 lblF7mod4a: DirectIndirectIndexedLong1
9369 lblF9mod4a: AbsoluteIndexedY1
9382 lblFDmod4a: AbsoluteIndexedX1
9386 lblFEmod4a: AbsoluteIndexedX1
9390 lblFFmod4a: AbsoluteLongIndexedX1