8 static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
10 qemu_put_be32(f, dt->selector);
11 qemu_put_betl(f, dt->base);
12 qemu_put_be32(f, dt->limit);
13 qemu_put_be32(f, dt->flags);
16 static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
18 dt->selector = qemu_get_be32(f);
19 dt->base = qemu_get_betl(f);
20 dt->limit = qemu_get_be32(f);
21 dt->flags = qemu_get_be32(f);
24 void cpu_save(QEMUFile *f, void *opaque)
26 CPUState *env = opaque;
27 uint16_t fptag, fpus, fpuc, fpregs_format;
32 for(i = 0; i < CPU_NB_REGS; i++)
33 qemu_put_betls(f, &env->regs[i]);
34 qemu_put_betls(f, &env->eip);
35 qemu_put_betls(f, &env->eflags);
36 hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
37 qemu_put_be32s(f, &hflags);
41 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
43 for(i = 0; i < 8; i++) {
44 fptag |= ((!env->fptags[i]) << i);
47 qemu_put_be16s(f, &fpuc);
48 qemu_put_be16s(f, &fpus);
49 qemu_put_be16s(f, &fptag);
56 qemu_put_be16s(f, &fpregs_format);
58 for(i = 0; i < 8; i++) {
63 /* we save the real CPU data (in case of MMX usage only 'mant'
64 contains the MMX register */
65 cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
66 qemu_put_be64(f, mant);
67 qemu_put_be16(f, exp);
70 /* if we use doubles for float emulation, we save the doubles to
71 avoid losing information in case of MMX usage. It can give
72 problems if the image is restored on a CPU where long
73 doubles are used instead. */
74 qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
78 for(i = 0; i < 6; i++)
79 cpu_put_seg(f, &env->segs[i]);
80 cpu_put_seg(f, &env->ldt);
81 cpu_put_seg(f, &env->tr);
82 cpu_put_seg(f, &env->gdt);
83 cpu_put_seg(f, &env->idt);
85 qemu_put_be32s(f, &env->sysenter_cs);
86 qemu_put_betls(f, &env->sysenter_esp);
87 qemu_put_betls(f, &env->sysenter_eip);
89 qemu_put_betls(f, &env->cr[0]);
90 qemu_put_betls(f, &env->cr[2]);
91 qemu_put_betls(f, &env->cr[3]);
92 qemu_put_betls(f, &env->cr[4]);
94 for(i = 0; i < 8; i++)
95 qemu_put_betls(f, &env->dr[i]);
98 a20_mask = (int32_t) env->a20_mask;
99 qemu_put_sbe32s(f, &a20_mask);
102 qemu_put_be32s(f, &env->mxcsr);
103 for(i = 0; i < CPU_NB_REGS; i++) {
104 qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
105 qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
109 qemu_put_be64s(f, &env->efer);
110 qemu_put_be64s(f, &env->star);
111 qemu_put_be64s(f, &env->lstar);
112 qemu_put_be64s(f, &env->cstar);
113 qemu_put_be64s(f, &env->fmask);
114 qemu_put_be64s(f, &env->kernelgsbase);
116 qemu_put_be32s(f, &env->smbase);
118 qemu_put_be64s(f, &env->pat);
119 qemu_put_be32s(f, &env->hflags2);
121 qemu_put_be64s(f, &env->vm_hsave);
122 qemu_put_be64s(f, &env->vm_vmcb);
123 qemu_put_be64s(f, &env->tsc_offset);
124 qemu_put_be64s(f, &env->intercept);
125 qemu_put_be16s(f, &env->intercept_cr_read);
126 qemu_put_be16s(f, &env->intercept_cr_write);
127 qemu_put_be16s(f, &env->intercept_dr_read);
128 qemu_put_be16s(f, &env->intercept_dr_write);
129 qemu_put_be32s(f, &env->intercept_exceptions);
130 qemu_put_8s(f, &env->v_tpr);
133 for(i = 0; i < 11; i++)
134 qemu_put_be64s(f, &env->mtrr_fixed[i]);
135 qemu_put_be64s(f, &env->mtrr_deftype);
136 for(i = 0; i < 8; i++) {
137 qemu_put_be64s(f, &env->mtrr_var[i].base);
138 qemu_put_be64s(f, &env->mtrr_var[i].mask);
142 #ifdef USE_X86LDOUBLE
143 /* XXX: add that in a FPU generic layer */
144 union x86_longdouble {
149 #define MANTD1(fp) (fp & ((1LL << 52) - 1))
150 #define EXPBIAS1 1023
151 #define EXPD1(fp) ((fp >> 52) & 0x7FF)
152 #define SIGND1(fp) ((fp >> 32) & 0x80000000)
154 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
158 p->mant = (MANTD1(temp) << 11) | (1LL << 63);
159 /* exponent + sign */
160 e = EXPD1(temp) - EXPBIAS1 + 16383;
161 e |= SIGND1(temp) >> 16;
166 int cpu_load(QEMUFile *f, void *opaque, int version_id)
168 CPUState *env = opaque;
171 uint16_t fpus, fpuc, fptag, fpregs_format;
174 if (version_id != 3 && version_id != 4 && version_id != 5
175 && version_id != 6 && version_id != 7 && version_id != 8)
177 for(i = 0; i < CPU_NB_REGS; i++)
178 qemu_get_betls(f, &env->regs[i]);
179 qemu_get_betls(f, &env->eip);
180 qemu_get_betls(f, &env->eflags);
181 qemu_get_be32s(f, &hflags);
183 qemu_get_be16s(f, &fpuc);
184 qemu_get_be16s(f, &fpus);
185 qemu_get_be16s(f, &fptag);
186 qemu_get_be16s(f, &fpregs_format);
188 /* NOTE: we cannot always restore the FPU state if the image come
189 from a host with a different 'USE_X86LDOUBLE' define. We guess
190 if we are in an MMX state to restore correctly in that case. */
191 guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
192 for(i = 0; i < 8; i++) {
196 switch(fpregs_format) {
198 mant = qemu_get_be64(f);
199 exp = qemu_get_be16(f);
200 #ifdef USE_X86LDOUBLE
201 env->fpregs[i].d = cpu_set_fp80(mant, exp);
205 env->fpregs[i].mmx.MMX_Q(0) = mant;
207 env->fpregs[i].d = cpu_set_fp80(mant, exp);
211 mant = qemu_get_be64(f);
212 #ifdef USE_X86LDOUBLE
214 union x86_longdouble *p;
216 p = (void *)&env->fpregs[i];
221 fp64_to_fp80(p, mant);
225 env->fpregs[i].mmx.MMX_Q(0) = mant;
234 /* XXX: restore FPU round state */
235 env->fpstt = (fpus >> 11) & 7;
236 env->fpus = fpus & ~0x3800;
238 for(i = 0; i < 8; i++) {
239 env->fptags[i] = (fptag >> i) & 1;
242 for(i = 0; i < 6; i++)
243 cpu_get_seg(f, &env->segs[i]);
244 cpu_get_seg(f, &env->ldt);
245 cpu_get_seg(f, &env->tr);
246 cpu_get_seg(f, &env->gdt);
247 cpu_get_seg(f, &env->idt);
249 qemu_get_be32s(f, &env->sysenter_cs);
250 if (version_id >= 7) {
251 qemu_get_betls(f, &env->sysenter_esp);
252 qemu_get_betls(f, &env->sysenter_eip);
254 env->sysenter_esp = qemu_get_be32(f);
255 env->sysenter_eip = qemu_get_be32(f);
258 qemu_get_betls(f, &env->cr[0]);
259 qemu_get_betls(f, &env->cr[2]);
260 qemu_get_betls(f, &env->cr[3]);
261 qemu_get_betls(f, &env->cr[4]);
263 for(i = 0; i < 8; i++)
264 qemu_get_betls(f, &env->dr[i]);
265 cpu_breakpoint_remove_all(env, BP_CPU);
266 cpu_watchpoint_remove_all(env, BP_CPU);
267 for (i = 0; i < 4; i++)
268 hw_breakpoint_insert(env, i);
271 qemu_get_sbe32s(f, &a20_mask);
272 env->a20_mask = a20_mask;
274 qemu_get_be32s(f, &env->mxcsr);
275 for(i = 0; i < CPU_NB_REGS; i++) {
276 qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
277 qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
281 qemu_get_be64s(f, &env->efer);
282 qemu_get_be64s(f, &env->star);
283 qemu_get_be64s(f, &env->lstar);
284 qemu_get_be64s(f, &env->cstar);
285 qemu_get_be64s(f, &env->fmask);
286 qemu_get_be64s(f, &env->kernelgsbase);
288 if (version_id >= 4) {
289 qemu_get_be32s(f, &env->smbase);
291 if (version_id >= 5) {
292 qemu_get_be64s(f, &env->pat);
293 qemu_get_be32s(f, &env->hflags2);
295 qemu_get_be32s(f, &env->halted);
297 qemu_get_be64s(f, &env->vm_hsave);
298 qemu_get_be64s(f, &env->vm_vmcb);
299 qemu_get_be64s(f, &env->tsc_offset);
300 qemu_get_be64s(f, &env->intercept);
301 qemu_get_be16s(f, &env->intercept_cr_read);
302 qemu_get_be16s(f, &env->intercept_cr_write);
303 qemu_get_be16s(f, &env->intercept_dr_read);
304 qemu_get_be16s(f, &env->intercept_dr_write);
305 qemu_get_be32s(f, &env->intercept_exceptions);
306 qemu_get_8s(f, &env->v_tpr);
309 if (version_id >= 8) {
311 for(i = 0; i < 11; i++)
312 qemu_get_be64s(f, &env->mtrr_fixed[i]);
313 qemu_get_be64s(f, &env->mtrr_deftype);
314 for(i = 0; i < 8; i++) {
315 qemu_get_be64s(f, &env->mtrr_var[i].base);
316 qemu_get_be64s(f, &env->mtrr_var[i].mask);
320 /* XXX: ensure compatiblity for halted bit ? */
321 /* XXX: compute redundant hflags bits */
322 env->hflags = hflags;