2 * QEMU interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
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25 //#define DEBUG_IRQ_COUNT
27 /* These registers are used for sending/receiving irqs from/to
30 struct sun4m_intreg_percpu {
31 unsigned int tbt; /* Intrs pending for this cpu, by PIL. */
32 /* These next two registers are WRITE-ONLY and are only
33 * "on bit" sensitive, "off bits" written have NO affect.
35 unsigned int clear; /* Clear this cpus irqs here. */
36 unsigned int set; /* Set this cpus irqs here. */
40 * Actually the clear and set fields in this struct are misleading..
41 * according to the SLAVIO manual (and the same applies for the SEC)
42 * the clear field clears bits in the mask which will ENABLE that IRQ
43 * the set field sets bits in the mask to DISABLE the IRQ.
45 * Also the undirected_xx address in the SLAVIO is defined as
46 * RESERVED and write only..
48 * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
49 * sun4m machines, for MP the layout makes more sense.
51 struct sun4m_intreg_master {
52 unsigned int tbt; /* IRQ's that are pending, see sun4m masks. */
53 unsigned int irqs; /* Master IRQ bits. */
55 /* Again, like the above, two these registers are WRITE-ONLY. */
56 unsigned int clear; /* Clear master IRQ's by setting bits here. */
57 unsigned int set; /* Set master IRQ's by setting bits here. */
59 /* This register is both READ and WRITE. */
60 unsigned int undirected_target; /* Which cpu gets undirected irqs. */
63 #define SUN4M_INT_ENABLE 0x80000000
64 #define SUN4M_INT_E14 0x00000080
65 #define SUN4M_INT_E10 0x00080000
67 #define SUN4M_HARD_INT(x) (0x000000001 << (x))
68 #define SUN4M_SOFT_INT(x) (0x000010000 << (x))
70 #define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
71 #define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
72 #define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
73 #define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
74 #define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
75 #define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
76 #define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
77 #define SUN4M_INT_REALTIME 0x00080000 /* system timer */
78 #define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
79 #define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
80 #define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
81 #define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
82 #define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
84 #define SUN4M_INT_SBUS(x) (1 << (x+7))
85 #define SUN4M_INT_VME(x) (1 << (x))
87 typedef struct SCHEDState {
89 uint32_t intreg_pending;
90 uint32_t intreg_enabled;
91 uint32_t intregm_pending;
92 uint32_t intregm_enabled;
95 static SCHEDState *ps;
97 #ifdef DEBUG_IRQ_COUNT
98 static uint64_t irq_count[32];
101 static uint32_t intreg_mem_readl(void *opaque, target_phys_addr_t addr)
103 SCHEDState *s = opaque;
106 saddr = (addr - s->addr) >> 2;
109 return s->intreg_pending;
117 static void intreg_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
119 SCHEDState *s = opaque;
122 saddr = (addr - s->addr) >> 2;
125 s->intreg_pending = val;
128 s->intreg_enabled &= ~val;
131 s->intreg_enabled |= val;
138 static CPUReadMemoryFunc *intreg_mem_read[3] = {
144 static CPUWriteMemoryFunc *intreg_mem_write[3] = {
150 static uint32_t intregm_mem_readl(void *opaque, target_phys_addr_t addr)
152 SCHEDState *s = opaque;
155 saddr = (addr - s->addrg) >> 2;
158 return s->intregm_pending;
161 return s->intregm_enabled;
169 static void intregm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
171 SCHEDState *s = opaque;
174 saddr = (addr - s->addrg) >> 2;
177 s->intregm_pending = val;
180 s->intregm_enabled = val;
183 s->intregm_enabled &= ~val;
186 s->intregm_enabled |= val;
193 static CPUReadMemoryFunc *intregm_mem_read[3] = {
199 static CPUWriteMemoryFunc *intregm_mem_write[3] = {
207 term_printf("per-cpu: pending 0x%08x, enabled 0x%08x\n", ps->intreg_pending, ps->intreg_enabled);
208 term_printf("master: pending 0x%08x, enabled 0x%08x\n", ps->intregm_pending, ps->intregm_enabled);
213 #ifndef DEBUG_IRQ_COUNT
214 term_printf("irq statistic code not compiled.\n");
219 term_printf("IRQ statistics:\n");
220 for (i = 0; i < 32; i++) {
221 count = irq_count[i];
223 term_printf("%2d: %lld\n", i, count);
228 static const unsigned int intr_to_mask[16] = {
229 0, 0, 0, 0, 0, 0, SUN4M_INT_ETHERNET, 0,
230 0, 0, 0, 0, 0, 0, 0, 0,
233 void pic_set_irq(int irq, int level)
236 unsigned int mask = intr_to_mask[irq];
237 ps->intreg_pending |= 1 << irq;
238 if (ps->intregm_enabled & mask) {
239 cpu_single_env->interrupt_index = irq;
240 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
243 #ifdef DEBUG_IRQ_COUNT
249 void sched_init(uint32_t addr, uint32_t addrg)
251 int intreg_io_memory, intregm_io_memory;
254 s = qemu_mallocz(sizeof(SCHEDState));
260 intreg_io_memory = cpu_register_io_memory(0, intreg_mem_read, intreg_mem_write, s);
261 cpu_register_physical_memory(addr, 3, intreg_io_memory);
263 intregm_io_memory = cpu_register_io_memory(0, intregm_mem_read, intregm_mem_write, s);
264 cpu_register_physical_memory(addrg, 5, intregm_io_memory);