2 * QEMU Xilinx OPB Interrupt Controller.
4 * Copyright (c) 2009 Edgar E. Iglesias.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
45 /* Configuration reg chosen at synthesis-time. QEMU populates
46 the bits at board-setup. */
47 uint32_t c_kind_of_intr;
49 /* Runtime control registers. */
53 static void update_irq(struct xlx_pic *p)
56 /* Update the pending register. */
57 p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER];
59 /* Update the vector register. */
60 for (i = 0; i < 32; i++) {
61 if (p->regs[R_IPR] & (1 << i))
68 if ((p->regs[R_MER] & 1) && p->regs[R_IPR]) {
69 qemu_irq_raise(p->parent_irq);
71 qemu_irq_lower(p->parent_irq);
75 static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
77 struct xlx_pic *p = opaque;
84 if (addr < ARRAY_SIZE(p->regs))
89 D(printf("%s %x=%x\n", __func__, addr * 4, r));
94 pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
96 struct xlx_pic *p = opaque;
99 D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
103 p->regs[R_ISR] &= ~value; /* ACK. */
106 p->regs[R_IER] |= value; /* Atomic set ie. */
109 p->regs[R_IER] &= ~value; /* Atomic clear ie. */
112 if (addr < ARRAY_SIZE(p->regs))
113 p->regs[addr] = value;
119 static CPUReadMemoryFunc *pic_read[] = {
124 static CPUWriteMemoryFunc *pic_write[] = {
129 static void irq_handler(void *opaque, int irq, int level)
131 struct xlx_pic *p = opaque;
133 if (!(p->regs[R_MER] & 2)) {
134 qemu_irq_lower(p->parent_irq);
138 /* Update source flops. Don't clear unless level triggered.
139 Edge triggered interrupts only go away when explicitely acked to
140 the interrupt controller. */
141 if (!(p->c_kind_of_intr & (1 << irq)) || level) {
142 p->regs[R_ISR] &= ~(1 << irq);
143 p->regs[R_ISR] |= (level << irq);
148 static void xilinx_intc_init(SysBusDevice *dev)
150 struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev);
153 p->c_kind_of_intr = qdev_get_prop_int(&dev->qdev, "kind-of-intr", 0);
154 qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
155 sysbus_init_irq(dev, &p->parent_irq);
157 pic_regs = cpu_register_io_memory(0, pic_read, pic_write, p);
158 sysbus_init_mmio(dev, R_MAX * 4, pic_regs);
161 static void xilinx_intc_register(void)
163 sysbus_register_dev("xilinx,intc", sizeof (struct xlx_pic),
167 device_init(xilinx_intc_register)