vcs.maemo.org Git - qemu/blob - hw/omap_clk.c

   1 /*
   2  * OMAP clocks.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, write to the Free Software Foundation, Inc.,
  20  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  21  */
  22 #include "hw.h"
  23 #include "omap.h"
  24
  25 struct clk {
  26     const char *name;
  27     const char *alias;
  28     struct clk *parent;
  29     struct clk *child1;
  30     struct clk *sibling;
  31 #define ALWAYS_ENABLED          (1 << 0)
  32 #define CLOCK_IN_OMAP310        (1 << 10)
  33 #define CLOCK_IN_OMAP730        (1 << 11)
  34 #define CLOCK_IN_OMAP1510       (1 << 12)
  35 #define CLOCK_IN_OMAP16XX       (1 << 13)
  36 #define CLOCK_IN_OMAP242X       (1 << 14)
  37 #define CLOCK_IN_OMAP243X       (1 << 15)
  38 #define CLOCK_IN_OMAP343X       (1 << 16)
  39 #define CLOCK_IN_OMAP3XXX   (1 << 17)
  40     uint32_t flags;
  41     int id;
  42
  43     int running;                /* Is currently ticking */
  44     int enabled;                /* Is enabled, regardless of its input clk */
  45     unsigned long rate;         /* Current rate (if .running) */
  46     unsigned int divisor;       /* Rate relative to input (if .enabled) */
  47     unsigned int multiplier;    /* Rate relative to input (if .enabled) */
  48     qemu_irq users[16];         /* Who to notify on change */
  49     int usecount;               /* Automatically idle when unused */
  50 };
  51
  52 static struct clk xtal_osc12m = {
  53     .name       = "xtal_osc_12m",
  54     .rate       = 12000000,
  55     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  56 };
  57
  58 static struct clk xtal_osc32k = {
  59     .name       = "xtal_osc_32k",
  60     .rate       = 32768,
  61     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  62             CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
  63 };
  64
  65 static struct clk ck_ref = {
  66     .name       = "ck_ref",
  67     .alias      = "clkin",
  68     .parent     = &xtal_osc12m,
  69     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  70             ALWAYS_ENABLED,
  71 };
  72
  73 /* If a dpll is disabled it becomes a bypass, child clocks don't stop */
  74 static struct clk dpll1 = {
  75     .name       = "dpll1",
  76     .parent     = &ck_ref,
  77     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  78             ALWAYS_ENABLED,
  79 };
  80
  81 static struct clk dpll2 = {
  82     .name       = "dpll2",
  83     .parent     = &ck_ref,
  84     .flags      = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
  85 };
  86
  87 static struct clk dpll3 = {
  88     .name       = "dpll3",
  89     .parent     = &ck_ref,
  90     .flags      = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
  91 };
  92
  93 static struct clk dpll4 = {
  94     .name       = "dpll4",
  95     .parent     = &ck_ref,
  96     .multiplier = 4,
  97     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  98 };
  99
 100 static struct clk apll = {
 101     .name       = "apll",
 102     .parent     = &ck_ref,
 103     .multiplier = 48,
 104     .divisor    = 12,
 105     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
 106 };
 107
 108 static struct clk ck_48m = {
 109     .name       = "ck_48m",
 110     .parent     = &dpll4,       /* either dpll4 or apll */
 111     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
 112 };
 113
 114 static struct clk ck_dpll1out = {
 115     .name       = "ck_dpll1out",
 116     .parent     = &dpll1,
 117     .flags      = CLOCK_IN_OMAP16XX,
 118 };
 119
 120 static struct clk sossi_ck = {
 121     .name       = "ck_sossi",
 122     .parent     = &ck_dpll1out,
 123     .flags      = CLOCK_IN_OMAP16XX,
 124 };
 125
 126 static struct clk clkm1 = {
 127     .name       = "clkm1",
 128     .alias      = "ck_gen1",
 129     .parent     = &dpll1,
 130     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
 131             ALWAYS_ENABLED,
 132 };
 133
 134 static struct clk clkm2 = {
 135     .name       = "clkm2",
 136     .alias      = "ck_gen2",
 137     .parent     = &dpll1,
 138     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
 139             ALWAYS_ENABLED,
 140 };
 141
 142 static struct clk clkm3 = {
 143     .name       = "clkm3",
 144     .alias      = "ck_gen3",
 145     .parent     = &dpll1,       /* either dpll1 or ck_ref */
 146     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
 147             ALWAYS_ENABLED,
 148 };
 149
 150 static struct clk arm_ck = {
 151     .name       = "arm_ck",
 152     .alias      = "mpu_ck",
 153     .parent     = &clkm1,
 154     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
 155             ALWAYS_ENABLED,
 156 };
 157
 158 static struct clk armper_ck = {
 159     .name       = "armper_ck",
 160     .alias      = "mpuper_ck",
 161     .parent     = &clkm1,
 162     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
 163 };
 164
 165 static struct clk arm_gpio_ck = {
 166     .name       = "arm_gpio_ck",
 167     .alias      = "mpu_gpio_ck",
 168     .parent     = &clkm1,
 169     .divisor    = 1,
 170     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 171 };
 172
 173 static struct clk armxor_ck = {
 174     .name       = "armxor_ck",
 175     .alias      = "mpuxor_ck",
 176     .parent     = &ck_ref,
 177     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
 178 };
 179
 180 static struct clk armtim_ck = {
 181     .name       = "armtim_ck",
 182     .alias      = "mputim_ck",
 183     .parent     = &ck_ref,      /* either CLKIN or DPLL1 */
 184     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
 185 };
 186
 187 static struct clk armwdt_ck = {
 188     .name       = "armwdt_ck",
 189     .alias      = "mpuwd_ck",
 190     .parent     = &clkm1,
 191     .divisor    = 14,
 192     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
 193             ALWAYS_ENABLED,
 194 };
 195
 196 static struct clk arminth_ck16xx = {
 197     .name       = "arminth_ck",
 198     .parent     = &arm_ck,
 199     .flags      = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 200     /* Note: On 16xx the frequency can be divided by 2 by programming
 201      * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 202      *
 203      * 1510 version is in TC clocks.
 204      */
 205 };
 206
 207 static struct clk dsp_ck = {
 208     .name       = "dsp_ck",
 209     .parent     = &clkm2,
 210     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 211 };
 212
 213 static struct clk dspmmu_ck = {
 214     .name       = "dspmmu_ck",
 215     .parent     = &clkm2,
 216     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 217             ALWAYS_ENABLED,
 218 };
 219
 220 static struct clk dspper_ck = {
 221     .name       = "dspper_ck",
 222     .parent     = &clkm2,
 223     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 224 };
 225
 226 static struct clk dspxor_ck = {
 227     .name       = "dspxor_ck",
 228     .parent     = &ck_ref,
 229     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 230 };
 231
 232 static struct clk dsptim_ck = {
 233     .name       = "dsptim_ck",
 234     .parent     = &ck_ref,
 235     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 236 };
 237
 238 static struct clk tc_ck = {
 239     .name       = "tc_ck",
 240     .parent     = &clkm3,
 241     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 242             CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
 243             ALWAYS_ENABLED,
 244 };
 245
 246 static struct clk arminth_ck15xx = {
 247     .name       = "arminth_ck",
 248     .parent     = &tc_ck,
 249     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 250     /* Note: On 1510 the frequency follows TC_CK
 251      *
 252      * 16xx version is in MPU clocks.
 253      */
 254 };
 255
 256 static struct clk tipb_ck = {
 257     /* No-idle controlled by "tc_ck" */
 258     .name       = "tipb_ck",
 259     .parent     = &tc_ck,
 260     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 261 };
 262
 263 static struct clk l3_ocpi_ck = {
 264     /* No-idle controlled by "tc_ck" */
 265     .name       = "l3_ocpi_ck",
 266     .parent     = &tc_ck,
 267     .flags      = CLOCK_IN_OMAP16XX,
 268 };
 269
 270 static struct clk tc1_ck = {
 271     .name       = "tc1_ck",
 272     .parent     = &tc_ck,
 273     .flags      = CLOCK_IN_OMAP16XX,
 274 };
 275
 276 static struct clk tc2_ck = {
 277     .name       = "tc2_ck",
 278     .parent     = &tc_ck,
 279     .flags      = CLOCK_IN_OMAP16XX,
 280 };
 281
 282 static struct clk dma_ck = {
 283     /* No-idle controlled by "tc_ck" */
 284     .name       = "dma_ck",
 285     .parent     = &tc_ck,
 286     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
 287             ALWAYS_ENABLED,
 288 };
 289
 290 static struct clk dma_lcdfree_ck = {
 291     .name       = "dma_lcdfree_ck",
 292     .parent     = &tc_ck,
 293     .flags      = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 294 };
 295
 296 static struct clk api_ck = {
 297     .name       = "api_ck",
 298     .alias      = "mpui_ck",
 299     .parent     = &tc_ck,
 300     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
 301 };
 302
 303 static struct clk lb_ck = {
 304     .name       = "lb_ck",
 305     .parent     = &tc_ck,
 306     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 307 };
 308
 309 static struct clk lbfree_ck = {
 310     .name       = "lbfree_ck",
 311     .parent     = &tc_ck,
 312     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 313 };
 314
 315 static struct clk hsab_ck = {
 316     .name       = "hsab_ck",
 317     .parent     = &tc_ck,
 318     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 319 };
 320
 321 static struct clk rhea1_ck = {
 322     .name       = "rhea1_ck",
 323     .parent     = &tc_ck,
 324     .flags      = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 325 };
 326
 327 static struct clk rhea2_ck = {
 328     .name       = "rhea2_ck",
 329     .parent     = &tc_ck,
 330     .flags      = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 331 };
 332
 333 static struct clk lcd_ck_16xx = {
 334     .name       = "lcd_ck",
 335     .parent     = &clkm3,
 336     .flags      = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730,
 337 };
 338
 339 static struct clk lcd_ck_1510 = {
 340     .name       = "lcd_ck",
 341     .parent     = &clkm3,
 342     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 343 };
 344
 345 static struct clk uart1_1510 = {
 346     .name       = "uart1_ck",
 347     /* Direct from ULPD, no real parent */
 348     .parent     = &armper_ck,   /* either armper_ck or dpll4 */
 349     .rate       = 12000000,
 350     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 351 };
 352
 353 static struct clk uart1_16xx = {
 354     .name       = "uart1_ck",
 355     /* Direct from ULPD, no real parent */
 356     .parent     = &armper_ck,
 357     .rate       = 48000000,
 358     .flags      = CLOCK_IN_OMAP16XX,
 359 };
 360
 361 static struct clk uart2_ck = {
 362     .name       = "uart2_ck",
 363     /* Direct from ULPD, no real parent */
 364     .parent     = &armper_ck,   /* either armper_ck or dpll4 */
 365     .rate       = 12000000,
 366     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
 367             ALWAYS_ENABLED,
 368 };
 369
 370 static struct clk uart3_1510 = {
 371     .name       = "uart3_ck",
 372     /* Direct from ULPD, no real parent */
 373     .parent     = &armper_ck,   /* either armper_ck or dpll4 */
 374     .rate       = 12000000,
 375     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 376 };
 377
 378 static struct clk uart3_16xx = {
 379     .name       = "uart3_ck",
 380     /* Direct from ULPD, no real parent */
 381     .parent     = &armper_ck,
 382     .rate       = 48000000,
 383     .flags      = CLOCK_IN_OMAP16XX,
 384 };
 385
 386 static struct clk usb_clk0 = {  /* 6 MHz output on W4_USB_CLK0 */
 387     .name       = "usb_clk0",
 388     .alias      = "usb.clko",
 389     /* Direct from ULPD, no parent */
 390     .rate       = 6000000,
 391     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
 392 };
 393
 394 static struct clk usb_hhc_ck1510 = {
 395     .name       = "usb_hhc_ck",
 396     /* Direct from ULPD, no parent */
 397     .rate       = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 398     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 399 };
 400
 401 static struct clk usb_hhc_ck16xx = {
 402     .name       = "usb_hhc_ck",
 403     /* Direct from ULPD, no parent */
 404     .rate       = 48000000,
 405     /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 406     .flags      = CLOCK_IN_OMAP16XX,
 407 };
 408
 409 static struct clk usb_w2fc_mclk = {
 410     .name       = "usb_w2fc_mclk",
 411     .alias      = "usb_w2fc_ck",
 412     .parent     = &ck_48m,
 413     .rate       = 48000000,
 414     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 415 };
 416
 417 static struct clk mclk_1510 = {
 418     .name       = "mclk",
 419     /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 420     .rate       = 12000000,
 421     .flags      = CLOCK_IN_OMAP1510,
 422 };
 423
 424 static struct clk bclk_310 = {
 425     .name       = "bt_mclk_out",        /* Alias midi_mclk_out? */
 426     .parent     = &armper_ck,
 427     .flags      = CLOCK_IN_OMAP310,
 428 };
 429
 430 static struct clk mclk_310 = {
 431     .name       = "com_mclk_out",
 432     .parent     = &armper_ck,
 433     .flags      = CLOCK_IN_OMAP310,
 434 };
 435
 436 static struct clk mclk_16xx = {
 437     .name       = "mclk",
 438     /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 439     .flags      = CLOCK_IN_OMAP16XX,
 440 };
 441
 442 static struct clk bclk_1510 = {
 443     .name       = "bclk",
 444     /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 445     .rate       = 12000000,
 446     .flags      = CLOCK_IN_OMAP1510,
 447 };
 448
 449 static struct clk bclk_16xx = {
 450     .name       = "bclk",
 451     /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 452     .flags      = CLOCK_IN_OMAP16XX,
 453 };
 454
 455 static struct clk mmc1_ck = {
 456     .name       = "mmc_ck",
 457     .id         = 1,
 458     /* Functional clock is direct from ULPD, interface clock is ARMPER */
 459     .parent     = &armper_ck,   /* either armper_ck or dpll4 */
 460     .rate       = 48000000,
 461     .flags      = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
 462 };
 463
 464 static struct clk mmc2_ck = {
 465     .name       = "mmc_ck",
 466     .id         = 2,
 467     /* Functional clock is direct from ULPD, interface clock is ARMPER */
 468     .parent     = &armper_ck,
 469     .rate       = 48000000,
 470     .flags      = CLOCK_IN_OMAP16XX,
 471 };
 472
 473 static struct clk cam_mclk = {
 474     .name       = "cam.mclk",
 475     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 476     .rate       = 12000000,
 477 };
 478
 479 static struct clk cam_exclk = {
 480     .name       = "cam.exclk",
 481     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 482     /* Either 12M from cam.mclk or 48M from dpll4 */
 483     .parent     = &cam_mclk,
 484 };
 485
 486 static struct clk cam_lclk = {
 487     .name       = "cam.lclk",
 488     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 489 };
 490
 491 static struct clk i2c_fck = {
 492     .name       = "i2c_fck",
 493     .id         = 1,
 494     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 495             ALWAYS_ENABLED,
 496     .parent     = &armxor_ck,
 497 };
 498
 499 static struct clk i2c_ick = {
 500     .name       = "i2c_ick",
 501     .id         = 1,
 502     .flags      = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 503     .parent     = &armper_ck,
 504 };
 505
 506 static struct clk clk32k = {
 507     .name       = "clk32-kHz",
 508     .flags      = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 509             CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
 510     .parent     = &xtal_osc32k,
 511 };
 512
 513 static struct clk ref_clk = {
 514     .name       = "ref_clk",
 515     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
 516     .rate       = 12000000,     /* 12 MHz or 13 MHz or 19.2 MHz */
 517     /*.parent   = sys.xtalin */
 518 };
 519
 520 static struct clk apll_96m = {
 521     .name       = "apll_96m",
 522     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
 523     .rate       = 96000000,
 524     /*.parent   = ref_clk */
 525 };
 526
 527 static struct clk apll_54m = {
 528     .name       = "apll_54m",
 529     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
 530     .rate       = 54000000,
 531     /*.parent   = ref_clk */
 532 };
 533
 534 static struct clk sys_clk = {
 535     .name       = "sys_clk",
 536     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
 537     .rate       = 32768,
 538     /*.parent   = sys.xtalin */
 539 };
 540
 541 static struct clk sleep_clk = {
 542     .name       = "sleep_clk",
 543     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
 544     .rate       = 32768,
 545     /*.parent   = sys.xtalin */
 546 };
 547
 548 static struct clk dpll_ck = {
 549     .name       = "dpll",
 550     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
 551     .parent     = &ref_clk,
 552 };
 553
 554 static struct clk dpll_x2_ck = {
 555     .name       = "dpll_x2",
 556     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
 557     .parent     = &ref_clk,
 558 };
 559
 560 static struct clk wdt1_sys_clk = {
 561     .name       = "wdt1_sys_clk",
 562     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
 563     .rate       = 32768,
 564     /*.parent   = sys.xtalin */
 565 };
 566
 567 static struct clk func_96m_clk = {
 568     .name       = "func_96m_clk",
 569     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 570     .divisor    = 1,
 571     .parent     = &apll_96m,
 572 };
 573
 574 static struct clk func_48m_clk = {
 575     .name       = "func_48m_clk",
 576     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 577     .divisor    = 2,
 578     .parent     = &apll_96m,
 579 };
 580
 581 static struct clk func_12m_clk = {
 582     .name       = "func_12m_clk",
 583     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 584     .divisor    = 8,
 585     .parent     = &apll_96m,
 586 };
 587
 588 static struct clk func_54m_clk = {
 589     .name       = "func_54m_clk",
 590     .flags      = CLOCK_IN_OMAP242X,
 591     .divisor    = 1,
 592     .parent     = &apll_54m,
 593 };
 594
 595 static struct clk sys_clkout = {
 596     .name       = "clkout",
 597     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 598     .parent     = &sys_clk,
 599 };
 600
 601 static struct clk sys_clkout2 = {
 602     .name       = "clkout2",
 603     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 604     .parent     = &sys_clk,
 605 };
 606
 607 static struct clk core_clk = {
 608     .name       = "core_clk",
 609     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 610     .parent     = &dpll_x2_ck,  /* Switchable between dpll_ck and clk32k */
 611 };
 612
 613 static struct clk l3_clk = {
 614     .name       = "l3_clk",
 615     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 616     .parent     = &core_clk,
 617 };
 618
 619 static struct clk core_l4_iclk = {
 620     .name       = "core_l4_iclk",
 621     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 622     .parent     = &l3_clk,
 623 };
 624
 625 static struct clk wu_l4_iclk = {
 626     .name       = "wu_l4_iclk",
 627     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 628     .parent     = &l3_clk,
 629 };
 630
 631 static struct clk core_l3_iclk = {
 632     .name       = "core_l3_iclk",
 633     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 634     .parent     = &core_clk,
 635 };
 636
 637 static struct clk core_l4_usb_clk = {
 638     .name       = "core_l4_usb_clk",
 639     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 640     .parent     = &l3_clk,
 641 };
 642
 643 static struct clk wu_gpt1_clk = {
 644     .name       = "wu_gpt1_clk",
 645     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 646     .parent     = &sys_clk,
 647 };
 648
 649 static struct clk wu_32k_clk = {
 650     .name       = "wu_32k_clk",
 651     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 652     .parent     = &sys_clk,
 653 };
 654
 655 static struct clk uart1_fclk = {
 656     .name       = "uart1_fclk",
 657     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 658     .parent     = &func_48m_clk,
 659 };
 660
 661 static struct clk uart1_iclk = {
 662     .name       = "uart1_iclk",
 663     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 664     .parent     = &core_l4_iclk,
 665 };
 666
 667 static struct clk uart2_fclk = {
 668     .name       = "uart2_fclk",
 669     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 670     .parent     = &func_48m_clk,
 671 };
 672
 673 static struct clk uart2_iclk = {
 674     .name       = "uart2_iclk",
 675     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 676     .parent     = &core_l4_iclk,
 677 };
 678
 679 static struct clk uart3_fclk = {
 680     .name       = "uart3_fclk",
 681     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 682     .parent     = &func_48m_clk,
 683 };
 684
 685 static struct clk uart3_iclk = {
 686     .name       = "uart3_iclk",
 687     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 688     .parent     = &core_l4_iclk,
 689 };
 690
 691 static struct clk mpu_fclk = {
 692     .name       = "mpu_fclk",
 693     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 694     .parent     = &core_clk,
 695 };
 696
 697 static struct clk mpu_iclk = {
 698     .name       = "mpu_iclk",
 699     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 700     .parent     = &core_clk,
 701 };
 702
 703 static struct clk int_m_fclk = {
 704     .name       = "int_m_fclk",
 705     .alias      = "mpu_intc_fclk",
 706     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 707     .parent     = &core_clk,
 708 };
 709
 710 static struct clk int_m_iclk = {
 711     .name       = "int_m_iclk",
 712     .alias      = "mpu_intc_iclk",
 713     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 714     .parent     = &core_clk,
 715 };
 716
 717 static struct clk core_gpt2_clk = {
 718     .name       = "core_gpt2_clk",
 719     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 720     .parent     = &sys_clk,
 721 };
 722
 723 static struct clk core_gpt3_clk = {
 724     .name       = "core_gpt3_clk",
 725     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 726     .parent     = &sys_clk,
 727 };
 728
 729 static struct clk core_gpt4_clk = {
 730     .name       = "core_gpt4_clk",
 731     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 732     .parent     = &sys_clk,
 733 };
 734
 735 static struct clk core_gpt5_clk = {
 736     .name       = "core_gpt5_clk",
 737     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 738     .parent     = &sys_clk,
 739 };
 740
 741 static struct clk core_gpt6_clk = {
 742     .name       = "core_gpt6_clk",
 743     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 744     .parent     = &sys_clk,
 745 };
 746
 747 static struct clk core_gpt7_clk = {
 748     .name       = "core_gpt7_clk",
 749     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 750     .parent     = &sys_clk,
 751 };
 752
 753 static struct clk core_gpt8_clk = {
 754     .name       = "core_gpt8_clk",
 755     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 756     .parent     = &sys_clk,
 757 };
 758
 759 static struct clk core_gpt9_clk = {
 760     .name       = "core_gpt9_clk",
 761     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 762     .parent     = &sys_clk,
 763 };
 764
 765 static struct clk core_gpt10_clk = {
 766     .name       = "core_gpt10_clk",
 767     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 768     .parent     = &sys_clk,
 769 };
 770
 771 static struct clk core_gpt11_clk = {
 772     .name       = "core_gpt11_clk",
 773     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 774     .parent     = &sys_clk,
 775 };
 776
 777 static struct clk core_gpt12_clk = {
 778     .name       = "core_gpt12_clk",
 779     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 780     .parent     = &sys_clk,
 781 };
 782
 783 static struct clk mcbsp1_clk = {
 784     .name       = "mcbsp1_cg",
 785     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 786     .divisor    = 2,
 787     .parent     = &func_96m_clk,
 788 };
 789
 790 static struct clk mcbsp2_clk = {
 791     .name       = "mcbsp2_cg",
 792     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 793     .divisor    = 2,
 794     .parent     = &func_96m_clk,
 795 };
 796
 797 static struct clk emul_clk = {
 798     .name       = "emul_ck",
 799     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 800     .parent     = &func_54m_clk,
 801 };
 802
 803 static struct clk sdma_fclk = {
 804     .name       = "sdma_fclk",
 805     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 806     .parent     = &l3_clk,
 807 };
 808
 809 static struct clk sdma_iclk = {
 810     .name       = "sdma_iclk",
 811     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 812     .parent     = &core_l3_iclk, /* core_l4_iclk for the configuration port */
 813 };
 814
 815 static struct clk i2c1_fclk = {
 816     .name       = "i2c1.fclk",
 817     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 818     .parent     = &func_12m_clk,
 819     .divisor    = 1,
 820 };
 821
 822 static struct clk i2c1_iclk = {
 823     .name       = "i2c1.iclk",
 824     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 825     .parent     = &core_l4_iclk,
 826 };
 827
 828 static struct clk i2c2_fclk = {
 829     .name       = "i2c2.fclk",
 830     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 831     .parent     = &func_12m_clk,
 832     .divisor    = 1,
 833 };
 834
 835 static struct clk i2c2_iclk = {
 836     .name       = "i2c2.iclk",
 837     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 838     .parent     = &core_l4_iclk,
 839 };
 840
 841 static struct clk gpio_dbclk[4] = {
 842     {
 843         .name   = "gpio1_dbclk",
 844         .flags  = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 845         .parent = &wu_32k_clk,
 846     }, {
 847         .name   = "gpio2_dbclk",
 848         .flags  = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 849         .parent = &wu_32k_clk,
 850     }, {
 851         .name   = "gpio3_dbclk",
 852         .flags  = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 853         .parent = &wu_32k_clk,
 854     }, {
 855         .name   = "gpio4_dbclk",
 856         .flags  = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 857         .parent = &wu_32k_clk,
 858     },
 859 };
 860
 861 static struct clk gpio_iclk = {
 862     .name       = "gpio_iclk",
 863     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 864     .parent     = &wu_l4_iclk,
 865 };
 866
 867 static struct clk mmc_fck = {
 868     .name       = "mmc_fclk",
 869     .flags      = CLOCK_IN_OMAP242X,
 870     .parent     = &func_96m_clk,
 871 };
 872
 873 static struct clk mmc_ick = {
 874     .name       = "mmc_iclk",
 875     .flags      = CLOCK_IN_OMAP242X,
 876     .parent     = &core_l4_iclk,
 877 };
 878
 879 static struct clk spi_fclk[3] = {
 880     {
 881         .name   = "spi1_fclk",
 882         .flags  = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 883         .parent = &func_48m_clk,
 884     }, {
 885         .name   = "spi2_fclk",
 886         .flags  = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 887         .parent = &func_48m_clk,
 888     }, {
 889         .name   = "spi3_fclk",
 890         .flags  = CLOCK_IN_OMAP243X,
 891         .parent = &func_48m_clk,
 892     },
 893 };
 894
 895 static struct clk dss_clk[2] = {
 896     {
 897         .name   = "dss_clk1",
 898         .flags  = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 899         .parent = &core_clk,
 900     }, {
 901         .name   = "dss_clk2",
 902         .flags  = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 903         .parent = &sys_clk,
 904     },
 905 };
 906
 907 static struct clk dss_54m_clk = {
 908     .name       = "dss_54m_clk",
 909     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 910     .parent     = &func_54m_clk,
 911 };
 912
 913 static struct clk dss_l3_iclk = {
 914     .name       = "dss_l3_iclk",
 915     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 916     .parent     = &core_l3_iclk,
 917 };
 918
 919 static struct clk dss_l4_iclk = {
 920     .name       = "dss_l4_iclk",
 921     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 922     .parent     = &core_l4_iclk,
 923 };
 924
 925 static struct clk spi_iclk[3] = {
 926     {
 927         .name   = "spi1_iclk",
 928         .flags  = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 929         .parent = &core_l4_iclk,
 930     }, {
 931         .name   = "spi2_iclk",
 932         .flags  = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 933         .parent = &core_l4_iclk,
 934     }, {
 935         .name   = "spi3_iclk",
 936         .flags  = CLOCK_IN_OMAP243X,
 937         .parent = &core_l4_iclk,
 938     },
 939 };
 940
 941 static struct clk omapctrl_clk = {
 942     .name       = "omapctrl_iclk",
 943     .flags      = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 944     /* XXX Should be in WKUP domain */
 945     .parent     = &core_l4_iclk,
 946 };
 947
 948 /* OMAP3 Clocks */
 949
 950 static struct clk omap3_sys_32k = {
 951     .name       = "omap3_sys_32k",
 952     .rate       = 32768,
 953     .flags      = CLOCK_IN_OMAP3XXX  | ALWAYS_ENABLED,
 954 };
 955
 956 static struct clk omap3_osc_sys_clk12 = {
 957     .name       = "omap3_osc_sys_clk12",
 958     .rate       = 12000000,
 959     .flags      = CLOCK_IN_OMAP3XXX  | ALWAYS_ENABLED,
 960 };
 961
 962 static struct clk omap3_osc_sys_clk13 = {
 963     .name       = "omap3_osc_sys_clk13",
 964     .rate       = 13000000,
 965     .flags      = CLOCK_IN_OMAP3XXX  | ALWAYS_ENABLED,
 966 };
 967
 968 static struct clk omap3_osc_sys_clk168 = {
 969     .name       = "omap3_osc_sys_clk168",
 970     .rate       = 16800000,
 971     .flags      = CLOCK_IN_OMAP3XXX  | ALWAYS_ENABLED,
 972 };
 973
 974 static struct clk omap3_osc_sys_clk192 = {
 975     .name       = "omap3_osc_sys_clk192",
 976     .rate       = 19200000,
 977     .flags      = CLOCK_IN_OMAP3XXX  | ALWAYS_ENABLED,
 978 };
 979
 980 static struct clk omap3_osc_sys_clk26 = {
 981     .name       = "omap3_osc_sys_clk26",
 982     .rate       = 26000000,
 983     .flags      = CLOCK_IN_OMAP3XXX  | ALWAYS_ENABLED,
 984 };
 985
 986 static struct clk omap3_osc_sys_clk384 = {
 987     .name       = "omap3_osc_sys_clk384",
 988     .rate       = 38400000,
 989     .flags      = CLOCK_IN_OMAP3XXX  | ALWAYS_ENABLED,
 990 };
 991
 992 /*Is the altclk is enabled in beagle board?*/
 993 static struct clk omap3_sys_altclk = {
 994     .name       = "omap3_sys_altclk",
 995     .rate       = 13000000,
 996     .flags      = CLOCK_IN_OMAP3XXX  ,
 997 };
 998
 999 /*PRM*/
1000 static struct clk omap3_sys_clk = {
1001     .name       = "omap3_sys_clk",
1002     .flags      = CLOCK_IN_OMAP3XXX  | ALWAYS_ENABLED,
1003     .parent = &omap3_osc_sys_clk26,
1004 };
1005
1006 static struct clk omap3_32k_fclk = {
1007     .name       = "omap3_32k_fclk",
1008     .rate       = 32768,
1009     .flags      = CLOCK_IN_OMAP3XXX  | ALWAYS_ENABLED,
1010     .parent = &omap3_sys_32k,
1011 };
1012
1013 /*DPLL3:
1014  *      Input: SYS_CLK
1015  *   Output:
1016  *           DPLL3_M2_CLK  (CORE_CLK)
1017  *           DPLL3_M2*2_CLK   (CORE*2_CLK)
1018  *           EMULE_CORE_ALWON_CLK
1019  */
1020 static struct clk omap3_core_clk = {
1021     .name       = "omap3_core_clk",
1022     .flags      = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
1023     .parent     = &omap3_sys_clk,
1024 };
1025
1026 static struct clk omap3_core2_clk = {
1027     .name       = "omap3_core2_clk",
1028     .flags      = CLOCK_IN_OMAP3XXX ,
1029     .parent     = &omap3_sys_clk,
1030 };
1031
1032 static struct clk omap3_emu_core_alwon_clk = {
1033     .name       = "omap3_emu_core_alwon_clk",
1034     .flags      = CLOCK_IN_OMAP3XXX ,
1035     .parent     = &omap3_sys_clk,
1036 };
1037
1038 /*DPLL1 : it is for MPU
1039  *    Input:
1040  *           reference clock: SYS_CLK
1041  *           bypass clock : CORE_CLK from dpll3
1042  *    Output:
1043  *           MPU_CLK (DPLL_CLK_M2)
1044  */
1045 static struct clk omap3_mpu_clk = {
1046     .name       = "omap3_mpu_clk",
1047     .flags      = CLOCK_IN_OMAP3XXX ,
1048     .parent     = &omap3_core_clk,         /*between sys_clk and core_clk*/
1049 };
1050
1051 /*DPLL2: it is for iva2*/
1052 static struct clk omap3_iva2_clk = {
1053     .name       = "omap3_iva2_clk",
1054     .flags      = CLOCK_IN_OMAP3XXX ,
1055     .parent     = &omap3_core_clk,         /*between sys_clk and core_clk*/
1056 };
1057
1058 /* DPLL4:
1059  *      INPUT: SYS_CLK
1060  *      OUTPUT:
1061  *              M2: 96M_FCLK
1062  *              M3: TO TV(54M_FCLK)
1063  *              M4: DSS1_ALWON_CLK
1064  *              M5: CAM_CLK
1065  *              M6: EMUL_PER_ALWON_CLK
1066  */
1067 static struct clk omap3_96m_fclk = {
1068     .name       = "omap3_96m_fclk",
1069     .flags      = CLOCK_IN_OMAP3XXX ,
1070     .parent     = &omap3_sys_clk,
1071 };
1072
1073 static struct clk omap3_54m_fclk = {
1074     .name       = "omap3_54m_fclk",
1075     .flags      = CLOCK_IN_OMAP3XXX,
1076     .parent     = &omap3_sys_clk,
1077 };
1078
1079 static struct clk omap3_dss1_alwon_fclk = {
1080     .name       = "omap3_dss1_alwon_fclk",
1081     .flags      = CLOCK_IN_OMAP3XXX ,
1082     .parent     = &omap3_sys_clk,
1083 };
1084
1085 static struct clk omap3_cam_mclk = {
1086     .name       = "omap3_cam_mclk",
1087     .flags      = CLOCK_IN_OMAP3XXX ,
1088     .parent     = &omap3_sys_clk,
1089 };
1090 static struct clk omap3_per_alwon_clk = {
1091     .name       = "omap3_per_alwon_clk",
1092     .flags      = CLOCK_IN_OMAP3XXX ,
1093     .parent     = &omap3_sys_clk,
1094 };
1095
1096 /* DPLL5:
1097  *      INPUT: SYS_CLK
1098  *      OUTPUT:
1099  *              M2: 120M_FCLK
1100  */
1101 static struct clk omap3_120m_fclk = {
1102     .name       = "omap3_120m_fclk",
1103     .flags      = CLOCK_IN_OMAP3XXX ,
1104     .parent     = &omap3_sys_clk,
1105 };
1106
1107 /*CM*/
1108 static struct clk omap3_48m_fclk = {
1109     .name       = "omap3_48m_fclk",
1110     .flags      = CLOCK_IN_OMAP3XXX ,
1111     .parent     = &omap3_96m_fclk, /* omap3_96m_fclk and omap3_sys_altclk */
1112     .divisor = 2,
1113     .multiplier = 1,
1114 };
1115
1116 static struct clk omap3_12m_fclk = {
1117     .name       = "omap3_12m_fclk",
1118     .flags      = CLOCK_IN_OMAP3XXX ,
1119     .parent     = &omap3_96m_fclk, /*omap3_96m_fclk and omap3_sys_altclk */
1120     .divisor = 8,
1121     .multiplier = 1,
1122 };
1123
1124 /*Common interface clock*/
1125 /*   Input: core_clk
1126  *   Output:
1127  *           l3x2_iclk
1128  *           l3_iclk
1129  *           l4_iclk
1130  *           rm_iclk
1131  */
1132 static struct clk omap3_l3x2_iclk = {
1133     .name       = "omap3_l3x2_iclk",
1134     .flags      = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
1135     .parent     = &omap3_core_clk,
1136 };
1137
1138 static struct clk omap3_l3_iclk = {
1139     .name       = "omap3_l3_iclk",
1140     .flags      = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
1141     .parent     = &omap3_core_clk,
1142 };
1143
1144 static struct clk omap3_l4_iclk = {
1145     .name       = "omap3_l4_iclk",
1146     .flags      = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
1147     .parent     = &omap3_l3_iclk,
1148 };
1149 static struct clk omap3_rm_iclk = {
1150     .name       = "omap3_rm_iclk",
1151     .flags      = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
1152     .parent     = &omap3_l4_iclk,
1153 };
1154
1155 /*Core power domain clock*/
1156 /*   Input: cm_sys_clk
1157  *            cm_32k_clk
1158  *            120m_fclk
1159  *            96m_fclk
1160  *            48m_fclk
1161  *            12m_fclk
1162  *            l3_iclk
1163  *            l4_iclk
1164  *   Output:
1165  *           gp10_fclk
1166  *           gp11_fclk
1167  *           core_32k_fclk
1168  *           cpefuse_fclk
1169  *           core_120M_fclk
1170  *           usbttl_sap_fclk
1171  *           core_96m_fclk
1172  *           core_48m_flck
1173  *           core_12m_fclk
1174  *           core_l3_iclk
1175  *           security_l3_iclk
1176  *           core_l4_iclk
1177  *           security_l4_iclk2
1178  */
1179 static struct clk omap3_gp10_fclk = {
1180     .name       = "omap3_gp10_fclk",
1181     .flags      = CLOCK_IN_OMAP3XXX,
1182     .parent     = &omap3_32k_fclk,   /*omap3_32k_fclk and omap3_sys_clk*/
1183 };
1184
1185 static struct clk omap3_gp11_fclk = {
1186     .name       = "omap3_gp11_fclk",
1187     .flags      = CLOCK_IN_OMAP3XXX,
1188     .parent     = &omap3_32k_fclk,   /*omap3_32k_fclk and omap3_sys_clk*/
1189 };
1190
1191 static struct clk omap3_core_32k_fclk = {
1192     .name       = "omap3_core_32k_fclk",
1193     .flags      = CLOCK_IN_OMAP3XXX,
1194     .parent     = &omap3_32k_fclk,
1195 };
1196
1197 static struct clk omap3_cpefuse_fclk = {
1198     .name       = "omap3_cpefuse_fclk",
1199     .flags      = CLOCK_IN_OMAP3XXX,
1200     .parent     = &omap3_sys_clk,
1201 };
1202
1203 static struct clk omap3_core_120m_fclk = {
1204     .name       = "omap3_core_120m_fclk",
1205     .flags      = CLOCK_IN_OMAP3XXX,
1206     .parent     = &omap3_120m_fclk,
1207 };
1208
1209 static struct clk omap3_core_96m_fclk = {
1210     .name       = "omap3_core_96m_fclk",
1211     .flags      = CLOCK_IN_OMAP3XXX,
1212     .parent     = &omap3_96m_fclk,
1213 };
1214
1215 static struct clk omap3_core_48m_fclk = {
1216     .name       = "omap3_core_48m_fclk",
1217     .flags      = CLOCK_IN_OMAP3XXX,
1218     .parent     = &omap3_48m_fclk,
1219 };
1220
1221 static struct clk omap3_core_12m_fclk = {
1222     .name       = "omap3_core_12m_fclk",
1223     .flags      = CLOCK_IN_OMAP3XXX,
1224     .parent     = &omap3_12m_fclk,
1225 };
1226
1227 static struct clk omap3_core_l3_iclk = {
1228     .name       = "omap3_core_l3_iclk",
1229     .flags      = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
1230     .parent     = &omap3_l3_iclk,
1231 };
1232
1233 static struct clk omap3_core_l4_iclk = {
1234     .name       = "omap3_core_l4_iclk",
1235     .flags      = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
1236     .parent     = &omap3_l4_iclk,
1237 };
1238
1239 /* CORE_L3 interface clock based clocks */
1240 static struct clk omap3_sdrc_iclk = {
1241     .name       = "omap3_sdrc_iclk",
1242     .flags      = CLOCK_IN_OMAP3XXX ,
1243     .parent     = &omap3_core_l3_iclk,
1244 };
1245
1246
1247 /*WKUP Power Domain*/
1248 static struct clk omap3_wkup_32k_fclk = {
1249     .name       = "omap3_wkup_32k_fclk",
1250     .flags      = CLOCK_IN_OMAP3XXX ,
1251     .parent     = &omap3_32k_fclk,
1252 };
1253
1254 static struct clk omap3_wkup_l4_iclk = {
1255     .name       = "omap3_wkup_l4_iclk",
1256     .flags      = CLOCK_IN_OMAP3XXX,
1257     .enabled = 1,
1258     .parent     = &omap3_sys_clk,
1259 };
1260
1261 static struct clk omap3_gp1_fclk = {
1262     .name       = "omap3_gp1_fclk",
1263     .flags      = CLOCK_IN_OMAP3XXX ,
1264     .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
1265 };
1266
1267 static struct clk omap3_gp12_fclk = {
1268     .name       = "omap3_gp12_fclk",
1269     .flags      = CLOCK_IN_OMAP3XXX ,
1270     .parent     = &omap3_32k_fclk,        /*SECURE_32K_FCLK -> 32-kHz oscillator */
1271 };
1272
1273 /*PER Power Domain clock*/
1274 /*gp2-gp9 timer*/
1275 static struct clk omap3_gp2_fclk = {
1276     .name       = "omap3_gp2_fclk",
1277     .flags      = CLOCK_IN_OMAP3XXX ,
1278     .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
1279 };
1280
1281 static struct clk omap3_gp3_fclk = {
1282     .name       = "omap3_gp3_fclk",
1283     .flags      = CLOCK_IN_OMAP3XXX ,
1284     .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
1285 };
1286
1287 static struct clk omap3_gp4_fclk = {
1288     .name       = "omap3_gp4_fclk",
1289     .flags      = CLOCK_IN_OMAP3XXX ,
1290     .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
1291 };
1292
1293 static struct clk omap3_gp5_fclk = {
1294     .name       = "omap3_gp5_fclk",
1295     .flags      = CLOCK_IN_OMAP3XXX ,
1296     .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
1297 };
1298
1299 static struct clk omap3_gp6_fclk = {
1300     .name       = "omap3_gp6_fclk",
1301     .flags      = CLOCK_IN_OMAP3XXX ,
1302     .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
1303 };
1304
1305 static struct clk omap3_gp7_fclk = {
1306     .name       = "omap3_gp7_fclk",
1307     .flags      = CLOCK_IN_OMAP3XXX ,
1308     .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
1309 };
1310
1311 static struct clk omap3_gp8_fclk = {
1312     .name       = "omap3_gp8_fclk",
1313     .flags      = CLOCK_IN_OMAP3XXX ,
1314     .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
1315 };
1316
1317 static struct clk omap3_gp9_fclk = {
1318     .name       = "omap3_gp9_fclk",
1319     .flags      = CLOCK_IN_OMAP3XXX ,
1320     .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
1321 };
1322
1323 static struct clk omap3_per_96m_fclk = {
1324     .name       = "omap3_per_96m_fclk",
1325     .flags      = CLOCK_IN_OMAP3XXX ,
1326     .parent     = &omap3_96m_fclk,
1327 };
1328
1329 static struct clk omap3_per_48m_fclk = {
1330     .name       = "omap3_per_48m_fclk",
1331     .flags      = CLOCK_IN_OMAP3XXX ,
1332     .parent     = &omap3_48m_fclk,
1333 };
1334
1335 static struct clk omap3_per_l4_iclk = {
1336     .name       = "omap3_per_l4_iclk",
1337     .flags      = CLOCK_IN_OMAP3XXX,
1338     .enabled = 1,
1339     .parent     = &omap3_l4_iclk,
1340 };
1341
1342 /*UART Clocks*/
1343 static struct clk omap3_uart1_fclk = {
1344     .name       = "omap3_uart1_fclk",
1345     .flags      = CLOCK_IN_OMAP3XXX ,
1346     .parent     = &omap3_core_48m_fclk,
1347 };
1348
1349 static struct clk omap3_uart1_iclk = {
1350     .name       = "omap3_uart1_iclk",
1351     .flags      = CLOCK_IN_OMAP3XXX ,
1352     .parent     = &omap3_core_l4_iclk,
1353 };
1354
1355 static struct clk omap3_uart2_fclk = {
1356     .name       = "omap3_uart2_fclk",
1357     .flags      = CLOCK_IN_OMAP3XXX ,
1358     .parent     = &omap3_core_48m_fclk,
1359 };
1360
1361 static struct clk omap3_uart2_iclk = {
1362     .name       = "omap3_uart2_iclk",
1363     .flags      = CLOCK_IN_OMAP3XXX ,
1364     .parent     = &omap3_core_l4_iclk,
1365 };
1366
1367 static struct clk omap3_uart3_fclk = {
1368     .name       = "omap3_uart3_fclk",
1369     .flags      = CLOCK_IN_OMAP3XXX ,
1370     .parent     = &omap3_per_48m_fclk,
1371 };
1372
1373 static struct clk omap3_uart3_iclk = {
1374     .name       = "omap3_uart3_iclk",
1375     .flags      = CLOCK_IN_OMAP3XXX ,
1376     .parent     = &omap3_core_l4_iclk,
1377 };
1378
1379 /*INTC Clock*/
1380 static struct clk omap3_mpu_intc_fclk = {
1381     .name       = "omap3_mpu_intc_fclk",
1382     .flags      = CLOCK_IN_OMAP3XXX ,
1383     .divisor = 2,
1384     .parent     = &omap3_mpu_clk,
1385 };
1386
1387 static struct clk omap3_mpu_intc_iclk = {
1388     .name       = "omap3_mpu_intc_iclk",
1389     .flags      = CLOCK_IN_OMAP3XXX ,
1390     .divisor = 2,
1391     .parent     = &omap3_mpu_clk,
1392 };
1393
1394 /*SDMA clock*/
1395 static struct clk omap3_sdma_fclk = {
1396     .name       = "omap3_sdma_fclk",
1397     .flags      = CLOCK_IN_OMAP3XXX ,
1398     .parent     = &omap3_core_l3_iclk,
1399 };
1400
1401 static struct clk omap3_sdma_iclk = {
1402     .name       = "omap3_sdma_iclk",
1403     .flags      = CLOCK_IN_OMAP3XXX ,
1404     .parent     = &omap3_core_l4_iclk,
1405 };
1406
1407 /*CLKOUT*/
1408 static struct clk omap3_sys_clkout1 = {
1409     .name   = "omap3_sys_clkout1",
1410     .flags  = CLOCK_IN_OMAP3XXX,
1411     .parent = &omap3_osc_sys_clk26, /* same parent as as SYS_CLK */
1412 };
1413
1414 static struct clk omap3_sys_clkout2 = {
1415     .name       = "omap3_sys_clkout2",
1416     .flags      = CLOCK_IN_OMAP3XXX ,
1417     .parent     = &omap3_core_clk,        /*CORE_CLK CM_SYS_CLK CM_96M_FCLK 54 MHz clock*/
1418 };
1419
1420 /*MMC Clock*/
1421 static struct clk omap3_mmc1_fclk = {
1422     .name       = "omap3_mmc1_fclk",
1423     .flags      = CLOCK_IN_OMAP3XXX ,
1424     .parent     = &omap3_per_96m_fclk,
1425 };
1426
1427 static struct clk omap3_mmc1_iclk = {
1428     .name       = "omap3_mmc1_iclk",
1429     .flags      = CLOCK_IN_OMAP3XXX ,
1430     .parent     = &omap3_per_l4_iclk,
1431 };
1432
1433 static struct clk omap3_mmc2_fclk = {
1434     .name       = "omap3_mmc2_fclk",
1435     .flags      = CLOCK_IN_OMAP3XXX ,
1436     .parent     = &omap3_per_96m_fclk,
1437 };
1438
1439 static struct clk omap3_mmc2_iclk = {
1440     .name       = "omap3_mmc2_iclk",
1441     .flags      = CLOCK_IN_OMAP3XXX ,
1442     .parent     = &omap3_per_l4_iclk,
1443 };
1444
1445 static struct clk omap3_mmc3_fclk = {
1446     .name       = "omap3_mmc3_fclk",
1447     .flags      = CLOCK_IN_OMAP3XXX ,
1448     .parent     = &omap3_per_96m_fclk,
1449 };
1450
1451 static struct clk omap3_mmc3_iclk = {
1452     .name       = "omap3_mmc3_iclk",
1453     .flags      = CLOCK_IN_OMAP3XXX ,
1454     .parent     = &omap3_per_l4_iclk,
1455 };
1456
1457 /*I2C Clocls*/
1458 static struct clk omap3_i2c1_fclk = {
1459     .name       = "omap3_i2c1_fclk",
1460     .flags      = CLOCK_IN_OMAP3XXX ,
1461     .parent     = &omap3_per_96m_fclk,
1462 };
1463
1464 static struct clk omap3_i2c1_iclk = {
1465     .name       = "omap3_i2c1_iclk",
1466     .flags      = CLOCK_IN_OMAP3XXX ,
1467     .parent     = &omap3_core_l4_iclk,
1468 };
1469
1470 static struct clk omap3_i2c2_fclk = {
1471     .name       = "omap3_i2c2_fclk",
1472     .flags      = CLOCK_IN_OMAP3XXX ,
1473     .parent     = &omap3_per_96m_fclk,
1474 };
1475
1476 static struct clk omap3_i2c2_iclk = {
1477     .name       = "omap3_i2c2_iclk",
1478     .flags      = CLOCK_IN_OMAP3XXX ,
1479     .parent     = &omap3_core_l4_iclk,
1480 };
1481
1482 static struct clk omap3_i2c3_fclk = {
1483     .name       = "omap3_i2c3_fclk",
1484     .flags      = CLOCK_IN_OMAP3XXX ,
1485     .parent     = &omap3_per_96m_fclk,
1486 };
1487
1488 static struct clk omap3_i2c3_iclk = {
1489     .name       = "omap3_i2c3_iclk",
1490     .flags      = CLOCK_IN_OMAP3XXX ,
1491     .parent     = &omap3_core_l4_iclk,
1492 };
1493
1494 /* SPI clocks */
1495 static struct clk omap3_spi1_fclk = {
1496     .name   = "omap3_spi1_fclk",
1497     .flags  = CLOCK_IN_OMAP3XXX,
1498     .parent = &omap3_core_48m_fclk,
1499 };
1500
1501 static struct clk omap3_spi1_iclk = {
1502     .name   = "omap3_spi1_iclk",
1503     .flags  = CLOCK_IN_OMAP3XXX,
1504     .parent = &omap3_core_l4_iclk,
1505 };
1506
1507 static struct clk omap3_spi2_fclk = {
1508     .name   = "omap3_spi2_fclk",
1509     .flags  = CLOCK_IN_OMAP3XXX,
1510     .parent = &omap3_core_48m_fclk,
1511 };
1512
1513 static struct clk omap3_spi2_iclk = {
1514     .name   = "omap3_spi2_iclk",
1515     .flags  = CLOCK_IN_OMAP3XXX,
1516     .parent = &omap3_core_l4_iclk,
1517 };
1518
1519 static struct clk omap3_spi3_fclk = {
1520     .name   = "omap3_spi3_fclk",
1521     .flags  = CLOCK_IN_OMAP3XXX,
1522     .parent = &omap3_core_48m_fclk,
1523 };
1524
1525 static struct clk omap3_spi3_iclk = {
1526     .name   = "omap3_spi3_iclk",
1527     .flags  = CLOCK_IN_OMAP3XXX,
1528     .parent = &omap3_core_l4_iclk,
1529 };
1530
1531 static struct clk omap3_spi4_fclk = {
1532     .name   = "omap3_spi4_fclk",
1533     .flags  = CLOCK_IN_OMAP3XXX,
1534     .parent = &omap3_core_48m_fclk,
1535 };
1536
1537 static struct clk omap3_spi4_iclk = {
1538     .name   = "omap3_spi4_iclk",
1539     .flags  = CLOCK_IN_OMAP3XXX,
1540     .parent = &omap3_core_l4_iclk,
1541 };
1542
1543
1544 static struct clk *onchip_clks[] = {
1545     /* OMAP 1 */
1546
1547     /* non-ULPD clocks */
1548     &xtal_osc12m,
1549     &xtal_osc32k,
1550     &ck_ref,
1551     &dpll1,
1552     &dpll2,
1553     &dpll3,
1554     &dpll4,
1555     &apll,
1556     &ck_48m,
1557     /* CK_GEN1 clocks */
1558     &clkm1,
1559     &ck_dpll1out,
1560     &sossi_ck,
1561     &arm_ck,
1562     &armper_ck,
1563     &arm_gpio_ck,
1564     &armxor_ck,
1565     &armtim_ck,
1566     &armwdt_ck,
1567     &arminth_ck15xx,  &arminth_ck16xx,
1568     /* CK_GEN2 clocks */
1569     &clkm2,
1570     &dsp_ck,
1571     &dspmmu_ck,
1572     &dspper_ck,
1573     &dspxor_ck,
1574     &dsptim_ck,
1575     /* CK_GEN3 clocks */
1576     &clkm3,
1577     &tc_ck,
1578     &tipb_ck,
1579     &l3_ocpi_ck,
1580     &tc1_ck,
1581     &tc2_ck,
1582     &dma_ck,
1583     &dma_lcdfree_ck,
1584     &api_ck,
1585     &lb_ck,
1586     &lbfree_ck,
1587     &hsab_ck,
1588     &rhea1_ck,
1589     &rhea2_ck,
1590     &lcd_ck_16xx,
1591     &lcd_ck_1510,
1592     /* ULPD clocks */
1593     &uart1_1510,
1594     &uart1_16xx,
1595     &uart2_ck,
1596     &uart3_1510,
1597     &uart3_16xx,
1598     &usb_clk0,
1599     &usb_hhc_ck1510, &usb_hhc_ck16xx,
1600     &mclk_1510,  &mclk_16xx, &mclk_310,
1601     &bclk_1510,  &bclk_16xx, &bclk_310,
1602     &mmc1_ck,
1603     &mmc2_ck,
1604     &cam_mclk,
1605     &cam_exclk,
1606     &cam_lclk,
1607     &clk32k,
1608     &usb_w2fc_mclk,
1609     /* Virtual clocks */
1610     &i2c_fck,
1611     &i2c_ick,
1612
1613     /* OMAP 2 */
1614
1615     &ref_clk,
1616     &apll_96m,
1617     &apll_54m,
1618     &sys_clk,
1619     &sleep_clk,
1620     &dpll_ck,
1621     &dpll_x2_ck,
1622     &wdt1_sys_clk,
1623     &func_96m_clk,
1624     &func_48m_clk,
1625     &func_12m_clk,
1626     &func_54m_clk,
1627     &sys_clkout,
1628     &sys_clkout2,
1629     &core_clk,
1630     &l3_clk,
1631     &core_l4_iclk,
1632     &wu_l4_iclk,
1633     &core_l3_iclk,
1634     &core_l4_usb_clk,
1635     &wu_gpt1_clk,
1636     &wu_32k_clk,
1637     &uart1_fclk,
1638     &uart1_iclk,
1639     &uart2_fclk,
1640     &uart2_iclk,
1641     &uart3_fclk,
1642     &uart3_iclk,
1643     &mpu_fclk,
1644     &mpu_iclk,
1645     &int_m_fclk,
1646     &int_m_iclk,
1647     &core_gpt2_clk,
1648     &core_gpt3_clk,
1649     &core_gpt4_clk,
1650     &core_gpt5_clk,
1651     &core_gpt6_clk,
1652     &core_gpt7_clk,
1653     &core_gpt8_clk,
1654     &core_gpt9_clk,
1655     &core_gpt10_clk,
1656     &core_gpt11_clk,
1657     &core_gpt12_clk,
1658     &mcbsp1_clk,
1659     &mcbsp2_clk,
1660     &emul_clk,
1661     &sdma_fclk,
1662     &sdma_iclk,
1663     &i2c1_fclk,
1664     &i2c1_iclk,
1665     &i2c2_fclk,
1666     &i2c2_iclk,
1667     &gpio_dbclk[0],
1668     &gpio_dbclk[1],
1669     &gpio_dbclk[2],
1670     &gpio_dbclk[3],
1671     &gpio_iclk,
1672     &mmc_fck,
1673     &mmc_ick,
1674     &spi_fclk[0],
1675     &spi_iclk[0],
1676     &spi_fclk[1],
1677     &spi_iclk[1],
1678     &spi_fclk[2],
1679     &spi_iclk[2],
1680     &dss_clk[0],
1681     &dss_clk[1],
1682     &dss_54m_clk,
1683     &dss_l3_iclk,
1684     &dss_l4_iclk,
1685     &omapctrl_clk,
1686
1687     /* OMAP 3*/
1688
1689     &omap3_sys_32k,
1690     &omap3_osc_sys_clk12,
1691     &omap3_osc_sys_clk13,
1692     &omap3_osc_sys_clk168,
1693     &omap3_osc_sys_clk192,
1694     &omap3_osc_sys_clk26,
1695     &omap3_osc_sys_clk384,
1696     &omap3_sys_altclk,
1697     &omap3_sys_clk,
1698     &omap3_32k_fclk,
1699     &omap3_core_clk,
1700     &omap3_core2_clk,
1701     &omap3_emu_core_alwon_clk,
1702     &omap3_mpu_clk,
1703     &omap3_iva2_clk,
1704     &omap3_96m_fclk,
1705     &omap3_54m_fclk,
1706     &omap3_dss1_alwon_fclk,
1707     &omap3_cam_mclk,
1708     &omap3_per_alwon_clk,
1709     &omap3_120m_fclk,
1710     &omap3_48m_fclk,
1711     &omap3_12m_fclk,
1712     &omap3_l3x2_iclk,
1713     &omap3_l3_iclk,
1714     &omap3_l4_iclk,
1715     &omap3_rm_iclk,
1716     &omap3_gp10_fclk,
1717     &omap3_gp11_fclk,
1718     &omap3_core_32k_fclk,
1719     &omap3_cpefuse_fclk,
1720     &omap3_core_120m_fclk,
1721     &omap3_core_96m_fclk,
1722     &omap3_core_48m_fclk,
1723     &omap3_core_12m_fclk,
1724     &omap3_core_l3_iclk,
1725     &omap3_core_l4_iclk,
1726     &omap3_sdrc_iclk,
1727     &omap3_wkup_32k_fclk,
1728     &omap3_wkup_l4_iclk,
1729     &omap3_gp1_fclk,
1730     &omap3_gp12_fclk,
1731     &omap3_gp2_fclk,
1732     &omap3_gp3_fclk,
1733     &omap3_gp4_fclk,
1734     &omap3_gp5_fclk,
1735     &omap3_gp6_fclk,
1736     &omap3_gp7_fclk,
1737     &omap3_gp8_fclk,
1738     &omap3_gp9_fclk,
1739     &omap3_per_96m_fclk,
1740     &omap3_per_48m_fclk,
1741     &omap3_per_l4_iclk,
1742     &omap3_uart1_fclk,
1743     &omap3_uart1_iclk,
1744     &omap3_uart2_fclk,
1745     &omap3_uart2_iclk,
1746     &omap3_uart3_fclk,
1747     &omap3_uart3_iclk,
1748     &omap3_mpu_intc_fclk,
1749     &omap3_mpu_intc_iclk,
1750     &omap3_sdma_fclk,
1751     &omap3_sdma_iclk,
1752     &omap3_sys_clkout1,
1753     &omap3_sys_clkout2,
1754     &omap3_mmc1_fclk,
1755     &omap3_mmc1_iclk,
1756     &omap3_mmc2_fclk,
1757     &omap3_mmc2_iclk,
1758     &omap3_mmc3_fclk,
1759     &omap3_mmc3_iclk,
1760     &omap3_i2c1_fclk,
1761     &omap3_i2c1_iclk,
1762     &omap3_i2c2_fclk,
1763     &omap3_i2c2_iclk,
1764     &omap3_i2c3_fclk,
1765     &omap3_i2c3_iclk,
1766     &omap3_spi1_fclk,
1767     &omap3_spi1_iclk,
1768     &omap3_spi2_fclk,
1769     &omap3_spi2_iclk,
1770     &omap3_spi3_fclk,
1771     &omap3_spi3_iclk,
1772     &omap3_spi4_fclk,
1773     &omap3_spi4_iclk,
1774
1775     0
1776 };
1777
1778 void omap_clk_adduser(struct clk *clk, qemu_irq user)
1779 {
1780     qemu_irq *i;
1781
1782     for (i = clk->users; *i; i ++);
1783     *i = user;
1784 }
1785
1786 struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name)
1787 {
1788     struct clk *i;
1789
1790     for (i = mpu->clks; i->name; i ++)
1791         if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
1792             return i;
1793     hw_error("%s: %s not found\n", __FUNCTION__, name);
1794 }
1795
1796 void omap_clk_get(struct clk *clk)
1797 {
1798     clk->usecount ++;
1799 }
1800
1801 void omap_clk_put(struct clk *clk)
1802 {
1803     if (!(clk->usecount --))
1804         hw_error("%s: %s is not in use\n", __FUNCTION__, clk->name);
1805 }
1806
1807 static void omap_clk_update(struct clk *clk)
1808 {
1809     int parent, running;
1810     qemu_irq *user;
1811     struct clk *i;
1812
1813     if (clk->parent)
1814         parent = clk->parent->running;
1815     else
1816         parent = 1;
1817
1818     running = parent && (clk->enabled ||
1819                     ((clk->flags & ALWAYS_ENABLED) && clk->usecount));
1820     if (clk->running != running) {
1821         clk->running = running;
1822         for (user = clk->users; *user; user ++)
1823             qemu_set_irq(*user, running);
1824         for (i = clk->child1; i; i = i->sibling)
1825             omap_clk_update(i);
1826     }
1827 }
1828
1829 static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate,
1830                 unsigned long int div, unsigned long int mult)
1831 {
1832     struct clk *i;
1833     qemu_irq *user;
1834
1835     clk->rate = muldiv64(rate, mult, div);
1836     if (clk->running)
1837         for (user = clk->users; *user; user ++)
1838             qemu_irq_raise(*user);
1839     for (i = clk->child1; i; i = i->sibling)
1840         omap_clk_rate_update_full(i, rate,
1841                         div * i->divisor, mult * i->multiplier);
1842 }
1843
1844 static void omap_clk_rate_update(struct clk *clk)
1845 {
1846     struct clk *i;
1847     unsigned long int div, mult = div = 1;
1848
1849     for (i = clk; i->parent; i = i->parent) {
1850         div *= i->divisor;
1851         mult *= i->multiplier;
1852     }
1853
1854     omap_clk_rate_update_full(clk, i->rate, div, mult);
1855 }
1856
1857 void omap_clk_reparent(struct clk *clk, struct clk *parent)
1858 {
1859     struct clk **p;
1860
1861     if (clk->parent) {
1862         for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
1863         *p = clk->sibling;
1864     }
1865
1866     clk->parent = parent;
1867     if (parent) {
1868         clk->sibling = parent->child1;
1869         parent->child1 = clk;
1870         omap_clk_update(clk);
1871         omap_clk_rate_update(clk);
1872     } else
1873         clk->sibling = 0;
1874 }
1875
1876 void omap_clk_onoff(struct clk *clk, int on)
1877 {
1878     clk->enabled = on;
1879     omap_clk_update(clk);
1880 }
1881
1882 void omap_clk_canidle(struct clk *clk, int can)
1883 {
1884     if (can)
1885         omap_clk_put(clk);
1886     else
1887         omap_clk_get(clk);
1888 }
1889
1890 void omap_clk_setrate(struct clk *clk, int divide, int multiply)
1891 {
1892     clk->divisor = divide;
1893     clk->multiplier = multiply;
1894     omap_clk_rate_update(clk);
1895 }
1896
1897 int64_t omap_clk_getrate(omap_clk clk)
1898 {
1899     return clk->rate;
1900 }
1901
1902 void omap_clk_init(struct omap_mpu_state_s *mpu)
1903 {
1904     struct clk **i, *j, *k;
1905     int count;
1906     int flag;
1907
1908     if (cpu_is_omap310(mpu))
1909         flag = CLOCK_IN_OMAP310;
1910     else if (cpu_is_omap1510(mpu))
1911         flag = CLOCK_IN_OMAP1510;
1912     else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu))
1913         flag = CLOCK_IN_OMAP242X;
1914     else if (cpu_is_omap2430(mpu))
1915         flag = CLOCK_IN_OMAP243X;
1916     else if (cpu_is_omap3430(mpu))
1917         flag = CLOCK_IN_OMAP243X;
1918     else if (cpu_is_omap3530(mpu))
1919         flag = CLOCK_IN_OMAP3XXX;
1920     else
1921         return;
1922
1923     for (i = onchip_clks, count = 0; *i; i ++)
1924         if ((*i)->flags & flag)
1925             count ++;
1926     mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1));
1927     for (i = onchip_clks, j = mpu->clks; *i; i ++)
1928         if ((*i)->flags & flag) {
1929             memcpy(j, *i, sizeof(struct clk));
1930             for (k = mpu->clks; k < j; k ++)
1931                 if (j->parent && !strcmp(j->parent->name, k->name)) {
1932                     j->parent = k;
1933                     j->sibling = k->child1;
1934                     k->child1 = j;
1935                 } else if (k->parent && !strcmp(k->parent->name, j->name)) {
1936                     k->parent = j;
1937                     k->sibling = j->child1;
1938                     j->child1 = k;
1939                 }
1940             j->divisor = j->divisor ?: 1;
1941             j->multiplier = j->multiplier ?: 1;
1942             j ++;
1943         }
1944     for (j = mpu->clks; count --; j ++) {
1945         omap_clk_update(j);
1946         omap_clk_rate_update(j);
1947     }
1948 }