vcs.maemo.org Git - kernel-power/blob - kernel-power-2.6.28/debian/patches/nokia-20101501+0m5.diff

   1 diff -Nurp kernel-2.6.28-20100903+0m5/arch/arm/mach-omap2/board-rx51-camera.c kernel-2.6.28-20101501+0m5/arch/arm/mach-omap2/board-rx51-camera.c
   2 --- kernel-2.6.28-20100903+0m5/arch/arm/mach-omap2/board-rx51-camera.c  2012-12-16 13:28:34.748315692 +0100
   3 +++ kernel-2.6.28-20101501+0m5/arch/arm/mach-omap2/board-rx51-camera.c  2012-12-16 13:30:14.168314148 +0100
   4 @@ -561,7 +561,7 @@ static int rx51_adp1653_power_on(struct
   5         gpio_set_value(ADP1653_GPIO_ENABLE, 1);
   6
   7         /* Some delay is apparently required. */
   8 -       udelay(20);
   9 +       udelay(400);
  10
  11         return 0;
  12  }
  13 diff -Nurp kernel-2.6.28-20100903+0m5/arch/arm/mach-omap2/pm34xx.c kernel-2.6.28-20101501+0m5/arch/arm/mach-omap2/pm34xx.c
  14 --- kernel-2.6.28-20100903+0m5/arch/arm/mach-omap2/pm34xx.c     2012-12-16 13:29:04.844315224 +0100
  15 +++ kernel-2.6.28-20101501+0m5/arch/arm/mach-omap2/pm34xx.c     2012-12-16 13:30:14.172314148 +0100
  16 @@ -45,6 +45,7 @@
  17  #include <mach/dma.h>
  18  #include <mach/vrfb.h>
  19  #include <mach/ssi.h>
  20 +#include <mach/omap-pm.h>
  21
  22  #include <asm/tlbflush.h>
  23
  24 @@ -102,6 +103,8 @@
  25  #define CONTROL_PADCONF_MCBSP4_DX      0x158
  26  #define CONTROL_PADCONF_UART1_TX       0x14c
  27
  28 +#define VSEL_1200      0x30
  29 +
  30  static u16 ssi_rx_rdy;
  31  static u16 ssi_tx_dat;
  32  static u16 ssi_tx_flag;
  33 @@ -520,6 +523,7 @@ void omap_sram_idle(void)
  34         u32 sdrc_pwr = 0;
  35         int per_state_modified = 0;
  36         int core_saved_state = PWRDM_POWER_ON;
  37 +       static int prev_dpll3_div = 0;
  38
  39         if (!_omap_sram_idle)
  40                 return;
  41 @@ -551,7 +555,7 @@ void omap_sram_idle(void)
  42         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) {
  43                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
  44                 neon_next_state = mpu_next_state;
  45 -               if (neon_next_state == PWRDM_POWER_OFF)
  46 +               if (neon_next_state == PWRDM_POWER_OFF)
  47                         omap3_save_neon_context();
  48         }
  49
  50 @@ -562,6 +566,12 @@ void omap_sram_idle(void)
  51         usb_state = pwrdm_read_pwrst(usb_pwrdm);
  52         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
  53
  54 +       if (dss_state == PWRDM_POWER_ON &&
  55 +               core_next_state < PWRDM_POWER_INACTIVE) {
  56 +               core_next_state = PWRDM_POWER_INACTIVE;
  57 +               pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
  58 +       }
  59 +
  60         /* Check if PER domain can enter OFF or not */
  61         if (per_next_state == PWRDM_POWER_OFF) {
  62                 if ((cm_read_mod_reg(OMAP3430_PER_MOD, CM_IDLEST) &
  63 @@ -679,6 +689,33 @@ void omap_sram_idle(void)
  64                                   OMAP3_PRM_CLKSETUP_OFFSET);
  65         }
  66
  67 +       if (core_next_state < PWRDM_POWER_INACTIVE) {
  68 +               u32 clksel1_pll, v;
  69 +
  70 +               clksel1_pll = cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
  71 +               prev_dpll3_div = clksel1_pll >> 28;
  72 +               if (prev_dpll3_div == 1) {
  73 +                       /* L3 @ 166Mhz */
  74 +                       struct omap_sdrc_params *sdrc_cs0;
  75 +                       struct omap_sdrc_params *sdrc_cs1;
  76 +
  77 +                       omap2_sdrc_get_params(83*1000*1000, &sdrc_cs0, &sdrc_cs1);
  78 +                       /* scale down to 83Mhz, use worst case delay for clock stabilization */
  79 +                       omap3_configure_core_dpll(4, 0, 28, 0, sdrc_cs0->rfr_ctrl, sdrc_cs0->mr, 0, 0);
  80 +
  81 +                       /* increase voltage to 1.2V */
  82 +                       sr_voltagescale_vcbypass(PRCM_VDD2_OPP3, PRCM_VDD2_OPP2, VSEL_1200, l3_opps[3].vsel);
  83 +               } else {
  84 +                       /* L3 @ 83Mhz, increase voltage to 1.2V  */
  85 +                       sr_voltagescale_vcbypass(PRCM_VDD2_OPP3, PRCM_VDD2_OPP2, VSEL_1200, l3_opps[2].vsel);
  86 +               }
  87 +
  88 +               /* enable DPLL3 autoidle */
  89 +               v = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
  90 +               v |= 1;
  91 +               cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
  92 +       }
  93 +
  94         memcpy(save_sdrc_counters, _sdrc_counters, sizeof(save_sdrc_counters));
  95
  96         /*
  97 @@ -701,6 +738,51 @@ void omap_sram_idle(void)
  98         if (neon_next_state == PWRDM_POWER_OFF)
  99                 omap3_restore_neon_context();
 100
 101 +       if (core_next_state < PWRDM_POWER_INACTIVE) {
 102 +               if (pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
 103 +                       u32 clksel1_pll;
 104 +
 105 +                       /* ROM code restored the scratchpad settings. So DPLL3 autoidle is
 106 +                        * disabled and L3 clock is back to the value before entering this function.
 107 +                        * This means we only have to lower the voltage if L3 runs at 83Mhz
 108 +                        */
 109 +                       clksel1_pll = cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
 110 +                       if ((clksel1_pll >> 28) == 2) {
 111 +                               /* restore VDD2 OPP2 voltage */
 112 +                               sr_voltagescale_vcbypass(PRCM_VDD2_OPP2, PRCM_VDD2_OPP3, l3_opps[2].vsel, VSEL_1200);
 113 +                       }
 114 +                       else {
 115 +                               /* restore VDD2 OPP3 voltage */
 116 +                               sr_voltagescale_vcbypass(PRCM_VDD2_OPP2, PRCM_VDD2_OPP3, l3_opps[3].vsel, VSEL_1200);
 117 +                       }
 118 +               }
 119 +               else {
 120 +                       u32 v;
 121 +
 122 +                       /* disable DPLL3 autoidle */
 123 +                       v = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
 124 +                       v &= ~0x7;
 125 +                       cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
 126 +
 127 +                       if (prev_dpll3_div == 1) {
 128 +                               /* restore L3 to 166Mhz */
 129 +                               struct omap_sdrc_params *sdrc_cs0;
 130 +                               struct omap_sdrc_params *sdrc_cs1;
 131 +
 132 +                               omap2_sdrc_get_params(166*1000*1000, &sdrc_cs0, &sdrc_cs1);
 133 +                               /* scale up to 166Mhz, use worst case delay for clock stabilization */
 134 +                               omap3_configure_core_dpll(2, 0, 28, 1, sdrc_cs0->rfr_ctrl, sdrc_cs0->mr, 0, 0);
 135 +
 136 +                               /* restore VDD2 OPP3 voltage */
 137 +                               sr_voltagescale_vcbypass(PRCM_VDD2_OPP2, PRCM_VDD2_OPP3, l3_opps[3].vsel, VSEL_1200);
 138 +                       }
 139 +                       else {
 140 +                               /* restore VDD2 OPP2 voltage */
 141 +                               sr_voltagescale_vcbypass(PRCM_VDD2_OPP2, PRCM_VDD2_OPP3, l3_opps[2].vsel, VSEL_1200);
 142 +                       }
 143 +               }
 144 +       }
 145 +
 146         /* CORE */
 147         if (core_next_state < PWRDM_POWER_ON) {
 148                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 149 @@ -1136,7 +1218,7 @@ static void __init prcm_setup_regs(void)
 150                          MPU_MOD,
 151                          CM_AUTOIDLE2);
 152         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 153 -                        (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 154 +                        (0 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 155                          PLL_MOD,
 156                          CM_AUTOIDLE);
 157         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 158 diff -Nurp kernel-2.6.28-20100903+0m5/arch/arm/mach-omap2/smartreflex.c kernel-2.6.28-20101501+0m5/arch/arm/mach-omap2/smartreflex.c
 159 --- kernel-2.6.28-20100903+0m5/arch/arm/mach-omap2/smartreflex.c        2012-12-16 13:28:45.472315523 +0100
 160 +++ kernel-2.6.28-20101501+0m5/arch/arm/mach-omap2/smartreflex.c        2012-12-16 13:30:17.084314106 +0100
 161 @@ -1004,6 +1004,11 @@ static ssize_t omap_sr_vdd2_autocomp_sto
 162                 return -EINVAL;
 163         }
 164
 165 +       if (value != 0) {
 166 +               pr_warning("VDD2 smartreflex is broken\n");
 167 +               return -EINVAL;
 168 +       }
 169 +
 170         mutex_lock(&dvfs_mutex);
 171
 172         current_vdd2opp_no = resource_get_level("vdd2_opp");
 173 diff -Nurp kernel-2.6.28-20100903+0m5/arch/arm/mach-omap2/ssi.c kernel-2.6.28-20101501+0m5/arch/arm/mach-omap2/ssi.c
 174 --- kernel-2.6.28-20100903+0m5/arch/arm/mach-omap2/ssi.c        2012-12-16 13:28:34.756315692 +0100
 175 +++ kernel-2.6.28-20101501+0m5/arch/arm/mach-omap2/ssi.c        2012-12-16 13:30:14.172314148 +0100
 176 @@ -378,7 +378,7 @@ static void enable_dpll3_autoidle(void)
 177         u32 v;
 178
 179         v = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
 180 -       v |= 1;
 181 +       v |= 0;
 182         cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
 183  }
 184
 185 diff -Nurp kernel-2.6.28-20100903+0m5/drivers/mmc/host/omap_hsmmc.c kernel-2.6.28-20101501+0m5/drivers/mmc/host/omap_hsmmc.c
 186 --- kernel-2.6.28-20100903+0m5/drivers/mmc/host/omap_hsmmc.c    2012-12-16 13:29:04.852315222 +0100
 187 +++ kernel-2.6.28-20101501+0m5/drivers/mmc/host/omap_hsmmc.c    2012-12-16 13:30:14.172314148 +0100
 188 @@ -28,6 +28,7 @@
 189  #include <linux/clk.h>
 190  #include <linux/mmc/host.h>
 191  #include <linux/mmc/core.h>
 192 +#include <linux/mmc/card.h>
 193  #include <linux/io.h>
 194  #include <linux/semaphore.h>
 195  #include <asm/dma.h>
 196 @@ -97,6 +98,8 @@
 197  #define SOFTRESET              (1 << 1)
 198  #define RESETDONE              (1 << 0)
 199
 200 +#define SAMSUNG_MANUF_ID       0x15
 201 +
 202  /*
 203   * FIXME: Most likely all the data using these _DEVID defines should come
 204   * from the platform_data, or implemented in controller and slot specific
 205 @@ -1283,10 +1286,24 @@ static int omap_hsmmc_enabled_to_disable
 206         return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
 207  }
 208
 209 +/* JEDEC specification says the nand core voltage can be shut off while the
 210 +   card is sleeping. Some cards are known not to be JEDEC compatible with
 211 +   this respect */
 212 +static int omap_hsmmc_full_sleep(struct mmc_card *card)
 213 +{
 214 +       if (card->cid.manfid == SAMSUNG_MANUF_ID) {
 215 +               unsigned int gbytes = card->ext_csd.sectors >> (30 - 9);
 216 +               if (gbytes > 24 && gbytes < 48)
 217 +                       return 0;
 218 +       }
 219 +
 220 +       return 1;
 221 +}
 222 +
 223  /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
 224  static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
 225  {
 226 -       int err, new_state;
 227 +       int err, new_state, sleep;
 228
 229         if (!mmc_try_claim_host(host->mmc))
 230                 return 0;
 231 @@ -1304,9 +1321,12 @@ static int omap_hsmmc_disabled_to_sleep(
 232         } else {
 233                 new_state = REGSLEEP;
 234         }
 235 +
 236 +       sleep = omap_hsmmc_full_sleep(host->mmc->card) &&
 237 +               (new_state == CARDSLEEP);
 238         if (mmc_slot(host).set_sleep)
 239                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
 240 -                                        new_state == CARDSLEEP);
 241 +                                       sleep);
 242         /* FIXME: turn off bus power and perhaps interrupts too */
 243         clk_disable(host->fclk);
 244         host->dpm_state = new_state;
 245 @@ -1376,14 +1396,18 @@ static int omap_hsmmc_disabled_to_enable
 246
 247  static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
 248  {
 249 +       int asleep;
 250 +
 251         if (!mmc_try_claim_host(host->mmc))
 252                 return 0;
 253
 254         clk_enable(host->fclk);
 255         omap_hsmmc_context_restore(host);
 256 +       asleep = omap_hsmmc_full_sleep(host->mmc->card) &&
 257 +               (host->dpm_state == CARDSLEEP);
 258         if (mmc_slot(host).set_sleep)
 259                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
 260 -                        host->vdd, host->dpm_state == CARDSLEEP);
 261 +                                       host->vdd, asleep);
 262         if (mmc_card_can_sleep(host->mmc))
 263                 mmc_card_awake(host->mmc);
 264
 265 diff -Nurp kernel-2.6.28-20100903+0m5/drivers/net/wireless/wl12xx/wl1251_main.c kernel-2.6.28-20101501+0m5/drivers/net/wireless/wl12xx/wl1251_main.c
 266 --- kernel-2.6.28-20100903+0m5/drivers/net/wireless/wl12xx/wl1251_main.c        2012-12-16 13:29:16.932315035 +0100
 267 +++ kernel-2.6.28-20101501+0m5/drivers/net/wireless/wl12xx/wl1251_main.c        2012-12-16 13:30:14.172314148 +0100
 268 @@ -1611,6 +1611,7 @@ static int wl1251_hw_scan(struct wl1251
 269         }
 270
 271  out:
 272 +       kfree(trigger);
 273         kfree(params);
 274         return ret;
 275
 276 diff -Nurp kernel-2.6.28-20100903+0m5/drivers/net/wireless/wl12xx/wl1251_spi.c kernel-2.6.28-20101501+0m5/drivers/net/wireless/wl12xx/wl1251_spi.c
 277 --- kernel-2.6.28-20100903+0m5/drivers/net/wireless/wl12xx/wl1251_spi.c 2012-12-16 13:28:34.816315688 +0100
 278 +++ kernel-2.6.28-20101501+0m5/drivers/net/wireless/wl12xx/wl1251_spi.c 2012-12-16 13:30:14.172314148 +0100
 279 @@ -92,6 +92,8 @@ void wl1251_spi_reset(struct wl1251 *wl)
 280         spi_sync(wl->spi, &m);
 281
 282         wl1251_dump(DEBUG_SPI, "spi reset -> ", cmd, WSPI_INIT_CMD_LEN);
 283 +
 284 +       kfree(cmd);
 285  }
 286
 287  void wl1251_spi_init(struct wl1251 *wl)
 288 @@ -146,6 +148,8 @@ void wl1251_spi_init(struct wl1251 *wl)
 289         spi_sync(wl->spi, &m);
 290
 291         wl1251_dump(DEBUG_SPI, "spi init -> ", cmd, WSPI_INIT_CMD_LEN);
 292 +
 293 +       kfree(cmd);
 294  }
 295
 296  /* Set the SPI partitions to access the chip addresses
 297 diff -Nurp kernel-2.6.28-20100903+0m5/net/mac80211/mlme.c kernel-2.6.28-20101501+0m5/net/mac80211/mlme.c
 298 --- kernel-2.6.28-20100903+0m5/net/mac80211/mlme.c      2012-12-16 13:29:04.852315222 +0100
 299 +++ kernel-2.6.28-20101501+0m5/net/mac80211/mlme.c      2012-12-16 13:30:14.172314148 +0100
 300 @@ -1624,6 +1624,7 @@ static int ieee80211_sta_join_ibss(struc
 301                         memcpy(pos, &bss->supp_rates[8], rates);
 302                 }
 303
 304 +               kfree_skb(ifsta->probe_resp);
 305                 ifsta->probe_resp = skb;
 306
 307                 ieee80211_if_config(sdata, IEEE80211_IFCC_BEACON);