vcs.maemo.org Git - kernel-bfs/blob - kernel-power-2.6.28/debian/patches/kexec.diff

   1 --- kernel-maemo-2.6.28.orig/arch/arm/boot/compressed/head.S
   2 +++ kernel-maemo-2.6.28/arch/arm/boot/compressed/head.S
   3 @@ -27,6 +27,14 @@
   4                 .macro  writeb, ch, rb
   5                 mcr     p14, 0, \ch, c0, c5, 0
   6                 .endm
   7 +elif defined(CONFIG_CPU_V7)
   8 +               .macro  loadsp, rb
   9 +               .endm
  10 +               .macro  writeb, ch, rb
  11 +wait:          mrc     p14, 0, pc, c0, c1, 0
  12 +               bcs     wait
  13 +               mcr     p14, 0, \ch, c0, c5, 0
  14 +               .endm
  15  #else
  16                 .macro  loadsp, rb
  17                 .endm
  18 --- kernel-maemo-2.6.28.orig/arch/arm/boot/compressed/misc.c
  19 +++ kernel-maemo-2.6.28/arch/arm/boot/compressed/misc.c
  20 @@ -47,6 +47,17 @@
  21         asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
  22  }
  23
  24 +#elif defined(CONFIG_CPU_V7)
  25 +
  26 +static void icedcc_putc(int ch)
  27 +{
  28 +       asm(
  29 +       "wait:  mrc     p14, 0, pc, c0, c1, 0                   \n\
  30 +               bcs     wait                                    \n\
  31 +               mcr     p14, 0, %0, c0, c5, 0                   "
  32 +       : : "r" (ch));
  33 +}
  34 +
  35  #else
  36
  37  static void icedcc_putc(int ch)
  38 --- kernel-maemo-2.6.28.orig/arch/arm/include/asm/cacheflush.h
  39 +++ kernel-maemo-2.6.28/arch/arm/include/asm/cacheflush.h
  40 @@ -138,16 +138,16 @@
  41   *     Please note that the implementation of these, and the required
  42   *     effects are cache-type (VIVT/VIPT/PIPT) specific.
  43   *
  44 - *     flush_cache_kern_all()
  45 + *     flush_kern_all()
  46   *
  47   *             Unconditionally clean and invalidate the entire cache.
  48   *
  49 - *     flush_cache_user_mm(mm)
  50 + *     flush_user_all()
  51   *
  52   *             Clean and invalidate all user space cache entries
  53   *             before a change of page tables.
  54   *
  55 - *     flush_cache_user_range(start, end, flags)
  56 + *     flush_user_range(start, end, flags)
  57   *
  58   *             Clean and invalidate a range of cache entries in the
  59   *             specified address space before a change of page tables.
  60 @@ -163,6 +163,20 @@
  61   *             - start  - virtual start address
  62   *             - end    - virtual end address
  63   *
  64 + *     coherent_user_range(start, end)
  65 + *
  66 + *             Ensure coherency between the Icache and the Dcache in the
  67 + *             region described by start, end.  If you have non-snooping
  68 + *             Harvard caches, you need to implement this function.
  69 + *             - start  - virtual start address
  70 + *             - end    - virtual end address
  71 + *
  72 + *     flush_kern_dcache_area(kaddr, size)
  73 + *
  74 + *             Ensure that the data held in page is written back.
  75 + *             - kaddr  - page address
  76 + *             - size   - region size
  77 + *
  78   *     DMA Cache Coherency
  79   *     ===================
  80   *
  81 --- kernel-maemo-2.6.28.orig/arch/arm/kernel/debug.S
  82 +++ kernel-maemo-2.6.28/arch/arm/kernel/debug.S
  83 @@ -49,6 +49,26 @@
  84  1002:
  85                 .endm
  86
  87 +#elif defined(CONFIG_CPU_V7)
  88 +
  89 +               .macro  addruart, rx
  90 +               .endm
  91 +
  92 +               .macro  senduart, rd, rx
  93 +               mcr     p14, 0, \rd, c0, c5, 0
  94 +               .endm
  95 +
  96 +               .macro  busyuart, rd, rx
  97 +busy:          mrc     p14, 0, pc, c0, c1, 0
  98 +               bcs     busy
  99 +               .endm
 100 +
 101 +               .macro  waituart, rd, rx
 102 +wait:          mrc     p14, 0, pc, c0, c1, 0
 103 +               bcs     wait
 104 +
 105 +               .endm
 106 +
 107  #else
 108
 109                 .macro  addruart, rx
 110 --- kernel-maemo-2.6.28.orig/arch/arm/mm/mmu.c
 111 +++ kernel-maemo-2.6.28/arch/arm/mm/mmu.c
 112 @@ -953,4 +953,6 @@
 113                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
 114                 flush_pmd_entry(pmd);
 115         }
 116 +
 117 +       local_flush_tlb_all();
 118  }
 119 --- kernel-maemo-2.6.28.orig/arch/arm/mm/proc-v6.S
 120 +++ kernel-maemo-2.6.28/arch/arm/mm/proc-v6.S
 121 @@ -56,8 +56,6 @@
 122   *     to what would be the reset vector.
 123   *
 124   *     - loc   - location to jump to for soft reset
 125 - *
 126 - *     It is assumed that:
 127   */
 128         .align  5
 129  ENTRY(cpu_v6_reset)
 130 --- kernel-maemo-2.6.28.orig/arch/arm/mm/proc-v7.S
 131 +++ kernel-maemo-2.6.28/arch/arm/mm/proc-v7.S
 132 @@ -28,7 +28,14 @@
 133  ENDPROC(cpu_v7_proc_init)
 134
 135  ENTRY(cpu_v7_proc_fin)
 136 -       mov     pc, lr
 137 +       stmfd   sp!, {lr}
 138 +       cpsid   if                              @ disable interrupts
 139 +       bl      v7_flush_kern_cache_all
 140 +       mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
 141 +       bic     r0, r0, #0x1000                 @ ...i............
 142 +       bic     r0, r0, #0x0006                 @ .............ca.
 143 +       mcr     p15, 0, r0, c1, c0, 0           @ disable caches
 144 +       ldmfd   sp!, {pc}
 145  ENDPROC(cpu_v7_proc_fin)
 146
 147  /*
 148 @@ -39,8 +46,6 @@
 149   *     to what would be the reset vector.
 150   *
 151   *     - loc   - location to jump to for soft reset
 152 - *
 153 - *     It is assumed that:
 154   */
 155         .align  5
 156  ENTRY(cpu_v7_reset)