From: aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Sat, 7 Mar 2009 21:47:53 +0000 (+0000)
Subject: arm: Fix gic_irq_state.level bitfield type
X-Git-Tag: 0.10.0-0sb10~1827
X-Git-Url: https://vcs.maemo.org/git/?a=commitdiff_plain;h=a45db6c6fd587be85118038be3722c1dadeedfe4;p=qemu

arm: Fix gic_irq_state.level bitfield type

Found while cleaning up compiler warnings: GIC_*_LEVEL macros strongly
suggest that gic_irq_state.level is intended to be per-CPU and not just
a single, global bit. I'm unable to test the effect, but it seems to be
the most reasonable fix for the apparent brokenness.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6765 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index fef3113..8e61b6e 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -39,7 +39,7 @@ typedef struct gic_irq_state
     unsigned enabled:1;
     unsigned pending:NCPU;
     unsigned active:NCPU;
-    unsigned level:1;
+    unsigned level:NCPU;
     unsigned model:1; /* 0 = N:N, 1 = 1:N */
     unsigned trigger:1; /* nonzero = edge triggered.  */
 } gic_irq_state;