cpu_register_physical_memory(base, 0x900, malta);
cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
- s->display = qemu_chr_open("vc:320x200");
+ s->display = qemu_chr_open("fpga", "vc:320x200");
qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
qemu_chr_printf(s->display, "+--------+\r\n");
qemu_chr_printf(s->display, "+ +\r\n");
qemu_chr_printf(s->display, "+ +\r\n");
qemu_chr_printf(s->display, "+--------+\r\n");
- uart_chr = qemu_chr_open("vc:80Cx24C");
+ uart_chr = qemu_chr_open("cbus", "vc:80Cx24C");
qemu_chr_printf(uart_chr, "CBUS UART\r\n");
s->uart =
serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1);
s->fclk = fclk;
s->irq = irq;
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
- chr ?: qemu_chr_open("null"), 1);
+ chr ?: qemu_chr_open("null", "null"), 1);
return s;
}
/* TODO: Should reuse or destroy current s->serial */
s->serial = serial_mm_init(s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16,
- chr ?: qemu_chr_open("null"), 1);
+ chr ?: qemu_chr_open("null", "null"), 1);
}
/* MPU Clock/Reset/Power Mode Control */
s->irq = irq;
omap_sti_reset(s);
- s->chr = chr ?: qemu_chr_open("null");
+ s->chr = chr ?: qemu_chr_open("null", "null");
iomemtype = l4_register_io_memory(0, omap_sti_readfn,
omap_sti_writefn, s);