uint32_t pcsr; /* CPU sensitivity register */
IRQ_queue_t raised;
IRQ_queue_t servicing;
- CPUState *env; /* Needed if we did SMP */
+ CPUState *env;
} IRQ_dst_t;
struct openpic_t {
if (priority > dst->raised.priority) {
IRQ_get_next(opp, &dst->raised);
DPRINTF("Raise CPU IRQ\n");
- /* XXX: choose the correct cpu */
- cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
+ cpu_interrupt(dst->env, CPU_INTERRUPT_HARD);
}
}
src = &opp->src[n_IRQ];
if (IPVP_PRIORITY(src->ipvp) > dst->servicing.priority) {
DPRINTF("Raise CPU IRQ\n");
- /* XXX: choose cpu */
- cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
+ cpu_interrupt(dst->env, CPU_INTERRUPT_HARD);
}
}
break;
#endif
}
-openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus)
+openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
+ CPUPPCState **envp)
{
openpic_t *opp;
uint8_t *pci_conf;
for (; i < MAX_IRQ; i++) {
opp->src[i].type = IRQ_INTERNAL;
}
+ for (i = 0; i < nb_cpus; i++)
+ opp->dst[i].env = envp[i];
openpic_reset(opp);
if (pmem_index)
*pmem_index = opp->mem_index;
vga_initialize(pci_bus, ds, phys_ram_base + ram_size,
ram_size, vga_ram_size,
vga_bios_offset, vga_bios_size);
- pic = openpic_init(NULL, &openpic_mem_index, 1);
+ pic = openpic_init(NULL, &openpic_mem_index, 1, &env);
set_irq = openpic_set_irq;
pci_set_pic(pci_bus, set_irq, pic);
/* openpic.c */
typedef struct openpic_t openpic_t;
void openpic_set_irq(void *opaque, int n_IRQ, int level);
-openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus);
+openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
+ CPUState **envp);
/* heathrow_pic.c */
typedef struct HeathrowPICS HeathrowPICS;