}
pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
-#ifdef TARGET_SPARC
+#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
do_unassigned_access(addr, 0, 1, 0);
#else
cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);
+void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
+ int unused);
+
#define CPUState CPUMIPSState
#define cpu_init cpu_mips_init
#define cpu_exec cpu_mips_exec
env = saved_env;
}
+void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
+ int unused)
+{
+ if (is_exec)
+ do_raise_exception(EXCP_IBE);
+ else
+ do_raise_exception(EXCP_DBE);
+}
#endif
/* Complex FPU operations which may need stack space. */