new_mode = ARM_CPU_MODE_SVC;
addr = 0x08;
mask = CPSR_I;
- /* The PC already points to the next instructon. */
+ /* The PC already points to the next instruction. */
offset = 0;
break;
case EXCP_BKPT:
type = (desc & 3);
domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
if (type == 0) {
- /* Secton translation fault. */
+ /* Section translation fault. */
code = 5;
goto do_fault;
}
desc = ldl_phys(table);
type = (desc & 3);
if (type == 0) {
- /* Secton translation fault. */
+ /* Section translation fault. */
code = 5;
domain = 0;
goto do_fault;
tmp = load_cpu_field(vfp.xregs[rn]);
break;
case ARM_VFP_FPSCR:
- if (rd == 15) {
+ if (rd == 15) {
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
} else {
if (!(arm_feature(env, ARM_FEATURE_THUMB2)
|| arm_feature (env, ARM_FEATURE_M))) {
- /* Thumb-1 cores may need to tread bl and blx as a pair of
+ /* Thumb-1 cores may need to treat bl and blx as a pair of
16-bit instructions to get correct prefetch abort behavior. */
insn = insn_hw1;
if ((insn & (1 << 12)) == 0) {