X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Ftcx.c;h=a6c8e4891502bdd9ef5bd265d98ec763d72a6f90;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=db27dcf4914bf38b246256dccbde4b809946ebfc;hpb=8508b89e366906ec4f1b15fdd2e9ce5fab2b1bd6;p=qemu diff --git a/hw/tcx.c b/hw/tcx.c index db27dcf..a6c8e48 100644 --- a/hw/tcx.c +++ b/hw/tcx.c @@ -1,8 +1,8 @@ /* * QEMU TCX Frame buffer - * + * * Copyright (c) 2003-2005 Fabrice Bellard - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -22,6 +22,7 @@ * THE SOFTWARE. */ #include "vl.h" +#include "pixel_ops.h" #define MAXX 1024 #define MAXY 768 @@ -31,7 +32,7 @@ #define TCX_TEC_NREGS 0x1000 typedef struct TCXState { - uint32_t addr; + target_phys_addr_t addr; DisplayState *ds; uint8_t *vram; uint32_t *vram24, *cplane; @@ -44,27 +45,8 @@ typedef struct TCXState { static void tcx_screen_dump(void *opaque, const char *filename); static void tcx24_screen_dump(void *opaque, const char *filename); - -/* XXX: unify with vga draw line functions */ -static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b) -{ - return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6); -} - -static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b) -{ - return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3); -} - -static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b) -{ - return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3); -} - -static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b) -{ - return (r << 16) | (g << 8) | b; -} +static void tcx_invalidate_display(void *opaque); +static void tcx24_invalidate_display(void *opaque); static void update_palette_entries(TCXState *s, int start, int end) { @@ -76,52 +58,65 @@ static void update_palette_entries(TCXState *s, int start, int end) s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); break; case 15: - s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); + if (s->ds->bgr) + s->palette[i] = rgb_to_pixel15bgr(s->r[i], s->g[i], s->b[i]); + else + s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); break; case 16: - s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); + if (s->ds->bgr) + s->palette[i] = rgb_to_pixel16bgr(s->r[i], s->g[i], s->b[i]); + else + s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); break; case 32: - s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); + if (s->ds->bgr) + s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); + else + s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); break; } } + if (s->depth == 24) + tcx24_invalidate_display(s); + else + tcx_invalidate_display(s); } -static void tcx_draw_line32(TCXState *s1, uint8_t *d, - const uint8_t *s, int width) +static void tcx_draw_line32(TCXState *s1, uint8_t *d, + const uint8_t *s, int width) { int x; uint8_t val; uint32_t *p = (uint32_t *)d; for(x = 0; x < width; x++) { - val = *s++; + val = *s++; *p++ = s1->palette[val]; } } -static void tcx_draw_line16(TCXState *s1, uint8_t *d, - const uint8_t *s, int width) +static void tcx_draw_line16(TCXState *s1, uint8_t *d, + const uint8_t *s, int width) { int x; uint8_t val; uint16_t *p = (uint16_t *)d; for(x = 0; x < width; x++) { - val = *s++; + val = *s++; *p++ = s1->palette[val]; } } -static void tcx_draw_line8(TCXState *s1, uint8_t *d, - const uint8_t *s, int width) +static void tcx_draw_line8(TCXState *s1, uint8_t *d, + const uint8_t *s, int width) { int x; uint8_t val; for(x = 0; x < width; x++) { - val = *s++; + val = *s++; *d++ = s1->palette[val]; } } @@ -185,10 +180,10 @@ static void tcx_update_display(void *opaque) ram_addr_t page, page_min, page_max; int y, y_start, dd, ds; uint8_t *d, *s; - void (*f)(TCXState *s1, uint8_t *d, const uint8_t *s, int width); + void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); if (ts->ds->depth == 0) - return; + return; page = ts->vram_offset; y_start = -1; page_min = 0xffffffff; @@ -200,55 +195,55 @@ static void tcx_update_display(void *opaque) switch (ts->ds->depth) { case 32: - f = tcx_draw_line32; - break; + f = tcx_draw_line32; + break; case 15: case 16: - f = tcx_draw_line16; - break; + f = tcx_draw_line16; + break; default: case 8: - f = tcx_draw_line8; - break; + f = tcx_draw_line8; + break; case 0: - return; + return; } - + for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { - if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) { - if (y_start < 0) + if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) { + if (y_start < 0) y_start = y; if (page < page_min) page_min = page; if (page > page_max) page_max = page; - f(ts, d, s, ts->width); - d += dd; - s += ds; - f(ts, d, s, ts->width); - d += dd; - s += ds; - f(ts, d, s, ts->width); - d += dd; - s += ds; - f(ts, d, s, ts->width); - d += dd; - s += ds; - } else { + f(ts, d, s, ts->width); + d += dd; + s += ds; + f(ts, d, s, ts->width); + d += dd; + s += ds; + f(ts, d, s, ts->width); + d += dd; + s += ds; + f(ts, d, s, ts->width); + d += dd; + s += ds; + } else { if (y_start >= 0) { /* flush to display */ - dpy_update(ts->ds, 0, y_start, + dpy_update(ts->ds, 0, y_start, ts->width, y - y_start); y_start = -1; } - d += dd * 4; - s += ds * 4; - } + d += dd * 4; + s += ds * 4; + } } if (y_start >= 0) { - /* flush to display */ - dpy_update(ts->ds, 0, y_start, - ts->width, y - y_start); + /* flush to display */ + dpy_update(ts->ds, 0, y_start, + ts->width, y - y_start); } /* reset modified pages */ if (page_min <= page_max) { @@ -339,7 +334,7 @@ static void tcx_invalidate_display(void *opaque) int i; for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { - cpu_physical_memory_set_dirty(s->vram_offset + i); + cpu_physical_memory_set_dirty(s->vram_offset + i); } } @@ -358,11 +353,7 @@ static void tcx24_invalidate_display(void *opaque) static void tcx_save(QEMUFile *f, void *opaque) { TCXState *s = opaque; - - qemu_put_be32s(f, (uint32_t *)&s->addr); - qemu_put_be32s(f, (uint32_t *)&s->vram); - qemu_put_be32s(f, (uint32_t *)&s->vram24); - qemu_put_be32s(f, (uint32_t *)&s->cplane); + qemu_put_be16s(f, (uint16_t *)&s->height); qemu_put_be16s(f, (uint16_t *)&s->width); qemu_put_be16s(f, (uint16_t *)&s->depth); @@ -376,14 +367,16 @@ static void tcx_save(QEMUFile *f, void *opaque) static int tcx_load(QEMUFile *f, void *opaque, int version_id) { TCXState *s = opaque; - - if (version_id != 2) + uint32_t dummy; + + if (version_id != 3 && version_id != 4) return -EINVAL; - qemu_get_be32s(f, (uint32_t *)&s->addr); - qemu_get_be32s(f, (uint32_t *)&s->vram); - qemu_get_be32s(f, (uint32_t *)&s->vram24); - qemu_get_be32s(f, (uint32_t *)&s->cplane); + if (version_id == 3) { + qemu_get_be32s(f, (uint32_t *)&dummy); + qemu_get_be32s(f, (uint32_t *)&dummy); + qemu_get_be32s(f, (uint32_t *)&dummy); + } qemu_get_be16s(f, (uint16_t *)&s->height); qemu_get_be16s(f, (uint16_t *)&s->width); qemu_get_be16s(f, (uint16_t *)&s->depth); @@ -393,7 +386,10 @@ static int tcx_load(QEMUFile *f, void *opaque, int version_id) qemu_get_8s(f, &s->dac_index); qemu_get_8s(f, &s->dac_state); update_palette_entries(s, 0, 256); - tcx_invalidate_display(s); + if (s->depth == 24) + tcx24_invalidate_display(s); + else + tcx_invalidate_display(s); return 0; } @@ -428,32 +424,32 @@ static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2; switch (saddr) { case 0: - s->dac_index = val >> 24; - s->dac_state = 0; - break; + s->dac_index = val >> 24; + s->dac_state = 0; + break; case 1: - switch (s->dac_state) { - case 0: - s->r[s->dac_index] = val >> 24; + switch (s->dac_state) { + case 0: + s->r[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); - s->dac_state++; - break; - case 1: - s->g[s->dac_index] = val >> 24; + s->dac_state++; + break; + case 1: + s->g[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); - s->dac_state++; - break; - case 2: - s->b[s->dac_index] = val >> 24; + s->dac_state++; + break; + case 2: + s->b[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement - default: - s->dac_state = 0; - break; - } - break; + default: + s->dac_state = 0; + break; + } + break; default: - break; + break; } return; } @@ -492,7 +488,7 @@ static CPUWriteMemoryFunc *tcx_dummy_write[3] = { tcx_dummy_writel, }; -void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base, +void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base, unsigned long vram_offset, int vram_size, int width, int height, int depth) { @@ -513,23 +509,23 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base, // 8-bit plane s->vram = vram_base; size = vram_size; - cpu_register_physical_memory(addr + 0x00800000, size, vram_offset); + cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset); vram_offset += size; vram_base += size; io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s); - cpu_register_physical_memory(addr + 0x00200000, TCX_DAC_NREGS, io_memory); + cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, io_memory); dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write, s); - cpu_register_physical_memory(addr + 0x00700000, TCX_TEC_NREGS, + cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS, dummy_memory); if (depth == 24) { // 24-bit plane size = vram_size * 4; s->vram24 = (uint32_t *)vram_base; s->vram24_offset = vram_offset; - cpu_register_physical_memory(addr + 0x02000000, size, vram_offset); + cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset); vram_offset += size; vram_base += size; @@ -537,19 +533,20 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base, size = vram_size * 4; s->cplane = (uint32_t *)vram_base; s->cplane_offset = vram_offset; - cpu_register_physical_memory(addr + 0x0a000000, size, vram_offset); - cpu_register_physical_memory(addr + 0x00301000, TCX_THC_NREGS_24, - dummy_memory); + cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset); graphic_console_init(s->ds, tcx24_update_display, tcx24_invalidate_display, tcx24_screen_dump, s); } else { - cpu_register_physical_memory(addr + 0x00300000, TCX_THC_NREGS_8, + cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8, dummy_memory); graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display, tcx_screen_dump, s); } + // NetBSD writes here even with 8-bit display + cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24, + dummy_memory); - register_savevm("tcx", addr, 1, tcx_save, tcx_load, s); + register_savevm("tcx", addr, 4, tcx_save, tcx_load, s); qemu_register_reset(tcx_reset, s); tcx_reset(s); dpy_resize(s->ds, width, height);