X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fsun4m.c;h=89f4b418d24b2366b5f75f9499fd942217ea2b2b;hb=384ccb5d348656584de998fc0aee81d5efa3b11e;hp=5150af4ca5929e74bef9f09adc5461f58e068a43;hpb=e0353fe250eacac23104ff7fe466cd6533536509;p=qemu diff --git a/hw/sun4m.c b/hw/sun4m.c index 5150af4..89f4b41 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -117,6 +117,34 @@ static void nvram_set_string (m48t59_t *nvram, uint32_t addr, m48t59_write(nvram, addr + max - 1, '\0'); } +static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr, + const unsigned char *str) +{ + uint32_t len; + + len = strlen(str) + 1; + nvram_set_string(nvram, addr, str, len); + + return addr + len; +} + +static void nvram_finish_partition (m48t59_t *nvram, uint32_t start, + uint32_t end) +{ + unsigned int i, sum; + + // Length divided by 16 + m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff); + m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff); + // Checksum + sum = m48t59_read(nvram, start); + for (i = 0; i < 14; i++) { + sum += m48t59_read(nvram, start + 2 + i); + sum = (sum + ((sum & 0xff00) >> 8)) & 0xff; + } + m48t59_write(nvram, start + 1, sum & 0xff); +} + static m48t59_t *nvram; extern int nographic; @@ -128,7 +156,8 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, int machine_id) { unsigned char tmp = 0; - int i, j; + unsigned int i, j; + uint32_t start, end; // Try to match PPC NVRAM nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); @@ -151,8 +180,30 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, nvram_set_word(nvram, 0x56, height); nvram_set_word(nvram, 0x58, depth); + // OpenBIOS nvram variables + // Variable partition + start = 252; + m48t59_write(nvram, start, 0x70); + nvram_set_string(nvram, start + 4, "system", 12); + + end = start + 16; + for (i = 0; i < nb_prom_envs; i++) + end = nvram_set_var(nvram, end, prom_envs[i]); + + m48t59_write(nvram, end++ , 0); + end = start + ((end - start + 15) & ~15); + nvram_finish_partition(nvram, start, end); + + // free partition + start = end; + m48t59_write(nvram, start, 0x7f); + nvram_set_string(nvram, start + 4, "free", 12); + + end = 0x1fd0; + nvram_finish_partition(nvram, start, end); + // Sun4m specific use - i = 0x1fd8; + start = i = 0x1fd8; m48t59_write(nvram, i++, 0x01); m48t59_write(nvram, i++, machine_id); j = 0; @@ -164,10 +215,10 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, m48t59_write(nvram, i, macaddr[j]); /* Calculate checksum */ - for (i = 0x1fd8; i < 0x1fe7; i++) { - tmp ^= m48t59_read(nvram, i); + for (i = start; i < start + 15; i++) { + tmp ^= m48t59_read(nvram, i); } - m48t59_write(nvram, 0x1fe7, tmp); + m48t59_write(nvram, start + 15, tmp); } static void *slavio_intctl; @@ -182,21 +233,6 @@ void irq_info() slavio_irq_info(slavio_intctl); } -void pic_set_irq(int irq, int level) -{ - slavio_pic_set_irq(slavio_intctl, irq, level); -} - -void pic_set_irq_new(void *opaque, int irq, int level) -{ - pic_set_irq(irq, level); -} - -void pic_set_irq_cpu(int irq, int level, unsigned int cpu) -{ - slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu); -} - static void *slavio_misc; void qemu_system_powerdown(void) @@ -218,6 +254,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size, unsigned int i; void *iommu, *dma, *main_esp, *main_lance = NULL; const sparc_def_t *def; + qemu_irq *slavio_irq; /* init CPUs */ sparc_find_by_name(cpu_model, &def); @@ -240,37 +277,44 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size, iommu = iommu_init(hwdef->iommu_base); slavio_intctl = slavio_intctl_init(hwdef->intctl_base, hwdef->intctl_base + 0x10000, - &hwdef->intbit_to_level[0]); + &hwdef->intbit_to_level[0], + &slavio_irq); for(i = 0; i < smp_cpus; i++) { slavio_intctl_set_cpu(slavio_intctl, i, envs[i]); } - dma = sparc32_dma_init(hwdef->dma_base, hwdef->esp_irq, - hwdef->le_irq, iommu, slavio_intctl); + dma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], + slavio_irq[hwdef->le_irq], iommu); + if (graphic_depth != 8 && graphic_depth != 24) { + fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); + exit (1); + } tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size, - hwdef->vram_size, graphic_width, graphic_height); + hwdef->vram_size, graphic_width, graphic_height, graphic_depth); if (nd_table[0].vlan) { if (nd_table[0].model == NULL || strcmp(nd_table[0].model, "lance") == 0) { - main_lance = lance_init(&nd_table[0], hwdef->le_base, dma); + main_lance = lance_init(&nd_table[0], hwdef->le_base, dma, + slavio_irq[hwdef->le_irq]); } else { fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); exit (1); } } - nvram = m48t59_init(0, hwdef->nvram_base, 0, hwdef->nvram_size, 8); + nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, + hwdef->nvram_size, 8); for (i = 0; i < MAX_CPUS; i++) { slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE, - hwdef->clock_irq, 0, i); + hwdef->clock_irq, 0, i, slavio_intctl); } slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2, - (unsigned int)-1); - slavio_serial_ms_kbd_init(hwdef->ms_kb_base, hwdef->ms_kb_irq); + (unsigned int)-1, slavio_intctl); + slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]); // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device - slavio_serial_init(hwdef->serial_base, hwdef->ser_irq, + slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], serial_hds[1], serial_hds[0]); - fdctrl_init(hwdef->fd_irq, 0, 1, hwdef->fd_base, fd_table); + fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table); main_esp = esp_init(bs_table, hwdef->esp_base, dma); for (i = 0; i < MAX_DISKS; i++) { @@ -279,8 +323,10 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size, } } - slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->me_irq); - cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); + slavio_misc = slavio_misc_init(hwdef->slavio_base, + slavio_irq[hwdef->me_irq]); + if (hwdef->cs_base != (target_ulong)-1) + cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); sparc32_dma_set_reset_data(dma, main_esp, main_lance); } @@ -303,7 +349,7 @@ static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device, prom_offset | IO_MEM_ROM); snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME); - ret = load_elf(buf, 0, NULL); + ret = load_elf(buf, 0, NULL, NULL, NULL); if (ret < 0) { fprintf(stderr, "qemu: could not load prom '%s'\n", buf); @@ -312,7 +358,7 @@ static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device, kernel_size = 0; if (linux_boot) { - kernel_size = load_elf(kernel_filename, -0xf0000000, NULL); + kernel_size = load_elf(kernel_filename, -0xf0000000, NULL, NULL, NULL); if (kernel_size < 0) kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); if (kernel_size < 0) @@ -355,7 +401,7 @@ static const struct hwdef hwdefs[] = { .iommu_base = 0x10000000, .tcx_base = 0x50000000, .cs_base = 0x6c000000, - .slavio_base = 0x71000000, + .slavio_base = 0x70000000, .ms_kb_base = 0x71000000, .serial_base = 0x71100000, .nvram_base = 0x71200000, @@ -383,21 +429,20 @@ static const struct hwdef hwdefs[] = { }, }, /* SS-10 */ - /* XXX: Replace with real values */ { - .iommu_base = 0x10000000, - .tcx_base = 0x50000000, - .cs_base = 0x6c000000, - .slavio_base = 0x71000000, - .ms_kb_base = 0x71000000, - .serial_base = 0x71100000, - .nvram_base = 0x71200000, - .fd_base = 0x71400000, - .counter_base = 0x71d00000, - .intctl_base = 0x71e00000, - .dma_base = 0x78400000, - .esp_base = 0x78800000, - .le_base = 0x78c00000, + .iommu_base = 0xe0000000, // XXX Actually at 0xfe0000000ULL (36 bits) + .tcx_base = 0x20000000, // 0xe20000000ULL, + .cs_base = -1, + .slavio_base = 0xf0000000, // 0xff0000000ULL, + .ms_kb_base = 0xf1000000, // 0xff1000000ULL, + .serial_base = 0xf1100000, // 0xff1100000ULL, + .nvram_base = 0xf1200000, // 0xff1200000ULL, + .fd_base = 0xf1700000, // 0xff1700000ULL, + .counter_base = 0xf1300000, // 0xff1300000ULL, + .intctl_base = 0xf1400000, // 0xff1400000ULL, + .dma_base = 0xf0400000, // 0xef0400000ULL, + .esp_base = 0xf0800000, // 0xef0800000ULL, + .le_base = 0xf0c00000, // 0xef0c00000ULL, .vram_size = 0x00100000, .nvram_size = 0x2000, .esp_irq = 18, @@ -408,8 +453,8 @@ static const struct hwdef hwdefs[] = { .ser_irq = 15, .fd_irq = 22, .me_irq = 30, - .cs_irq = 5, - .machine_id = 0x73, + .cs_irq = -1, + .machine_id = 0x72, .intbit_to_level = { 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,