X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fsun4m.c;h=5974812670b23a64428274b69286cf6cc5dd75b2;hb=327ac2e797ed57d7231d44c77a7473d62efe0989;hp=ec195def4a55e9d6008bd51192ad7d39676b8d05;hpb=4edebb0e8e14a5b934114b5ff74cb86437bb2532;p=qemu diff --git a/hw/sun4m.c b/hw/sun4m.c index ec195de..5974812 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -22,6 +22,7 @@ * THE SOFTWARE. */ #include "vl.h" +//#define DEBUG_IRQ /* * Sun4m architecture was used in the following machines: @@ -38,6 +39,13 @@ * See for example: http://www.sunhelp.org/faq/sunref1.html */ +#ifdef DEBUG_IRQ +#define DPRINTF(fmt, args...) \ + do { printf("CPUIRQ: " fmt , ##args); } while (0) +#else +#define DPRINTF(fmt, args...) +#endif + #define KERNEL_LOAD_ADDR 0x00004000 #define CMDLINE_ADDR 0x007ff000 #define INITRD_LOAD_ADDR 0x00800000 @@ -46,17 +54,18 @@ #define PROM_FILENAME "openbios-sparc32" #define MAX_CPUS 16 +#define MAX_PILS 16 struct hwdef { - target_ulong iommu_base, slavio_base; - target_ulong intctl_base, counter_base, nvram_base, ms_kb_base, serial_base; - target_ulong fd_base; - target_ulong dma_base, esp_base, le_base; - target_ulong tcx_base, cs_base; + target_phys_addr_t iommu_base, slavio_base; + target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; + target_phys_addr_t serial_base, fd_base; + target_phys_addr_t dma_base, esp_base, le_base; + target_phys_addr_t tcx_base, cs_base, power_base; long vram_size, nvram_size; // IRQ numbers are not PIL ones, but master interrupt controller register // bit numbers - int intctl_g_intr, esp_irq, le_irq, cpu_irq, clock_irq, clock1_irq; + int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq; int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq; int machine_id; // For NVRAM uint32_t intbit_to_level[32]; @@ -145,8 +154,6 @@ static void nvram_finish_partition (m48t59_t *nvram, uint32_t start, m48t59_write(nvram, start + 1, sum & 0xff); } -static m48t59_t *nvram; - extern int nographic; static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, @@ -233,6 +240,48 @@ void irq_info() slavio_irq_info(slavio_intctl); } +void cpu_check_irqs(CPUState *env) +{ + if (env->pil_in && (env->interrupt_index == 0 || + (env->interrupt_index & ~15) == TT_EXTINT)) { + unsigned int i; + + for (i = 15; i > 0; i--) { + if (env->pil_in & (1 << i)) { + int old_interrupt = env->interrupt_index; + + env->interrupt_index = TT_EXTINT | i; + if (old_interrupt != env->interrupt_index) + cpu_interrupt(env, CPU_INTERRUPT_HARD); + break; + } + } + } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { + env->interrupt_index = 0; + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + } +} + +static void cpu_set_irq(void *opaque, int irq, int level) +{ + CPUState *env = opaque; + + if (level) { + DPRINTF("Raise CPU IRQ %d\n", irq); + env->halted = 0; + env->pil_in |= 1 << irq; + cpu_check_irqs(env); + } else { + DPRINTF("Lower CPU IRQ %d\n", irq); + env->pil_in &= ~(1 << irq); + cpu_check_irqs(env); + } +} + +static void dummy_cpu_set_irq(void *opaque, int irq, int level) +{ +} + static void *slavio_misc; void qemu_system_powerdown(void) @@ -256,15 +305,16 @@ static void secondary_cpu_reset(void *opaque) env->halted = 1; } -static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size, - DisplayState *ds, const char *cpu_model) +static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size, + DisplayState *ds, const char *cpu_model) { CPUState *env, *envs[MAX_CPUS]; unsigned int i; - void *iommu, *dma, *main_esp, *main_lance = NULL; + void *iommu, *espdma, *ledma, *main_esp, *nvram; const sparc_def_t *def; - qemu_irq *slavio_irq; + qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, + *espdma_irq, *ledma_irq; /* init CPUs */ sparc_find_by_name(cpu_model, &def); @@ -272,6 +322,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size, fprintf(stderr, "Unable to find Sparc CPU definition\n"); exit(1); } + for(i = 0; i < smp_cpus; i++) { env = cpu_init(); cpu_sparc_register(env, def); @@ -283,52 +334,62 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size, env->halted = 1; } register_savevm("cpu", i, 3, cpu_save, cpu_load, env); + cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); } + + for (i = smp_cpus; i < MAX_CPUS; i++) + cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); + /* allocate RAM */ - cpu_register_physical_memory(0, ram_size, 0); + cpu_register_physical_memory(0, RAM_size, 0); iommu = iommu_init(hwdef->iommu_base); slavio_intctl = slavio_intctl_init(hwdef->intctl_base, - hwdef->intctl_base + 0x10000, + hwdef->intctl_base + 0x10000ULL, &hwdef->intbit_to_level[0], - &slavio_irq); - for(i = 0; i < smp_cpus; i++) { - slavio_intctl_set_cpu(slavio_intctl, i, envs[i]); - } - dma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], - slavio_irq[hwdef->le_irq], iommu); + &slavio_irq, &slavio_cpu_irq, + cpu_irqs, + hwdef->clock_irq); + + espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], + iommu, &espdma_irq); + ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, + slavio_irq[hwdef->le_irq], iommu, &ledma_irq); if (graphic_depth != 8 && graphic_depth != 24) { fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); exit (1); } - tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size, + tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, hwdef->vram_size, graphic_width, graphic_height, graphic_depth); - if (nd_table[0].vlan) { - if (nd_table[0].model == NULL - || strcmp(nd_table[0].model, "lance") == 0) { - main_lance = lance_init(&nd_table[0], hwdef->le_base, dma, - slavio_irq[hwdef->le_irq]); - } else { - fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); - exit (1); - } + + if (nd_table[0].model == NULL + || strcmp(nd_table[0].model, "lance") == 0) { + lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq); + } else if (strcmp(nd_table[0].model, "?") == 0) { + fprintf(stderr, "qemu: Supported NICs: lance\n"); + exit (1); + } else { + fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); + exit (1); } + nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, hwdef->nvram_size, 8); for (i = 0; i < MAX_CPUS; i++) { - slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE, - hwdef->clock_irq, 0, i, slavio_intctl); + slavio_timer_init(hwdef->counter_base + + (target_phys_addr_t)(i * TARGET_PAGE_SIZE), + slavio_cpu_irq[i], 0); } - slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2, - (unsigned int)-1, slavio_intctl); + slavio_timer_init(hwdef->counter_base + 0x10000ULL, + slavio_irq[hwdef->clock1_irq], 2); slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]); // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], serial_hds[1], serial_hds[0]); fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table); - main_esp = esp_init(bs_table, hwdef->esp_base, dma); + main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq); for (i = 0; i < MAX_DISKS; i++) { if (bs_table[i]) { @@ -336,18 +397,20 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size, } } - slavio_misc = slavio_misc_init(hwdef->slavio_base, + slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base, slavio_irq[hwdef->me_irq]); - if (hwdef->cs_base != (target_ulong)-1) + if (hwdef->cs_base != (target_phys_addr_t)-1) cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); - sparc32_dma_set_reset_data(dma, main_esp, main_lance); + + return nvram; } -static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device, +static void sun4m_load_kernel(long vram_size, int RAM_size, int boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, - int machine_id) + int machine_id, + void *nvram) { int ret, linux_boot; char buf[1024]; @@ -356,7 +419,7 @@ static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device, linux_boot = (kernel_filename != NULL); - prom_offset = ram_size + vram_size; + prom_offset = RAM_size + vram_size; cpu_register_physical_memory(PROM_ADDR, (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK, prom_offset | IO_MEM_ROM); @@ -404,7 +467,7 @@ static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device, } } nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, - boot_device, ram_size, kernel_size, graphic_width, + boot_device, RAM_size, kernel_size, graphic_width, graphic_height, graphic_depth, machine_id); } @@ -424,6 +487,7 @@ static const struct hwdef hwdefs[] = { .dma_base = 0x78400000, .esp_base = 0x78800000, .le_base = 0x78c00000, + .power_base = 0x7a000000, .vram_size = 0x00100000, .nvram_size = 0x2000, .esp_irq = 18, @@ -443,19 +507,20 @@ static const struct hwdef hwdefs[] = { }, /* SS-10 */ { - .iommu_base = 0xe0000000, // XXX Actually at 0xfe0000000ULL (36 bits) - .tcx_base = 0x20000000, // 0xe20000000ULL, + .iommu_base = 0xfe0000000ULL, + .tcx_base = 0xe20000000ULL, .cs_base = -1, - .slavio_base = 0xf0000000, // 0xff0000000ULL, - .ms_kb_base = 0xf1000000, // 0xff1000000ULL, - .serial_base = 0xf1100000, // 0xff1100000ULL, - .nvram_base = 0xf1200000, // 0xff1200000ULL, - .fd_base = 0xf1700000, // 0xff1700000ULL, - .counter_base = 0xf1300000, // 0xff1300000ULL, - .intctl_base = 0xf1400000, // 0xff1400000ULL, - .dma_base = 0xf0400000, // 0xef0400000ULL, - .esp_base = 0xf0800000, // 0xef0800000ULL, - .le_base = 0xf0c00000, // 0xef0c00000ULL, + .slavio_base = 0xff0000000ULL, + .ms_kb_base = 0xff1000000ULL, + .serial_base = 0xff1100000ULL, + .nvram_base = 0xff1200000ULL, + .fd_base = 0xff1700000ULL, + .counter_base = 0xff1300000ULL, + .intctl_base = 0xff1400000ULL, + .dma_base = 0xef0400000ULL, + .esp_base = 0xef0800000ULL, + .le_base = 0xef0c00000ULL, + .power_base = 0xefa000000ULL, .vram_size = 0x00100000, .nvram_size = 0x2000, .esp_irq = 18, @@ -475,47 +540,50 @@ static const struct hwdef hwdefs[] = { }, }; -static void sun4m_common_init(int ram_size, int boot_device, DisplayState *ds, +static void sun4m_common_init(int RAM_size, int boot_device, DisplayState *ds, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, unsigned int machine, int max_ram) { - if (ram_size > max_ram) { + void *nvram; + + if ((unsigned int)RAM_size > (unsigned int)max_ram) { fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", - ram_size / (1024 * 1024), max_ram / (1024 * 1024)); + (unsigned int)RAM_size / (1024 * 1024), + (unsigned int)max_ram / (1024 * 1024)); exit(1); } - sun4m_hw_init(&hwdefs[machine], ram_size, ds, cpu_model); + nvram = sun4m_hw_init(&hwdefs[machine], RAM_size, ds, cpu_model); - sun4m_load_kernel(hwdefs[machine].vram_size, ram_size, boot_device, + sun4m_load_kernel(hwdefs[machine].vram_size, RAM_size, boot_device, kernel_filename, kernel_cmdline, initrd_filename, - hwdefs[machine].machine_id); + hwdefs[machine].machine_id, nvram); } /* SPARCstation 5 hardware initialisation */ -static void ss5_init(int ram_size, int vga_ram_size, int boot_device, +static void ss5_init(int RAM_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { if (cpu_model == NULL) cpu_model = "Fujitsu MB86904"; - sun4m_common_init(ram_size, boot_device, ds, kernel_filename, + sun4m_common_init(RAM_size, boot_device, ds, kernel_filename, kernel_cmdline, initrd_filename, cpu_model, 0, 0x10000000); } /* SPARCstation 10 hardware initialisation */ -static void ss10_init(int ram_size, int vga_ram_size, int boot_device, +static void ss10_init(int RAM_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { if (cpu_model == NULL) cpu_model = "TI SuperSparc II"; - sun4m_common_init(ram_size, boot_device, ds, kernel_filename, + sun4m_common_init(RAM_size, boot_device, ds, kernel_filename, kernel_cmdline, initrd_filename, cpu_model, - 1, 0x20000000); // XXX tcx overlap, actually first 4GB ok + 1, PROM_ADDR); // XXX prom overlap, actually first 4GB ok } QEMUMachine ss5_machine = {