X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fslavio_intctl.c;h=5412228770af7921664feee694045a6166b2400c;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=745467214b04f1b7615150f0288f9b032bbc0931;hpb=e80cfcfc8884400e826328b772971913a14d0f44;p=qemu

diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
index 7454672..5412228 100644
--- a/hw/slavio_intctl.c
+++ b/hw/slavio_intctl.c
@@ -1,8 +1,8 @@
 /*
  * QEMU Sparc SLAVIO interrupt controller emulation
- * 
- * Copyright (c) 2003-2004 Fabrice Bellard
- * 
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
@@ -23,6 +23,14 @@
  */
 #include "vl.h"
 //#define DEBUG_IRQ_COUNT
+//#define DEBUG_IRQ
+
+#ifdef DEBUG_IRQ
+#define DPRINTF(fmt, args...) \
+do { printf("IRQ: " fmt , ##args); } while (0)
+#else
+#define DPRINTF(fmt, args...)
+#endif
 
 /*
  * Registers of interrupt controller in sun4m.
@@ -32,10 +40,11 @@
  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  *
  * There is a system master controller and one for each cpu.
- * 
+ *
  */
 
 #define MAX_CPUS 16
+#define MAX_PILS 16
 
 typedef struct SLAVIO_INTCTLState {
     uint32_t intreg_pending[MAX_CPUS];
@@ -45,27 +54,39 @@ typedef struct SLAVIO_INTCTLState {
 #ifdef DEBUG_IRQ_COUNT
     uint64_t irq_count[32];
 #endif
+    qemu_irq *cpu_irqs[MAX_CPUS];
+    const uint32_t *intbit_to_level;
+    uint32_t cputimer_bit;
+    uint32_t pil_out[MAX_CPUS];
 } SLAVIO_INTCTLState;
 
 #define INTCTL_MAXADDR 0xf
-#define INTCTLM_MAXADDR 0xf
+#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
+#define INTCTLM_MAXADDR 0x13
+#define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
+#define INTCTLM_MASK 0x1f
+static void slavio_check_interrupts(void *opaque);
 
 // per-cpu interrupt controller
 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
 {
     SLAVIO_INTCTLState *s = opaque;
-    uint32_t saddr;
+    uint32_t saddr, ret;
     int cpu;
 
     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
     saddr = (addr & INTCTL_MAXADDR) >> 2;
     switch (saddr) {
     case 0:
-	return s->intreg_pending[cpu];
+        ret = s->intreg_pending[cpu];
+        break;
     default:
-	break;
+        ret = 0;
+        break;
     }
-    return 0;
+    DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret);
+
+    return ret;
 }
 
 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
@@ -76,19 +97,24 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint
 
     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
     saddr = (addr & INTCTL_MAXADDR) >> 2;
+    DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
     switch (saddr) {
     case 1: // clear pending softints
-	if (val & 0x4000)
-	    val |= 80000000;
-	val &= 0xfffe0000;
-	s->intreg_pending[cpu] &= ~val;
-	break;
+        if (val & 0x4000)
+            val |= 80000000;
+        val &= 0xfffe0000;
+        s->intreg_pending[cpu] &= ~val;
+        slavio_check_interrupts(s);
+        DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
+        break;
     case 2: // set softint
-	val &= 0xfffe0000;
-	s->intreg_pending[cpu] |= val;
-	break;
+        val &= 0xfffe0000;
+        s->intreg_pending[cpu] |= val;
+        slavio_check_interrupts(s);
+        DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
+        break;
     default:
-	break;
+        break;
     }
 }
 
@@ -108,20 +134,26 @@ static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 {
     SLAVIO_INTCTLState *s = opaque;
-    uint32_t saddr;
+    uint32_t saddr, ret;
 
     saddr = (addr & INTCTLM_MAXADDR) >> 2;
     switch (saddr) {
     case 0:
-	return s->intregm_pending;
+        ret = s->intregm_pending & 0x7fffffff;
+        break;
     case 1:
-	return s->intregm_disabled;
+        ret = s->intregm_disabled;
+        break;
     case 4:
-	return s->target_cpu;
+        ret = s->target_cpu;
+        break;
     default:
-	break;
+        ret = 0;
+        break;
     }
-    return 0;
+    DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
+
+    return ret;
 }
 
 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
@@ -129,24 +161,31 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin
     SLAVIO_INTCTLState *s = opaque;
     uint32_t saddr;
 
-    saddr = (addr & INTCTLM_MAXADDR) >> 2;
+    saddr = (addr & INTCTLM_MASK) >> 2;
+    DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
     switch (saddr) {
     case 2: // clear (enable)
-	// Force unused bits
-	val |= 0x7fb2007f;
-	s->intregm_disabled &= ~val;
-	break;
+        // Force clear unused bits
+        val &= ~0x4fb2007f;
+        s->intregm_disabled &= ~val;
+        DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
+        slavio_check_interrupts(s);
+        break;
     case 3: // set (disable, clear pending)
-	// Force unused bits
-	val &= ~0x7fb2007f;
-	s->intregm_disabled |= val;
-	s->intregm_pending &= ~val;
-	break;
+        // Force clear unused bits
+        val &= ~0x4fb2007f;
+        s->intregm_disabled |= val;
+        s->intregm_pending &= ~val;
+        slavio_check_interrupts(s);
+        DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
+        break;
     case 4:
-	s->target_cpu = val & (MAX_CPUS - 1);
-	break;
+        s->target_cpu = val & (MAX_CPUS - 1);
+        slavio_check_interrupts(s);
+        DPRINTF("Set master irq cpu %d\n", s->target_cpu);
+        break;
     default:
-	break;
+        break;
     }
 }
 
@@ -168,7 +207,7 @@ void slavio_pic_info(void *opaque)
     int i;
 
     for (i = 0; i < MAX_CPUS; i++) {
-	term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
+        term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
     }
     term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
 }
@@ -186,58 +225,92 @@ void slavio_irq_info(void *opaque)
     for (i = 0; i < 32; i++) {
         count = s->irq_count[i];
         if (count > 0)
-            term_printf("%2d: %lld\n", i, count);
+            term_printf("%2d: %" PRId64 "\n", i, count);
     }
 #endif
 }
 
-static const uint32_t intbit_to_level[32] = {
-    2, 3, 5, 7, 9, 11, 0, 14,	3, 5, 7, 9, 11, 13, 12, 12,
-    6, 0, 4, 10, 8, 0, 11, 0,	0, 0, 0, 0, 15, 0, 0, 0,
-};
+static void slavio_check_interrupts(void *opaque)
+{
+    SLAVIO_INTCTLState *s = opaque;
+    uint32_t pending = s->intregm_pending, pil_pending;
+    unsigned int i, j;
+
+    pending &= ~s->intregm_disabled;
+
+    DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
+    for (i = 0; i < MAX_CPUS; i++) {
+        pil_pending = 0;
+        if (pending && !(s->intregm_disabled & 0x80000000) &&
+            (i == s->target_cpu)) {
+            for (j = 0; j < 32; j++) {
+                if (pending & (1 << j))
+                    pil_pending |= 1 << s->intbit_to_level[j];
+            }
+        }
+        pil_pending |= (s->intreg_pending[i] >> 16) & 0xfffe;
+
+        for (j = 0; j < MAX_PILS; j++) {
+            if (pil_pending & (1 << j)) {
+                if (!(s->pil_out[i] & (1 << j)))
+                    qemu_irq_raise(s->cpu_irqs[i][j]);
+            } else {
+                if (s->pil_out[i] & (1 << j))
+                    qemu_irq_lower(s->cpu_irqs[i][j]);
+            }
+        }
+        s->pil_out[i] = pil_pending;
+    }
+}
 
 /*
  * "irq" here is the bit number in the system interrupt register to
  * separate serial and keyboard interrupts sharing a level.
  */
-void slavio_pic_set_irq(void *opaque, int irq, int level)
+static void slavio_set_irq(void *opaque, int irq, int level)
 {
     SLAVIO_INTCTLState *s = opaque;
+    uint32_t mask = 1 << irq;
+    uint32_t pil = s->intbit_to_level[irq];
 
-    if (irq < 32) {
-	uint32_t mask = 1 << irq;
-	uint32_t pil = intbit_to_level[irq];
-	if (pil > 0) {
-	    if (level) {
-		s->intregm_pending |= mask;
-		s->intreg_pending[s->target_cpu] |= 1 << pil;
-	    }
-	    else {
-		s->intregm_pending &= ~mask;
-		s->intreg_pending[s->target_cpu] &= ~(1 << pil);
-	    }
-	    if (level &&
-		!(s->intregm_disabled & mask) &&
-		!(s->intregm_disabled & 0x80000000) &&
-		(pil == 15 || (pil > cpu_single_env->psrpil && cpu_single_env->psret == 1))) {
+    DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
+            level);
+    if (pil > 0) {
+        if (level) {
 #ifdef DEBUG_IRQ_COUNT
-		if (level == 1)
-		    s->irq_count[pil]++;
+            s->irq_count[pil]++;
 #endif
-		cpu_single_env->interrupt_index = TT_EXTINT | pil;
-		cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
-	    }
-	}
+            s->intregm_pending |= mask;
+            s->intreg_pending[s->target_cpu] |= 1 << pil;
+        } else {
+            s->intregm_pending &= ~mask;
+            s->intreg_pending[s->target_cpu] &= ~(1 << pil);
+        }
+        slavio_check_interrupts(s);
     }
 }
 
+static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
+{
+    SLAVIO_INTCTLState *s = opaque;
+
+    DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
+
+    if (level)
+        s->intreg_pending[cpu] |= s->cputimer_bit;
+    else
+        s->intreg_pending[cpu] &= ~s->cputimer_bit;
+
+    slavio_check_interrupts(s);
+}
+
 static void slavio_intctl_save(QEMUFile *f, void *opaque)
 {
     SLAVIO_INTCTLState *s = opaque;
     int i;
-    
+
     for (i = 0; i < MAX_CPUS; i++) {
-	qemu_put_be32s(f, &s->intreg_pending[i]);
+        qemu_put_be32s(f, &s->intreg_pending[i]);
     }
     qemu_put_be32s(f, &s->intregm_pending);
     qemu_put_be32s(f, &s->intregm_disabled);
@@ -253,11 +326,12 @@ static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
         return -EINVAL;
 
     for (i = 0; i < MAX_CPUS; i++) {
-	qemu_get_be32s(f, &s->intreg_pending[i]);
+        qemu_get_be32s(f, &s->intreg_pending[i]);
     }
     qemu_get_be32s(f, &s->intregm_pending);
     qemu_get_be32s(f, &s->intregm_disabled);
     qemu_get_be32s(f, &s->target_cpu);
+    slavio_check_interrupts(s);
     return 0;
 }
 
@@ -267,14 +341,18 @@ static void slavio_intctl_reset(void *opaque)
     int i;
 
     for (i = 0; i < MAX_CPUS; i++) {
-	s->intreg_pending[i] = 0;
+        s->intreg_pending[i] = 0;
     }
-    s->intregm_disabled = 0xffffffff;
+    s->intregm_disabled = ~0xffb2007f;
     s->intregm_pending = 0;
     s->target_cpu = 0;
+    slavio_check_interrupts(s);
 }
 
-void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
+void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
+                         const uint32_t *intbit_to_level,
+                         qemu_irq **irq, qemu_irq **cpu_irq,
+                         qemu_irq **parent_irq, unsigned int cputimer)
 {
     int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
     SLAVIO_INTCTLState *s;
@@ -283,16 +361,23 @@ void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
     if (!s)
         return NULL;
 
+    s->intbit_to_level = intbit_to_level;
     for (i = 0; i < MAX_CPUS; i++) {
-	slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
-	cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
+        slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
+        cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
+                                     slavio_intctl_io_memory);
+        s->cpu_irqs[i] = parent_irq[i];
     }
 
     slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
-    cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);
+    cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
 
     register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
     qemu_register_reset(slavio_intctl_reset, s);
+    *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
+
+    *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
+    s->cputimer_bit = 1 << s->intbit_to_level[cputimer];
     slavio_intctl_reset(s);
     return s;
 }