X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fserial.c;h=36a7cc4e3d5ce87f4e0506d3de7163d09cc143fd;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=60c311e55d643b2825b5c28698d77d05a18b8854;hpb=b41a2cd1e4228c765e3b82ec6c89096528b4d7d9;p=qemu diff --git a/hw/serial.c b/hw/serial.c index 60c311e..36a7cc4 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -1,8 +1,8 @@ /* * QEMU 16450 UART emulation - * + * * Copyright (c) 2003-2004 Fabrice Bellard - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -21,26 +21,6 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu.h" #include "vl.h" //#define DEBUG_SERIAL @@ -91,20 +71,23 @@ #define UART_LSR_DR 0x01 /* Receiver data ready */ struct SerialState { - uint8_t divider; + uint16_t divider; uint8_t rbr; /* receive register */ uint8_t ier; uint8_t iir; /* read only */ uint8_t lcr; uint8_t mcr; uint8_t lsr; /* read only */ - uint8_t msr; + uint8_t msr; /* read only */ uint8_t scr; /* NOTE: this hidden state is necessary for tx irq generation as it can be reset while reading iir */ int thr_ipending; - int irq; - int out_fd; + qemu_irq irq; + CharDriverState *chr; + int last_break_enable; + target_phys_addr_t base; + int it_shift; }; static void serial_update_irq(SerialState *s) @@ -117,18 +100,49 @@ static void serial_update_irq(SerialState *s) s->iir = UART_IIR_NO_INT; } if (s->iir != UART_IIR_NO_INT) { - pic_set_irq(s->irq, 1); + qemu_irq_raise(s->irq); + } else { + qemu_irq_lower(s->irq); + } +} + +static void serial_update_parameters(SerialState *s) +{ + int speed, parity, data_bits, stop_bits; + QEMUSerialSetParams ssp; + + if (s->lcr & 0x08) { + if (s->lcr & 0x10) + parity = 'E'; + else + parity = 'O'; } else { - pic_set_irq(s->irq, 0); + parity = 'N'; } + if (s->lcr & 0x04) + stop_bits = 2; + else + stop_bits = 1; + data_bits = (s->lcr & 0x03) + 5; + if (s->divider == 0) + return; + speed = 115200 / s->divider; + ssp.speed = speed; + ssp.parity = parity; + ssp.data_bits = data_bits; + ssp.stop_bits = stop_bits; + qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); +#if 0 + printf("speed=%d parity=%c data=%d stop=%d\n", + speed, parity, data_bits, stop_bits); +#endif } static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) { SerialState *s = opaque; unsigned char ch; - int ret; - + addr &= 7; #ifdef DEBUG_SERIAL printf("serial: write addr=0x%02x val=0x%02x\n", addr, val); @@ -138,15 +152,13 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) case 0: if (s->lcr & UART_LCR_DLAB) { s->divider = (s->divider & 0xff00) | val; + serial_update_parameters(s); } else { s->thr_ipending = 0; s->lsr &= ~UART_LSR_THRE; serial_update_irq(s); - ch = val; - do { - ret = write(s->out_fd, &ch, 1); - } while (ret != 1); + qemu_chr_write(s->chr, &ch, 1); s->thr_ipending = 1; s->lsr |= UART_LSR_THRE; s->lsr |= UART_LSR_TEMT; @@ -156,23 +168,36 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) case 1: if (s->lcr & UART_LCR_DLAB) { s->divider = (s->divider & 0x00ff) | (val << 8); + serial_update_parameters(s); } else { - s->ier = val; + s->ier = val & 0x0f; + if (s->lsr & UART_LSR_THRE) { + s->thr_ipending = 1; + } serial_update_irq(s); } break; case 2: break; case 3: - s->lcr = val; + { + int break_enable; + s->lcr = val; + serial_update_parameters(s); + break_enable = (val >> 6) & 1; + if (break_enable != s->last_break_enable) { + s->last_break_enable = break_enable; + qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, + &break_enable); + } + } break; case 4: - s->mcr = val; + s->mcr = val & 0x1f; break; case 5: break; case 6: - s->msr = val; break; case 7: s->scr = val; @@ -190,7 +215,7 @@ static uint32_t serial_ioport_read(void *opaque, uint32_t addr) default: case 0: if (s->lcr & UART_LCR_DLAB) { - ret = s->divider & 0xff; + ret = s->divider & 0xff; } else { ret = s->rbr; s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); @@ -241,19 +266,19 @@ static uint32_t serial_ioport_read(void *opaque, uint32_t addr) return ret; } -int serial_can_receive(SerialState *s) +static int serial_can_receive(SerialState *s) { return !(s->lsr & UART_LSR_DR); } -void serial_receive_byte(SerialState *s, int ch) +static void serial_receive_byte(SerialState *s, int ch) { s->rbr = ch; s->lsr |= UART_LSR_DR; serial_update_irq(s); } -void serial_receive_break(SerialState *s) +static void serial_receive_break(SerialState *s) { s->rbr = 0; s->lsr |= UART_LSR_BI | UART_LSR_DR; @@ -272,8 +297,53 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size) serial_receive_byte(s, buf[0]); } +static void serial_event(void *opaque, int event) +{ + SerialState *s = opaque; + if (event == CHR_EVENT_BREAK) + serial_receive_break(s); +} + +static void serial_save(QEMUFile *f, void *opaque) +{ + SerialState *s = opaque; + + qemu_put_be16s(f,&s->divider); + qemu_put_8s(f,&s->rbr); + qemu_put_8s(f,&s->ier); + qemu_put_8s(f,&s->iir); + qemu_put_8s(f,&s->lcr); + qemu_put_8s(f,&s->mcr); + qemu_put_8s(f,&s->lsr); + qemu_put_8s(f,&s->msr); + qemu_put_8s(f,&s->scr); +} + +static int serial_load(QEMUFile *f, void *opaque, int version_id) +{ + SerialState *s = opaque; + + if(version_id > 2) + return -EINVAL; + + if (version_id >= 2) + qemu_get_be16s(f, &s->divider); + else + s->divider = qemu_get_byte(f); + qemu_get_8s(f,&s->rbr); + qemu_get_8s(f,&s->ier); + qemu_get_8s(f,&s->iir); + qemu_get_8s(f,&s->lcr); + qemu_get_8s(f,&s->mcr); + qemu_get_8s(f,&s->lsr); + qemu_get_8s(f,&s->msr); + qemu_get_8s(f,&s->scr); + + return 0; +} + /* If fd is zero, it means that the serial device uses the console */ -SerialState *serial_init(int base, int irq, int fd) +SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr) { SerialState *s; @@ -283,16 +353,116 @@ SerialState *serial_init(int base, int irq, int fd) s->irq = irq; s->lsr = UART_LSR_TEMT | UART_LSR_THRE; s->iir = UART_IIR_NO_INT; + s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; + + register_savevm("serial", base, 2, serial_save, serial_load, s); register_ioport_write(base, 8, 1, serial_ioport_write, s); register_ioport_read(base, 8, 1, serial_ioport_read, s); + s->chr = chr; + qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, + serial_event, s); + return s; +} - if (fd != 0) { - add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s); - s->out_fd = fd; - } else { - serial_console = s; - s->out_fd = 1; +/* Memory mapped interface */ +uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr) +{ + SerialState *s = opaque; + + return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF; +} + +void serial_mm_writeb (void *opaque, + target_phys_addr_t addr, uint32_t value) +{ + SerialState *s = opaque; + + serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF); +} + +uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr) +{ + SerialState *s = opaque; + uint32_t val; + + val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF; +#ifdef TARGET_WORDS_BIGENDIAN + val = bswap16(val); +#endif + return val; +} + +void serial_mm_writew (void *opaque, + target_phys_addr_t addr, uint32_t value) +{ + SerialState *s = opaque; +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap16(value); +#endif + serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF); +} + +uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr) +{ + SerialState *s = opaque; + uint32_t val; + + val = serial_ioport_read(s, (addr - s->base) >> s->it_shift); +#ifdef TARGET_WORDS_BIGENDIAN + val = bswap32(val); +#endif + return val; +} + +void serial_mm_writel (void *opaque, + target_phys_addr_t addr, uint32_t value) +{ + SerialState *s = opaque; +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap32(value); +#endif + serial_ioport_write(s, (addr - s->base) >> s->it_shift, value); +} + +static CPUReadMemoryFunc *serial_mm_read[] = { + &serial_mm_readb, + &serial_mm_readw, + &serial_mm_readl, +}; + +static CPUWriteMemoryFunc *serial_mm_write[] = { + &serial_mm_writeb, + &serial_mm_writew, + &serial_mm_writel, +}; + +SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, + qemu_irq irq, CharDriverState *chr, + int ioregister) +{ + SerialState *s; + int s_io_memory; + + s = qemu_mallocz(sizeof(SerialState)); + if (!s) + return NULL; + s->irq = irq; + s->lsr = UART_LSR_TEMT | UART_LSR_THRE; + s->iir = UART_IIR_NO_INT; + s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; + s->base = base; + s->it_shift = it_shift; + + register_savevm("serial", base, 2, serial_save, serial_load, s); + + if (ioregister) { + s_io_memory = cpu_register_io_memory(0, serial_mm_read, + serial_mm_write, s); + cpu_register_physical_memory(base, 8 << it_shift, s_io_memory); } + s->chr = chr; + qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, + serial_event, s); return s; }