X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fpxa2xx.c;h=6109fc13e9a624070e9948fa0dba687fc55ac87d;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=1a7d4a741a84a3421bf386e9309ba9bb43a3a7db;hpb=187337f8b0ec0813dd3876d1efe37d415fb81c2e;p=qemu

diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 1a7d4a7..6109fc1 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -280,7 +280,7 @@ static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
 
         case 1:
             /* Idle */
-            if (!(s->cm_regs[CCCR] & (1 << 31))) {	/* CPDIS */
+            if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) {	/* CPDIS */
                 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
                 break;
             }
@@ -1530,6 +1530,8 @@ static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
     pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
 
     i2s->status &= 0xe0;
+    if (i2s->fifo_len < 16 || !i2s->enable)
+        i2s->status |= 1 << 0;			/* TNF */
     if (i2s->rx_len)
         i2s->status |= 1 << 1;			/* RNE */
     if (i2s->enable)
@@ -2057,7 +2059,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
         s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
 
     s->cm_base = 0x41300000;
-    s->cm_regs[CCCR >> 4] = 0x02000210;	/* 416.0 MHz */
+    s->cm_regs[CCCR >> 2] = 0x02000210;	/* 416.0 MHz */
     s->clkcfg = 0x00000009;		/* Turbo mode active */
     iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
                     pxa2xx_cm_writefn, s);
@@ -2118,7 +2120,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
     s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
 
     /* GPIO1 resets the processor */
-    /* The handler can be overriden by board-specific code */
+    /* The handler can be overridden by board-specific code */
     pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
     return s;
 }
@@ -2166,7 +2168,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
         s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
 
     s->cm_base = 0x41300000;
-    s->cm_regs[CCCR >> 4] = 0x02000210;	/* 416.0 MHz */
+    s->cm_regs[CCCR >> 2] = 0x02000210;	/* 416.0 MHz */
     s->clkcfg = 0x00000009;		/* Turbo mode active */
     iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
                     pxa2xx_cm_writefn, s);
@@ -2227,7 +2229,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
     s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
 
     /* GPIO1 resets the processor */
-    /* The handler can be overriden by board-specific code */
+    /* The handler can be overridden by board-specific code */
     pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
     return s;
 }