X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fppc_prep.c;h=7cb92c77fb3a9addb5a680c8ce32c240ea50768b;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=8d4e9801a92c144a88ac281725793a191a01661d;hpb=b6b8bd1819ffe95ff3b04c66610af5a4d7ba605f;p=qemu diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 8d4e980..7cb92c7 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -1,8 +1,8 @@ /* * QEMU PPC PREP hardware System Emulator - * - * Copyright (c) 2003-2004 Jocelyn Mayer - * + * + * Copyright (c) 2003-2007 Jocelyn Mayer + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -26,6 +26,9 @@ //#define HARD_DEBUG_PPC_IO //#define DEBUG_PPC_IO +/* SMP is not enabled, for now */ +#define MAX_CPUS 1 + #define BIOS_FILENAME "ppc_rom.bin" #define KERNEL_LOAD_ADDR 0x01000000 #define INITRD_LOAD_ADDR 0x01800000 @@ -76,7 +79,7 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; int speaker_data_on; int dummy_refresh_clock; -static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val) +static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) { #if 0 speaker_data_on = (val >> 1) & 1; @@ -84,32 +87,33 @@ static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val) #endif } -static uint32_t speaker_ioport_read(void *opaque, uint32_t addr) +static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) { #if 0 int out; out = pit_get_out(pit, 2, qemu_get_clock(vm_clock)); dummy_refresh_clock ^= 1; return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) | - (dummy_refresh_clock << 4); + (dummy_refresh_clock << 4); #endif return 0; } /* PCI intack register */ /* Read-only register (?) */ -static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value) +static void _PPC_intack_write (void *opaque, + target_phys_addr_t addr, uint32_t value) { // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value); } -static inline uint32_t _PPC_intack_read (target_phys_addr_t addr) +static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr) { uint32_t retval = 0; if (addr == 0xBFFFFFF0) - retval = pic_intack_read(NULL); - // printf("%s: 0x%08x <= %d\n", __func__, addr, retval); + retval = pic_intack_read(isa_pic); + // printf("%s: 0x%08x <= %d\n", __func__, addr, retval); return retval; } @@ -176,12 +180,14 @@ static struct { /* Error diagnostic */ } XCSR; -static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) +static void PPC_XCSR_writeb (void *opaque, + target_phys_addr_t addr, uint32_t value) { printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); } -static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value) +static void PPC_XCSR_writew (void *opaque, + target_phys_addr_t addr, uint32_t value) { #ifdef TARGET_WORDS_BIGENDIAN value = bswap16(value); @@ -189,7 +195,8 @@ static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t val printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); } -static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +static void PPC_XCSR_writel (void *opaque, + target_phys_addr_t addr, uint32_t value) { #ifdef TARGET_WORDS_BIGENDIAN value = bswap32(value); @@ -249,6 +256,8 @@ typedef struct sysctrl_t { uint8_t state; uint8_t syscontrol; uint8_t fake_io[2]; + int contiguous_map; + int endian; } sysctrl_t; enum { @@ -284,12 +293,13 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) /* Special port 92 */ /* Check soft reset asked */ if (val & 0x01) { - // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET); + // cpu_interrupt(first_cpu, PPC_INTERRUPT_RESET); } /* Check LE mode */ if (val & 0x02) { - printf("Little Endian mode isn't supported (yet ?)\n"); - abort(); + sysctrl->endian = 1; + } else { + sysctrl->endian = 0; } break; case 0x0800: @@ -320,7 +330,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) break; case 0x0814: /* L2 invalidate register */ - // tlb_flush(cpu_single_env, 1); + // tlb_flush(first_cpu, 1); break; case 0x081C: /* system control register */ @@ -328,10 +338,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) break; case 0x0850: /* I/O map type register */ - if (!(val & 0x01)) { - printf("No support for non-continuous I/O map mode\n"); - abort(); - } + sysctrl->contiguous_map = val & 0x01; break; default: printf("ERROR: unaffected IO port write: %04lx => %02x\n", @@ -375,6 +382,9 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) /* Motorola base module extended feature register */ retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ break; + case 0x0814: + /* L2 invalidate: don't care */ + break; case 0x0818: /* Keylock */ retval = 0x00; @@ -391,7 +401,7 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) break; case 0x0850: /* I/O map type register */ - retval = 0x01; + retval = sysctrl->contiguous_map; break; default: printf("ERROR: unaffected IO port: %04lx read\n", (long)addr); @@ -402,51 +412,178 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) return retval; } -extern CPUPPCState *global_env; +static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl, + target_phys_addr_t + addr) +{ + if (sysctrl->contiguous_map == 0) { + /* 64 KB contiguous space for IOs */ + addr &= 0xFFFF; + } else { + /* 8 MB non-contiguous space for IOs */ + addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); + } + + return addr; +} + +static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + sysctrl_t *sysctrl = opaque; + + addr = prep_IO_address(sysctrl, addr); + cpu_outb(NULL, addr, value); +} + +static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) +{ + sysctrl_t *sysctrl = opaque; + uint32_t ret; + + addr = prep_IO_address(sysctrl, addr); + ret = cpu_inb(NULL, addr); + + return ret; +} + +static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + sysctrl_t *sysctrl = opaque; + + addr = prep_IO_address(sysctrl, addr); +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap16(value); +#endif + PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value); + cpu_outw(NULL, addr, value); +} + +static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) +{ + sysctrl_t *sysctrl = opaque; + uint32_t ret; + + addr = prep_IO_address(sysctrl, addr); + ret = cpu_inw(NULL, addr); +#ifdef TARGET_WORDS_BIGENDIAN + ret = bswap16(ret); +#endif + PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret); + + return ret; +} + +static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + sysctrl_t *sysctrl = opaque; + + addr = prep_IO_address(sysctrl, addr); +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap32(value); +#endif + PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value); + cpu_outl(NULL, addr, value); +} + +static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) +{ + sysctrl_t *sysctrl = opaque; + uint32_t ret; + + addr = prep_IO_address(sysctrl, addr); + ret = cpu_inl(NULL, addr); +#ifdef TARGET_WORDS_BIGENDIAN + ret = bswap32(ret); +#endif + PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret); + + return ret; +} + +CPUWriteMemoryFunc *PPC_prep_io_write[] = { + &PPC_prep_io_writeb, + &PPC_prep_io_writew, + &PPC_prep_io_writel, +}; + +CPUReadMemoryFunc *PPC_prep_io_read[] = { + &PPC_prep_io_readb, + &PPC_prep_io_readw, + &PPC_prep_io_readl, +}; #define NVRAM_SIZE 0x2000 /* PowerPC PREP hardware initialisation */ -void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, - DisplayState *ds, const char **fd_filename, int snapshot, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename) +static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device, + DisplayState *ds, const char **fd_filename, + int snapshot, const char *kernel_filename, + const char *kernel_cmdline, + const char *initrd_filename, + const char *cpu_model) { + CPUState *env, *envs[MAX_CPUS]; char buf[1024]; m48t59_t *nvram; int PPC_io_memory; - int ret, linux_boot, i, nb_nics1, fd; + int linux_boot, i, nb_nics1, bios_size; unsigned long bios_offset; uint32_t kernel_base, kernel_size, initrd_base, initrd_size; + ppc_def_t *def; + PCIBus *pci_bus; + qemu_irq *i8259; sysctrl = qemu_mallocz(sizeof(sysctrl_t)); if (sysctrl == NULL) - return; + return; linux_boot = (kernel_filename != NULL); + /* init CPUs */ + env = cpu_init(); + if (cpu_model == NULL) + cpu_model = "default"; + ppc_find_by_name(cpu_model, &def); + if (def == NULL) { + cpu_abort(env, "Unable to find PowerPC CPU definition\n"); + } + for (i = 0; i < smp_cpus; i++) { + cpu_ppc_register(env, def); + cpu_ppc_reset(env); + /* Set time-base frequency to 100 Mhz */ + cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); + qemu_register_reset(&cpu_ppc_reset, env); + register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); + envs[i] = env; + } + /* allocate RAM */ cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); /* allocate and load BIOS */ bios_offset = ram_size + vga_ram_size; - snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); - ret = load_image(buf, phys_ram_base + bios_offset); - if (ret != BIOS_SIZE) { - fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf); + if (bios_name == NULL) + bios_name = BIOS_FILENAME; + snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); + bios_size = load_image(buf, phys_ram_base + bios_offset); + if (bios_size < 0 || bios_size > BIOS_SIZE) { + cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf); exit(1); } - cpu_register_physical_memory((uint32_t)(-BIOS_SIZE), - BIOS_SIZE, bios_offset | IO_MEM_ROM); - cpu_single_env->nip = 0xfffffffc; + bios_size = (bios_size + 0xfff) & ~0xfff; + cpu_register_physical_memory((uint32_t)(-bios_size), + bios_size, bios_offset | IO_MEM_ROM); if (linux_boot) { kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); if (kernel_size < 0) { - fprintf(stderr, "qemu: could not load kernel '%s'\n", - kernel_filename); + cpu_abort(env, "qemu: could not load kernel '%s'\n", + kernel_filename); exit(1); } /* load initrd */ @@ -455,8 +592,8 @@ void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, initrd_size = load_image(initrd_filename, phys_ram_base + initrd_base); if (initrd_size < 0) { - fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", - initrd_filename); + cpu_abort(env, "qemu: could not load initial ram disk '%s'\n", + initrd_filename); exit(1); } } else { @@ -471,45 +608,49 @@ void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, initrd_size = 0; } - /* Register CPU as a 74x/75x */ - cpu_ppc_register(cpu_single_env, 0x00080000); - /* Set time-base frequency to 100 Mhz */ - cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL); - isa_mem_base = 0xc0000000; - pci_prep_init(); - /* Register 64 KB of ISA IO space */ - PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL); - cpu_register_physical_memory(0x80000000, 0x00010000, PPC_io_memory); + if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { + cpu_abort(env, "Only 6xx bus is supported on PREP machine\n"); + exit(1); + } + i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); + pci_bus = pci_prep_init(i8259); + // pci_bus = i440fx_init(); + /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ + PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read, + PPC_prep_io_write, sysctrl); + cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); /* init basic PC hardware */ - vga_initialize(ds, phys_ram_base + ram_size, ram_size, - vga_ram_size, 1); - rtc_init(0x70, 8); + pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, + vga_ram_size, 0, 0); // openpic = openpic_init(0x00000000, 0xF0000000, 1); - // pic_init(openpic); - pic_init(); - // pit = pit_init(0x40, 0); + // pit = pit_init(0x40, i8259[0]); + rtc_init(0x70, i8259[8]); - fd = serial_open_device(); - serial_init(0x3f8, 4, fd); + serial_init(0x3f8, i8259[4], serial_hds[0]); nb_nics1 = nb_nics; if (nb_nics1 > NE2000_NB_MAX) nb_nics1 = NE2000_NB_MAX; for(i = 0; i < nb_nics1; i++) { - isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); + if (nd_table[i].model == NULL + || strcmp(nd_table[i].model, "ne2k_isa") == 0) { + isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]); + } else { + pci_nic_init(pci_bus, &nd_table[i], -1); + } } for(i = 0; i < 2; i++) { - isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], + isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], bs_table[2 * i], bs_table[2 * i + 1]); } - kbd_init(); + i8042_init(i8259[1], i8259[12], 0x60); DMA_init(1); // AUD_init(); // SB16_init(); - fdctrl_init(6, 2, 0, 0x3f0, fd_table); + fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table); /* Register speaker port */ register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); @@ -528,11 +669,16 @@ void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); /* PowerPC control and status register group */ #if 0 - PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL); + PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, + NULL); cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); #endif - nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE); + if (usb_enabled) { + usb_ohci_init_pci(pci_bus, 3, -1); + } + + nvram = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); if (nvram == NULL) return; sysctrl->nvram = nvram; @@ -546,5 +692,12 @@ void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, 0, graphic_width, graphic_height, graphic_depth); - pci_ppc_bios_init(); + /* Special port to get debug messages from Open-Firmware */ + register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); } + +QEMUMachine prep_machine = { + "prep", + "PowerPC PREP platform", + ppc_prep_init, +};