X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fppc_chrp.c;h=f53c85b8559e9b6de2b212e4a291430c58bf9e10;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=a8114fa2e46e427fb6c80bd2935810f758958321;hpb=4a0577124ac36b7cdf8e33bf91baa92d2c503a4c;p=qemu diff --git a/hw/ppc_chrp.c b/hw/ppc_chrp.c index a8114fa..f53c85b 100644 --- a/hw/ppc_chrp.c +++ b/hw/ppc_chrp.c @@ -1,8 +1,8 @@ /* * QEMU PPC CHRP/PMAC hardware System Emulator - * + * * Copyright (c) 2004-2007 Fabrice Bellard - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -46,22 +46,26 @@ static int macio_nvram_mem_index = -1; /* DBDMA: currently no op - should suffice right now */ -static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) +static void dbdma_writeb (void *opaque, + target_phys_addr_t addr, uint32_t value) { printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value); } -static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value) +static void dbdma_writew (void *opaque, + target_phys_addr_t addr, uint32_t value) { } -static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +static void dbdma_writel (void *opaque, + target_phys_addr_t addr, uint32_t value) { } static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr) { printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr); + return 0; } @@ -92,7 +96,8 @@ typedef struct MacIONVRAMState { uint8_t data[0x2000]; } MacIONVRAMState; -static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) +static void macio_nvram_writeb (void *opaque, + target_phys_addr_t addr, uint32_t value) { MacIONVRAMState *s = opaque; addr = (addr >> 4) & 0x1fff; @@ -108,6 +113,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) addr = (addr >> 4) & 0x1fff; value = s->data[addr]; // printf("macio_nvram_readb %04x = %02x\n", addr, value); + return value; } @@ -123,22 +129,23 @@ static CPUReadMemoryFunc *macio_nvram_read[] = { &macio_nvram_readb, }; -static MacIONVRAMState *macio_nvram_init(void) +static MacIONVRAMState *macio_nvram_init (void) { MacIONVRAMState *s; s = qemu_mallocz(sizeof(MacIONVRAMState)); if (!s) return NULL; - macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read, + macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read, macio_nvram_write, s); + return s; } -static void macio_map(PCIDevice *pci_dev, int region_num, - uint32_t addr, uint32_t size, int type) +static void macio_map (PCIDevice *pci_dev, int region_num, + uint32_t addr, uint32_t size, int type) { if (heathrow_pic_mem_index >= 0) { - cpu_register_physical_memory(addr + 0x00000, 0x1000, + cpu_register_physical_memory(addr + 0x00000, 0x1000, heathrow_pic_mem_index); } cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index); @@ -148,14 +155,15 @@ static void macio_map(PCIDevice *pci_dev, int region_num, if (ide1_mem_index >= 0) cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index); if (openpic_mem_index >= 0) { - cpu_register_physical_memory(addr + 0x40000, 0x40000, + cpu_register_physical_memory(addr + 0x40000, 0x40000, openpic_mem_index); } if (macio_nvram_mem_index >= 0) - cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index); + cpu_register_physical_memory(addr + 0x60000, 0x20000, + macio_nvram_mem_index); } -static void macio_init(PCIBus *bus, int device_id) +static void macio_init (PCIBus *bus, int device_id) { PCIDevice *d; @@ -173,10 +181,10 @@ static void macio_init(PCIBus *bus, int device_id) d->config[0x0e] = 0x00; // header_type d->config[0x3d] = 0x01; // interrupt on pin 1 - + dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL); - pci_register_io_region(d, 0, 0x80000, + pci_register_io_region(d, 0, 0x80000, PCI_ADDRESS_SPACE_MEM, macio_map); } @@ -204,11 +212,12 @@ static CPUReadMemoryFunc *unin_read[] = { /* temporary frame buffer OSI calls for the video.x driver. The right solution is to modify the driver to use VGA PCI I/Os */ -static int vga_osi_call(CPUState *env) +/* XXX: to be removed. This is no way related to emulation */ +static int vga_osi_call (CPUState *env) { static int vga_vbl_enabled; int linesize; - + // printf("osi_call R5=%d\n", env->gpr[5]); /* same handler as PearPC, coming from the original MOL video @@ -229,7 +238,7 @@ static int vga_osi_call(CPUState *env) break; } } - env->gpr[3] = 0; + env->gpr[3] = 0; env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ @@ -255,7 +264,7 @@ static int vga_osi_call(CPUState *env) break; case 64: /* get color */ /* R6 = index */ - env->gpr[3] = 0; + env->gpr[3] = 0; break; case 116: /* set hwcursor */ /* R6 = x, R7 = y, R8 = visible, R9 = data */ @@ -264,10 +273,11 @@ static int vga_osi_call(CPUState *env) fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]); break; } + return 1; /* osi_call handled */ } -static uint8_t nvram_chksum(const uint8_t *buf, int n) +static uint8_t nvram_chksum (const uint8_t *buf, int n) { int sum, i; sum = 0; @@ -277,17 +287,17 @@ static uint8_t nvram_chksum(const uint8_t *buf, int n) } /* set a free Mac OS NVRAM partition */ -void pmac_format_nvram_partition(uint8_t *buf, int len) +void pmac_format_nvram_partition (uint8_t *buf, int len) { char partition_name[12] = "wwwwwwwwwwww"; - + buf[0] = 0x7f; /* free partition magic */ buf[1] = 0; /* checksum */ buf[2] = len >> 8; buf[3] = len; memcpy(buf + 4, partition_name, 12); buf[1] = nvram_chksum(buf, 16); -} +} /* PowerPC CHRP hardware initialisation */ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, @@ -317,27 +327,20 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, /* init CPUs */ env = cpu_init(); - qemu_register_reset(&cpu_ppc_reset, env); - register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); - - /* Default CPU is a generic 74x/75x */ if (cpu_model == NULL) - cpu_model = "750"; - /* XXX: CPU model (or PVR) should be provided on command line */ - // ppc_find_by_name("750gx", &def); // Linux boot OK - // ppc_find_by_name("750fx", &def); // Linux boot OK - /* Linux does not boot on 750cxe (and probably other 750cx based) - * because it assumes it has 8 IBAT & DBAT pairs as it only have 4. - */ + cpu_model = "default"; ppc_find_by_name(cpu_model, &def); if (def == NULL) { cpu_abort(env, "Unable to find PowerPC CPU definition\n"); } for (i = 0; i < smp_cpus; i++) { cpu_ppc_register(env, def); + cpu_ppc_reset(env); /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); env->osi_call = vga_osi_call; + qemu_register_reset(&cpu_ppc_reset, env); + register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); envs[i] = env; } @@ -346,7 +349,9 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, /* allocate and load BIOS */ bios_offset = ram_size + vga_ram_size; - snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); + if (bios_name == NULL) + bios_name = BIOS_FILENAME; + snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); bios_size = load_image(buf, phys_ram_base + bios_offset); if (bios_size < 0 || bios_size > BIOS_SIZE) { cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf); @@ -355,7 +360,7 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, bios_size = (bios_size + 0xfff) & ~0xfff; cpu_register_physical_memory((uint32_t)(-bios_size), bios_size, bios_offset | IO_MEM_ROM); - + /* allocate and load VGA BIOS */ vga_bios_offset = bios_offset + bios_size; snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); @@ -371,12 +376,12 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, phys_ram_base[vga_bios_offset + 1] = 'D'; phys_ram_base[vga_bios_offset + 2] = 'R'; phys_ram_base[vga_bios_offset + 3] = 'V'; - cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4), + cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4), vga_bios_size); vga_bios_size += 8; } vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff; - + if (linux_boot) { kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ @@ -427,24 +432,24 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, /* XXX: suppress that */ dummy_irq = i8259_init(NULL); - + /* XXX: use Mac Serial port */ serial_init(0x3f8, dummy_irq[4], serial_hds[0]); - + for(i = 0; i < nb_nics; i++) { if (!nd_table[i].model) nd_table[i].model = "ne2k_pci"; pci_nic_init(pci_bus, &nd_table[i], -1); } - + pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); /* cuda also initialize ADB */ cuda_mem_index = cuda_init(pic[0x12]); - + adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); - + { MacIONVRAMState *nvr; nvr = macio_nvram_init(); @@ -488,6 +493,7 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; break; +#if defined(TARGET_PPC64) case PPC_FLAGS_INPUT_970: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = @@ -502,9 +508,9 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; break; +#endif /* defined(TARGET_PPC64) */ default: - cpu_abort(env, - "Only bus model not supported on mac99 machine\n"); + cpu_abort(env, "Bus model not supported on mac99 machine\n"); exit(1); } } @@ -534,14 +540,14 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, #endif /* cuda also initialize ADB */ cuda_mem_index = cuda_init(pic[0x19]); - + adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); - + macio_init(pci_bus, 0x0022); - + nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); - + arch_name = "MAC99"; } @@ -578,7 +584,7 @@ static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device, kernel_filename, kernel_cmdline, initrd_filename, cpu_model, 0); } - + static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot,