X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fppc.c;h=62e9e1b1e7cec4d3bf8b8253a11b9c295b31e633;hb=d0dfae6e91d9b2044523ed4db890860f898af86b;hp=c460fec48251d5c4211163adc5c0b305ab52bc66;hpb=4e588a4d0e1683488282658c057d4b44976d77d8;p=qemu diff --git a/hw/ppc.c b/hw/ppc.c index c460fec..62e9e1b 100644 --- a/hw/ppc.c +++ b/hw/ppc.c @@ -1,7 +1,7 @@ /* - * QEMU generic PPC hardware System Emulator + * QEMU generic PowerPC hardware System Emulator * - * Copyright (c) 2003-2004 Jocelyn Mayer + * Copyright (c) 2003-2007 Jocelyn Mayer * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -24,8 +24,364 @@ #include "vl.h" #include "m48t59.h" +//#define PPC_DEBUG_IRQ + +extern FILE *logfile; +extern int loglevel; + +void ppc_set_irq (CPUState *env, int n_IRQ, int level) +{ + if (level) { + env->pending_interrupts |= 1 << n_IRQ; + cpu_interrupt(env, CPU_INTERRUPT_HARD); + } else { + env->pending_interrupts &= ~(1 << n_IRQ); + if (env->pending_interrupts == 0) + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + } +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n", + __func__, env, n_IRQ, level, + env->pending_interrupts, env->interrupt_request); + } +#endif +} + +/* PowerPC 6xx / 7xx internal IRQ controller */ +static void ppc6xx_set_irq (void *opaque, int pin, int level) +{ + CPUState *env = opaque; + int cur_level; + +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, + env, pin, level); + } +#endif + cur_level = (env->irq_input_state >> pin) & 1; + /* Don't generate spurious events */ + if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { + switch (pin) { + case PPC6xx_INPUT_INT: + /* Level sensitive - active high */ +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: set the external IRQ state to %d\n", + __func__, level); + } +#endif + ppc_set_irq(env, PPC_INTERRUPT_EXT, level); + break; + case PPC6xx_INPUT_SMI: + /* Level sensitive - active high */ +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: set the SMI IRQ state to %d\n", + __func__, level); + } +#endif + ppc_set_irq(env, PPC_INTERRUPT_SMI, level); + break; + case PPC6xx_INPUT_MCP: + /* Negative edge sensitive */ + /* XXX: TODO: actual reaction may depends on HID0 status + * 603/604/740/750: check HID0[EMCP] + */ + if (cur_level == 1 && level == 0) { +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: raise machine check state\n", + __func__); + } +#endif + ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); + } + break; + case PPC6xx_INPUT_CKSTP_IN: + /* Level sensitive - active low */ + /* XXX: TODO: relay the signal to CKSTP_OUT pin */ + if (level) { +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: stop the CPU\n", __func__); + } +#endif + env->halted = 1; + } else { +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: restart the CPU\n", __func__); + } +#endif + env->halted = 0; + } + break; + case PPC6xx_INPUT_HRESET: + /* Level sensitive - active low */ + if (level) { +#if 0 // XXX: TOFIX +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: reset the CPU\n", __func__); + } +#endif + cpu_reset(env); +#endif + } + break; + case PPC6xx_INPUT_SRESET: +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: set the RESET IRQ state to %d\n", + __func__, level); + } +#endif + ppc_set_irq(env, PPC_INTERRUPT_RESET, level); + break; + default: + /* Unknown pin - do nothing */ +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); + } +#endif + return; + } + if (level) + env->irq_input_state |= 1 << pin; + else + env->irq_input_state &= ~(1 << pin); + } +} + +void ppc6xx_irq_init (CPUState *env) +{ + env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6); +} + +/* PowerPC 970 internal IRQ controller */ +static void ppc970_set_irq (void *opaque, int pin, int level) +{ + CPUState *env = opaque; + int cur_level; + +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, + env, pin, level); + } +#endif + cur_level = (env->irq_input_state >> pin) & 1; + /* Don't generate spurious events */ + if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { + switch (pin) { + case PPC970_INPUT_INT: + /* Level sensitive - active high */ +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: set the external IRQ state to %d\n", + __func__, level); + } +#endif + ppc_set_irq(env, PPC_INTERRUPT_EXT, level); + break; + case PPC970_INPUT_THINT: + /* Level sensitive - active high */ +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__, + level); + } +#endif + ppc_set_irq(env, PPC_INTERRUPT_THERM, level); + break; + case PPC970_INPUT_MCP: + /* Negative edge sensitive */ + /* XXX: TODO: actual reaction may depends on HID0 status + * 603/604/740/750: check HID0[EMCP] + */ + if (cur_level == 1 && level == 0) { +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: raise machine check state\n", + __func__); + } +#endif + ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); + } + break; + case PPC970_INPUT_CKSTP: + /* Level sensitive - active low */ + /* XXX: TODO: relay the signal to CKSTP_OUT pin */ + if (level) { +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: stop the CPU\n", __func__); + } +#endif + env->halted = 1; + } else { +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: restart the CPU\n", __func__); + } +#endif + env->halted = 0; + } + break; + case PPC970_INPUT_HRESET: + /* Level sensitive - active low */ + if (level) { +#if 0 // XXX: TOFIX +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: reset the CPU\n", __func__); + } +#endif + cpu_reset(env); +#endif + } + break; + case PPC970_INPUT_SRESET: +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: set the RESET IRQ state to %d\n", + __func__, level); + } +#endif + ppc_set_irq(env, PPC_INTERRUPT_RESET, level); + break; + case PPC970_INPUT_TBEN: +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: set the TBEN state to %d\n", __func__, + level); + } +#endif + /* XXX: TODO */ + break; + default: + /* Unknown pin - do nothing */ +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); + } +#endif + return; + } + if (level) + env->irq_input_state |= 1 << pin; + else + env->irq_input_state &= ~(1 << pin); + } +} + +void ppc970_irq_init (CPUState *env) +{ + env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7); +} + +/* PowerPC 405 internal IRQ controller */ +static void ppc405_set_irq (void *opaque, int pin, int level) +{ + CPUState *env = opaque; + int cur_level; + +#if defined(PPC_DEBUG_IRQ) + printf("%s: env %p pin %d level %d\n", __func__, env, pin, level); +#endif + cur_level = (env->irq_input_state >> pin) & 1; + /* Don't generate spurious events */ + if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { + switch (pin) { + case PPC405_INPUT_RESET_SYS: + /* XXX: TODO: reset all peripherals */ + /* No break here */ + case PPC405_INPUT_RESET_CHIP: + /* XXX: TODO: reset on-chip peripherals */ + /* No break here */ + case PPC405_INPUT_RESET_CORE: + /* XXX: TODO: update DBSR[MRR] */ + if (level) { +#if 0 // XXX: TOFIX +#if defined(PPC_DEBUG_IRQ) + printf("%s: reset the CPU\n", __func__); +#endif + cpu_reset(env); +#endif + } + break; + case PPC405_INPUT_CINT: + /* Level sensitive - active high */ +#if defined(PPC_DEBUG_IRQ) + printf("%s: set the critical IRQ state to %d\n", __func__, level); +#endif + /* XXX: TOFIX */ + ppc_set_irq(env, PPC_INTERRUPT_RESET, level); + break; + case PPC405_INPUT_INT: + /* Level sensitive - active high */ +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: set the external IRQ state to %d\n", + __func__, level); + } +#endif + ppc_set_irq(env, PPC_INTERRUPT_EXT, level); + break; + case PPC405_INPUT_HALT: + /* Level sensitive - active low */ + if (level) { +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: stop the CPU\n", __func__); + } +#endif + env->halted = 1; + } else { +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: restart the CPU\n", __func__); + } +#endif + env->halted = 0; + } + break; + case PPC405_INPUT_DEBUG: + /* Level sensitive - active high */ +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: set the external IRQ state to %d\n", + __func__, level); + } +#endif + ppc_set_irq(env, EXCP_40x_DEBUG, level); + break; + default: + /* Unknown pin - do nothing */ +#if defined(PPC_DEBUG_IRQ) + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); + } +#endif + return; + } + if (level) + env->irq_input_state |= 1 << pin; + else + env->irq_input_state &= ~(1 << pin); + } +} + +void ppc405_irq_init (CPUState *env) +{ + env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7); +} + /*****************************************************************************/ -/* PPC time base and decrementer emulation */ +/* PowerPC time base and decrementer emulation */ //#define DEBUG_TB struct ppc_tb_t { @@ -35,13 +391,14 @@ struct ppc_tb_t { /* Decrementer management */ uint64_t decr_next; /* Tick for next decr interrupt */ struct QEMUTimer *decr_timer; + void *opaque; }; static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env) { /* TB time in tb periods */ return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset, - tb_env->tb_freq, ticks_per_sec); + tb_env->tb_freq, ticks_per_sec); } uint32_t cpu_ppc_load_tbl (CPUState *env) @@ -52,14 +409,16 @@ uint32_t cpu_ppc_load_tbl (CPUState *env) tb = cpu_ppc_get_tb(tb_env); #ifdef DEBUG_TB { - static int last_time; - int now; - now = time(NULL); - if (last_time != now) { - last_time = now; - printf("%s: tb=0x%016lx %d %08lx\n", - __func__, tb, now, tb_env->tb_offset); - } + static int last_time; + int now; + now = time(NULL); + if (last_time != now) { + last_time = now; + if (loglevel) { + fprintf(logfile, "%s: tb=0x%016lx %d %08lx\n", + __func__, tb, now, tb_env->tb_offset); + } + } } #endif @@ -73,8 +432,11 @@ uint32_t cpu_ppc_load_tbu (CPUState *env) tb = cpu_ppc_get_tb(tb_env); #ifdef DEBUG_TB - printf("%s: tb=0x%016lx\n", __func__, tb); + if (loglevel) { + fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); + } #endif + return tb >> 32; } @@ -83,7 +445,9 @@ static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value) tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq) - qemu_get_clock(vm_clock); #ifdef DEBUG_TB - printf("%s: tb=0x%016lx offset=%08x\n", __func__, value); + if (loglevel) { + fprintf(logfile, "%s: tb=0x%016lx offset=%08x\n", __func__, value); + } #endif } @@ -115,8 +479,11 @@ uint32_t cpu_ppc_load_decr (CPUState *env) else decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec); #if defined(DEBUG_TB) - printf("%s: 0x%08x\n", __func__, decr); + if (loglevel) { + fprintf(logfile, "%s: 0x%08x\n", __func__, decr); + } #endif + return decr; } @@ -127,9 +494,11 @@ static inline void cpu_ppc_decr_excp (CPUState *env) { /* Raise it */ #ifdef DEBUG_TB - printf("raise decrementer exception\n"); + if (loglevel) { + fprintf(logfile, "raise decrementer exception\n"); + } #endif - cpu_interrupt(env, CPU_INTERRUPT_TIMER); + ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); } static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, @@ -139,14 +508,16 @@ static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, uint64_t now, next; #ifdef DEBUG_TB - printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value); + if (loglevel) { + fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value); + } #endif now = qemu_get_clock(vm_clock); next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq); if (is_excp) next += tb_env->decr_next - now; if (next == now) - next++; + next++; tb_env->decr_next = next; /* Adjust timer */ qemu_mod_timer(tb_env->decr_timer, next); @@ -154,7 +525,7 @@ static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, * raise an exception. */ if ((value & 0x80000000) && !(decr & 0x80000000)) - cpu_ppc_decr_excp(env); + cpu_ppc_decr_excp(env); } void cpu_ppc_store_decr (CPUState *env, uint32_t value) @@ -177,88 +548,371 @@ ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq) return NULL; env->tb_env = tb_env; if (tb_env->tb_freq == 0 || 1) { - tb_env->tb_freq = freq; - /* Create new timer */ - tb_env->decr_timer = + tb_env->tb_freq = freq; + /* Create new timer */ + tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); - /* There is a bug in 2.4 kernels: - * if a decrementer exception is pending when it enables msr_ee, - * it's not ready to handle it... - */ - _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); + /* There is a bug in Linux 2.4 kernels: + * if a decrementer exception is pending when it enables msr_ee, + * it's not ready to handle it... + */ + _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); } return tb_env; } -#if 0 +/* Specific helpers for POWER & PowerPC 601 RTC */ +ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env) +{ + return cpu_ppc_tb_init(env, 7812500); +} + +void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value) +__attribute__ (( alias ("cpu_ppc_store_tbu") )); + +uint32_t cpu_ppc601_load_rtcu (CPUState *env) +__attribute__ (( alias ("cpu_ppc_load_tbu") )); + +void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value) +{ + cpu_ppc_store_tbl(env, value & 0x3FFFFF80); +} + +uint32_t cpu_ppc601_load_rtcl (CPUState *env) +{ + return cpu_ppc_load_tbl(env) & 0x3FFFFF80; +} + /*****************************************************************************/ -/* Handle system reset (for now, just stop emulation) */ -void cpu_ppc_reset (CPUState *env) +/* Embedded PowerPC timers */ + +/* PIT, FIT & WDT */ +typedef struct ppcemb_timer_t ppcemb_timer_t; +struct ppcemb_timer_t { + uint64_t pit_reload; /* PIT auto-reload value */ + uint64_t fit_next; /* Tick for next FIT interrupt */ + struct QEMUTimer *fit_timer; + uint64_t wdt_next; /* Tick for next WDT interrupt */ + struct QEMUTimer *wdt_timer; +}; + +/* Fixed interval timer */ +static void cpu_4xx_fit_cb (void *opaque) { - printf("Reset asked... Stop emulation\n"); - abort(); + CPUState *env; + ppc_tb_t *tb_env; + ppcemb_timer_t *ppcemb_timer; + uint64_t now, next; + + env = opaque; + tb_env = env->tb_env; + ppcemb_timer = tb_env->opaque; + now = qemu_get_clock(vm_clock); + switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { + case 0: + next = 1 << 9; + break; + case 1: + next = 1 << 13; + break; + case 2: + next = 1 << 17; + break; + case 3: + next = 1 << 21; + break; + default: + /* Cannot occur, but makes gcc happy */ + return; + } + next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); + if (next == now) + next++; + qemu_mod_timer(ppcemb_timer->fit_timer, next); + tb_env->decr_next = next; + env->spr[SPR_40x_TSR] |= 1 << 26; + if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) + ppc_set_irq(env, PPC_INTERRUPT_FIT, 1); + if (loglevel) { + fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__, + (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), + env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); + } } -#endif -static void PPC_io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) +/* Programmable interval timer */ +static void cpu_4xx_pit_cb (void *opaque) { - cpu_outb(NULL, addr & 0xffff, value); + CPUState *env; + ppc_tb_t *tb_env; + ppcemb_timer_t *ppcemb_timer; + uint64_t now, next; + + env = opaque; + tb_env = env->tb_env; + ppcemb_timer = tb_env->opaque; + now = qemu_get_clock(vm_clock); + if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) { + /* Auto reload */ + next = now + muldiv64(ppcemb_timer->pit_reload, + ticks_per_sec, tb_env->tb_freq); + if (next == now) + next++; + qemu_mod_timer(tb_env->decr_timer, next); + tb_env->decr_next = next; + } + env->spr[SPR_40x_TSR] |= 1 << 27; + if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) + ppc_set_irq(env, PPC_INTERRUPT_PIT, 1); + if (loglevel) { + fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " " + "%016" PRIx64 "\n", __func__, + (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), + (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), + env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], + ppcemb_timer->pit_reload); + } } -static uint32_t PPC_io_readb (void *opaque, target_phys_addr_t addr) +/* Watchdog timer */ +static void cpu_4xx_wdt_cb (void *opaque) { - uint32_t ret = cpu_inb(NULL, addr & 0xffff); - return ret; + CPUState *env; + ppc_tb_t *tb_env; + ppcemb_timer_t *ppcemb_timer; + uint64_t now, next; + + env = opaque; + tb_env = env->tb_env; + ppcemb_timer = tb_env->opaque; + now = qemu_get_clock(vm_clock); + switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { + case 0: + next = 1 << 17; + break; + case 1: + next = 1 << 21; + break; + case 2: + next = 1 << 25; + break; + case 3: + next = 1 << 29; + break; + default: + /* Cannot occur, but makes gcc happy */ + return; + } + next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); + if (next == now) + next++; + if (loglevel) { + fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__, + env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); + } + switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { + case 0x0: + case 0x1: + qemu_mod_timer(ppcemb_timer->wdt_timer, next); + ppcemb_timer->wdt_next = next; + env->spr[SPR_40x_TSR] |= 1 << 31; + break; + case 0x2: + qemu_mod_timer(ppcemb_timer->wdt_timer, next); + ppcemb_timer->wdt_next = next; + env->spr[SPR_40x_TSR] |= 1 << 30; + if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) + ppc_set_irq(env, PPC_INTERRUPT_WDT, 1); + break; + case 0x3: + env->spr[SPR_40x_TSR] &= ~0x30000000; + env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; + switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { + case 0x0: + /* No reset */ + break; + case 0x1: /* Core reset */ + case 0x2: /* Chip reset */ + case 0x3: /* System reset */ + qemu_system_reset_request(); + return; + } + } } -static void PPC_io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) +void store_40x_pit (CPUState *env, target_ulong val) { -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap16(value); -#endif - cpu_outw(NULL, addr & 0xffff, value); + ppc_tb_t *tb_env; + ppcemb_timer_t *ppcemb_timer; + uint64_t now, next; + + tb_env = env->tb_env; + ppcemb_timer = tb_env->opaque; + if (loglevel) { + fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer); + } + ppcemb_timer->pit_reload = val; + if (val == 0) { + /* Stop PIT */ + if (loglevel) { + fprintf(logfile, "%s: stop PIT\n", __func__); + } + qemu_del_timer(tb_env->decr_timer); + } else { + if (loglevel) { + fprintf(logfile, "%s: start PIT 0x" ADDRX "\n", __func__, val); + } + now = qemu_get_clock(vm_clock); + next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq); + if (next == now) + next++; + qemu_mod_timer(tb_env->decr_timer, next); + tb_env->decr_next = next; + } } -static uint32_t PPC_io_readw (void *opaque, target_phys_addr_t addr) +target_ulong load_40x_pit (CPUState *env) { - uint32_t ret = cpu_inw(NULL, addr & 0xffff); -#ifdef TARGET_WORDS_BIGENDIAN - ret = bswap16(ret); -#endif - return ret; + return cpu_ppc_load_decr(env); } -static void PPC_io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +void store_booke_tsr (CPUState *env, target_ulong val) { -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap32(value); -#endif - cpu_outl(NULL, addr & 0xffff, value); + env->spr[SPR_40x_TSR] = val & 0xFC000000; } -static uint32_t PPC_io_readl (void *opaque, target_phys_addr_t addr) +void store_booke_tcr (CPUState *env, target_ulong val) { - uint32_t ret = cpu_inl(NULL, addr & 0xffff); + /* We don't update timers now. Maybe we should... */ + env->spr[SPR_40x_TCR] = val & 0xFF800000; +} -#ifdef TARGET_WORDS_BIGENDIAN - ret = bswap32(ret); -#endif - return ret; +void ppc_emb_timers_init (CPUState *env) +{ + ppc_tb_t *tb_env; + ppcemb_timer_t *ppcemb_timer; + + tb_env = env->tb_env; + ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t)); + tb_env->opaque = ppcemb_timer; + if (loglevel) + fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer); + if (ppcemb_timer != NULL) { + /* We use decr timer for PIT */ + tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); + ppcemb_timer->fit_timer = + qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); + ppcemb_timer->wdt_timer = + qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); + } } -CPUWriteMemoryFunc *PPC_io_write[] = { - &PPC_io_writeb, - &PPC_io_writew, - &PPC_io_writel, +/*****************************************************************************/ +/* Embedded PowerPC Device Control Registers */ +typedef struct ppc_dcrn_t ppc_dcrn_t; +struct ppc_dcrn_t { + dcr_read_cb dcr_read; + dcr_write_cb dcr_write; + void *opaque; }; -CPUReadMemoryFunc *PPC_io_read[] = { - &PPC_io_readb, - &PPC_io_readw, - &PPC_io_readl, +#define DCRN_NB 1024 +struct ppc_dcr_t { + ppc_dcrn_t dcrn[DCRN_NB]; + int (*read_error)(int dcrn); + int (*write_error)(int dcrn); }; +int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) +{ + ppc_dcrn_t *dcr; + + if (dcrn < 0 || dcrn >= DCRN_NB) + goto error; + dcr = &dcr_env->dcrn[dcrn]; + if (dcr->dcr_read == NULL) + goto error; + *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); + + return 0; + + error: + if (dcr_env->read_error != NULL) + return (*dcr_env->read_error)(dcrn); + + return -1; +} + +int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) +{ + ppc_dcrn_t *dcr; + + if (dcrn < 0 || dcrn >= DCRN_NB) + goto error; + dcr = &dcr_env->dcrn[dcrn]; + if (dcr->dcr_write == NULL) + goto error; + (*dcr->dcr_write)(dcr->opaque, dcrn, val); + + return 0; + + error: + if (dcr_env->write_error != NULL) + return (*dcr_env->write_error)(dcrn); + + return -1; +} + +int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, + dcr_read_cb dcr_read, dcr_write_cb dcr_write) +{ + ppc_dcr_t *dcr_env; + ppc_dcrn_t *dcr; + + dcr_env = env->dcr_env; + if (dcr_env == NULL) + return -1; + if (dcrn < 0 || dcrn >= DCRN_NB) + return -1; + dcr = &dcr_env->dcrn[dcrn]; + if (dcr->opaque != NULL || + dcr->dcr_read != NULL || + dcr->dcr_write != NULL) + return -1; + dcr->opaque = opaque; + dcr->dcr_read = dcr_read; + dcr->dcr_write = dcr_write; + + return 0; +} + +int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), + int (*write_error)(int dcrn)) +{ + ppc_dcr_t *dcr_env; + + dcr_env = qemu_mallocz(sizeof(ppc_dcr_t)); + if (dcr_env == NULL) + return -1; + dcr_env->read_error = read_error; + dcr_env->write_error = write_error; + env->dcr_env = dcr_env; + + return 0; +} + + +#if 0 +/*****************************************************************************/ +/* Handle system reset (for now, just stop emulation) */ +void cpu_ppc_reset (CPUState *env) +{ + printf("Reset asked... Stop emulation\n"); + abort(); +} +#endif + /*****************************************************************************/ /* Debug port */ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) @@ -283,60 +937,45 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) /* NVRAM helpers */ void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value) { - m48t59_set_addr(nvram, addr); - m48t59_write(nvram, value); + m48t59_write(nvram, addr, value); } uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) { - m48t59_set_addr(nvram, addr); - return m48t59_read(nvram); + return m48t59_read(nvram, addr); } void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value) { - m48t59_set_addr(nvram, addr); - m48t59_write(nvram, value >> 8); - m48t59_set_addr(nvram, addr + 1); - m48t59_write(nvram, value & 0xFF); + m48t59_write(nvram, addr, value >> 8); + m48t59_write(nvram, addr + 1, value & 0xFF); } uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) { uint16_t tmp; - m48t59_set_addr(nvram, addr); - tmp = m48t59_read(nvram) << 8; - m48t59_set_addr(nvram, addr + 1); - tmp |= m48t59_read(nvram); - + tmp = m48t59_read(nvram, addr) << 8; + tmp |= m48t59_read(nvram, addr + 1); return tmp; } void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value) { - m48t59_set_addr(nvram, addr); - m48t59_write(nvram, value >> 24); - m48t59_set_addr(nvram, addr + 1); - m48t59_write(nvram, (value >> 16) & 0xFF); - m48t59_set_addr(nvram, addr + 2); - m48t59_write(nvram, (value >> 8) & 0xFF); - m48t59_set_addr(nvram, addr + 3); - m48t59_write(nvram, value & 0xFF); + m48t59_write(nvram, addr, value >> 24); + m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF); + m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF); + m48t59_write(nvram, addr + 3, value & 0xFF); } uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) { uint32_t tmp; - m48t59_set_addr(nvram, addr); - tmp = m48t59_read(nvram) << 24; - m48t59_set_addr(nvram, addr + 1); - tmp |= m48t59_read(nvram) << 16; - m48t59_set_addr(nvram, addr + 2); - tmp |= m48t59_read(nvram) << 8; - m48t59_set_addr(nvram, addr + 3); - tmp |= m48t59_read(nvram); + tmp = m48t59_read(nvram, addr) << 24; + tmp |= m48t59_read(nvram, addr + 1) << 16; + tmp |= m48t59_read(nvram, addr + 2) << 8; + tmp |= m48t59_read(nvram, addr + 3); return tmp; } @@ -347,11 +986,9 @@ void NVRAM_set_string (m48t59_t *nvram, uint32_t addr, int i; for (i = 0; i < max && str[i] != '\0'; i++) { - m48t59_set_addr(nvram, addr + i); - m48t59_write(nvram, str[i]); + m48t59_write(nvram, addr + i, str[i]); } - m48t59_set_addr(nvram, addr + max - 1); - m48t59_write(nvram, '\0'); + m48t59_write(nvram, addr + max - 1, '\0'); } int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) @@ -392,10 +1029,10 @@ uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) odd = count & 1; count &= ~1; for (i = 0; i != count; i++) { - crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); + crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); } if (odd) { - crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); + crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); } return crc;