X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fmips_timer.c;h=b295bdbfeb812bc1d98df2b3c723b68fbc59ab73;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=251324d7b8fab7ecd93fa54292d2470bc2912e5e;hpb=e16fe40c87272f0bc081b5a915db54eab2dc74dc;p=qemu

diff --git a/hw/mips_timer.c b/hw/mips_timer.c
index 251324d..b295bdb 100644
--- a/hw/mips_timer.c
+++ b/hw/mips_timer.c
@@ -10,23 +10,26 @@ uint32_t cpu_mips_get_random (CPUState *env)
     static uint32_t seed = 0;
     uint32_t idx;
     seed = seed * 314159 + 1;
-    idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
+    idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
     return idx;
 }
 
 /* MIPS R4K timer */
 uint32_t cpu_mips_get_count (CPUState *env)
 {
-    return env->CP0_Count +
-        (uint32_t)muldiv64(qemu_get_clock(vm_clock),
-                           100 * 1000 * 1000, ticks_per_sec);
+    if (env->CP0_Cause & (1 << CP0Ca_DC))
+        return env->CP0_Count;
+    else
+        return env->CP0_Count +
+            (uint32_t)muldiv64(qemu_get_clock(vm_clock),
+                               100 * 1000 * 1000, ticks_per_sec);
 }
 
-static void cpu_mips_update_count (CPUState *env, uint32_t count,
-                                   uint32_t compare)
+void cpu_mips_store_count (CPUState *env, uint32_t count)
 {
     uint64_t now, next;
     uint32_t tmp;
+    uint32_t compare = env->CP0_Compare;
 
     tmp = count;
     if (count == compare)
@@ -49,16 +52,33 @@ static void cpu_mips_update_count (CPUState *env, uint32_t count,
     qemu_mod_timer(env->timer, next);
 }
 
-void cpu_mips_store_count (CPUState *env, uint32_t value)
+static void cpu_mips_update_count (CPUState *env, uint32_t count)
 {
-    cpu_mips_update_count(env, value, env->CP0_Compare);
+    if (env->CP0_Cause & (1 << CP0Ca_DC))
+        return;
+
+    cpu_mips_store_count(env, count);
 }
 
 void cpu_mips_store_compare (CPUState *env, uint32_t value)
 {
-    cpu_mips_update_count(env, cpu_mips_get_count(env), value);
-    env->CP0_Cause &= ~0x00008000;
-    cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+    env->CP0_Compare = value;
+    cpu_mips_update_count(env, cpu_mips_get_count(env));
+    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
+        env->CP0_Cause &= ~(1 << CP0Ca_TI);
+    qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+}
+
+void cpu_mips_start_count(CPUState *env)
+{
+    cpu_mips_store_count(env, env->CP0_Count);
+}
+
+void cpu_mips_stop_count(CPUState *env)
+{
+    /* Store the current value */
+    env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock),
+                                         100 * 1000 * 1000, ticks_per_sec);
 }
 
 static void mips_timer_cb (void *opaque)
@@ -71,15 +91,19 @@ static void mips_timer_cb (void *opaque)
         fprintf(logfile, "%s\n", __func__);
     }
 #endif
-    cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
-    env->CP0_Cause |= 0x00008000;
-    cpu_interrupt(env, CPU_INTERRUPT_HARD);
+
+    if (env->CP0_Cause & (1 << CP0Ca_DC))
+        return;
+
+    cpu_mips_update_count(env, cpu_mips_get_count(env));
+    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
+        env->CP0_Cause |= 1 << CP0Ca_TI;
+    qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
 }
 
 void cpu_mips_clock_init (CPUState *env)
 {
     env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
     env->CP0_Compare = 0;
-    cpu_mips_update_count(env, 1, 0);
+    cpu_mips_update_count(env, 1);
 }
-