X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fmips_r4k.c;h=ce7aaff9dfd5299be8928b9a41367669cbfbf666;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=22d742a2e3628e5011e15940d8cde404bfbd3a44;hpb=26a76461f259031f2c30cd5843a5ca91e056cf03;p=qemu diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c index 22d742a..ce7aaff 100644 --- a/hw/mips_r4k.c +++ b/hw/mips_r4k.c @@ -1,222 +1,191 @@ +/* + * QEMU/MIPS pseudo-board + * + * emulates a simple machine with ISA-like bus. + * ISA IO space mapped to the 0x14000000 (PHYS) and + * ISA memory at the 0x10000000 (PHYS, 16Mb in size). + * All peripherial devices are attached to this "bus" with + * the standard PC ISA addresses. +*/ #include "vl.h" +#ifdef TARGET_WORDS_BIGENDIAN #define BIOS_FILENAME "mips_bios.bin" -//#define BIOS_FILENAME "system.bin" -#define KERNEL_LOAD_ADDR 0x80010000 -#define INITRD_LOAD_ADDR 0x80800000 - -#define VIRT_TO_PHYS_ADDEND (-0x80000000LL) +#else +#define BIOS_FILENAME "mipsel_bios.bin" +#endif -extern FILE *logfile; +#ifdef TARGET_MIPS64 +#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) +#else +#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) +#endif -static PITState *pit; +#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) -static void pic_irq_request(void *opaque, int level) -{ - CPUState *env = first_cpu; - if (level) { - env->CP0_Cause |= 0x00000400; - cpu_interrupt(env, CPU_INTERRUPT_HARD); - } else { - env->CP0_Cause &= ~0x00000400; - cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); - } -} +static const int ide_iobase[2] = { 0x1f0, 0x170 }; +static const int ide_iobase2[2] = { 0x3f6, 0x376 }; +static const int ide_irq[2] = { 14, 15 }; -void cpu_mips_irqctrl_init (void) -{ -} +static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; +static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; -/* XXX: do not use a global */ -uint32_t cpu_mips_get_random (CPUState *env) -{ - static uint32_t seed = 0; - uint32_t idx; - seed = seed * 314159 + 1; - idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired; - return idx; -} +extern FILE *logfile; -/* MIPS R4K timer */ -uint32_t cpu_mips_get_count (CPUState *env) -{ - return env->CP0_Count + - (uint32_t)muldiv64(qemu_get_clock(vm_clock), - 100 * 1000 * 1000, ticks_per_sec); -} +static PITState *pit; /* PIT i8254 */ -static void cpu_mips_update_count (CPUState *env, uint32_t count, - uint32_t compare) -{ - uint64_t now, next; - uint32_t tmp; - - tmp = count; - if (count == compare) - tmp++; - now = qemu_get_clock(vm_clock); - next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); - if (next == now) - next++; -#if 0 - if (logfile) { - fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n", - __func__, now, count, compare, next - now); - } -#endif - /* Store new count and compare registers */ - env->CP0_Compare = compare; - env->CP0_Count = - count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); - /* Adjust timer */ - qemu_mod_timer(env->timer, next); -} +/*i8254 PIT is attached to the IRQ0 at PIC i8259 */ -void cpu_mips_store_count (CPUState *env, uint32_t value) +static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, + uint32_t val) { - cpu_mips_update_count(env, value, env->CP0_Compare); + if ((addr & 0xffff) == 0 && val == 42) + qemu_system_reset_request (); + else if ((addr & 0xffff) == 4 && val == 42) + qemu_system_shutdown_request (); } -void cpu_mips_store_compare (CPUState *env, uint32_t value) +static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) { - cpu_mips_update_count(env, cpu_mips_get_count(env), value); - env->CP0_Cause &= ~0x00008000; - cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + return 0; } -static void mips_timer_cb (void *opaque) -{ - CPUState *env; - - env = opaque; -#if 0 - if (logfile) { - fprintf(logfile, "%s\n", __func__); - } -#endif - cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); - env->CP0_Cause |= 0x00008000; - cpu_interrupt(env, CPU_INTERRUPT_HARD); -} +static CPUWriteMemoryFunc *mips_qemu_write[] = { + &mips_qemu_writel, + &mips_qemu_writel, + &mips_qemu_writel, +}; -void cpu_mips_clock_init (CPUState *env) -{ - env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); - env->CP0_Compare = 0; - cpu_mips_update_count(env, 1, 0); -} +static CPUReadMemoryFunc *mips_qemu_read[] = { + &mips_qemu_readl, + &mips_qemu_readl, + &mips_qemu_readl, +}; +static int mips_qemu_iomemtype = 0; -static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) +static void load_kernel (CPUState *env, int ram_size, + const char *kernel_filename, + const char *kernel_cmdline, + const char *initrd_filename) { -#if 0 - if (logfile) - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); -#endif - cpu_outb(NULL, addr & 0xffff, value); -} + int64_t entry, kernel_low, kernel_high; + long kernel_size, initrd_size; + ram_addr_t initrd_offset; -static uint32_t io_readb (void *opaque, target_phys_addr_t addr) -{ - uint32_t ret = cpu_inb(NULL, addr & 0xffff); -#if 0 - if (logfile) - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); -#endif - return ret; -} + kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, + &entry, &kernel_low, &kernel_high); + if (kernel_size >= 0) { + if ((entry & ~0x7fffffffULL) == 0x80000000) + entry = (int32_t)entry; + env->PC[env->current_tc] = entry; + } else { + fprintf(stderr, "qemu: could not load kernel '%s'\n", + kernel_filename); + exit(1); + } -static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) -{ -#if 0 - if (logfile) - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); -#endif -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap16(value); -#endif - cpu_outw(NULL, addr & 0xffff, value); -} + /* load initrd */ + initrd_size = 0; + initrd_offset = 0; + if (initrd_filename) { + initrd_size = get_image_size (initrd_filename); + if (initrd_size > 0) { + initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; + if (initrd_offset + initrd_size > ram_size) { + fprintf(stderr, + "qemu: memory too small for initial ram disk '%s'\n", + initrd_filename); + exit(1); + } + initrd_size = load_image(initrd_filename, + phys_ram_base + initrd_offset); + } + if (initrd_size == (target_ulong) -1) { + fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", + initrd_filename); + exit(1); + } + } -static uint32_t io_readw (void *opaque, target_phys_addr_t addr) -{ - uint32_t ret = cpu_inw(NULL, addr & 0xffff); -#ifdef TARGET_WORDS_BIGENDIAN - ret = bswap16(ret); -#endif -#if 0 - if (logfile) - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); -#endif - return ret; -} + /* Store command line. */ + if (initrd_size > 0) { + int ret; + ret = sprintf(phys_ram_base + (16 << 20) - 256, + "rd_start=0x" TARGET_FMT_lx " rd_size=%li ", + PHYS_TO_VIRT((uint32_t)initrd_offset), + initrd_size); + strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline); + } + else { + strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); + } -static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) -{ -#if 0 - if (logfile) - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); -#endif -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap32(value); -#endif - cpu_outl(NULL, addr & 0xffff, value); + *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); + *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); } -static uint32_t io_readl (void *opaque, target_phys_addr_t addr) +static void main_cpu_reset(void *opaque) { - uint32_t ret = cpu_inl(NULL, addr & 0xffff); + CPUState *env = opaque; + cpu_reset(env); + cpu_mips_register(env, NULL); -#ifdef TARGET_WORDS_BIGENDIAN - ret = bswap32(ret); -#endif -#if 0 - if (logfile) - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); -#endif - return ret; + if (env->kernel_filename) + load_kernel (env, env->ram_size, env->kernel_filename, + env->kernel_cmdline, env->initrd_filename); } -CPUWriteMemoryFunc *io_write[] = { - &io_writeb, - &io_writew, - &io_writel, -}; - -CPUReadMemoryFunc *io_read[] = { - &io_readb, - &io_readw, - &io_readl, -}; - +static void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename) + const char *initrd_filename, const char *cpu_model) { char buf[1024]; - int64_t entry = 0; unsigned long bios_offset; - int io_memory; - int ret; + int bios_size; CPUState *env; - long kernel_size; - + RTCState *rtc_state; + int i; + mips_def_t *def; + qemu_irq *i8259; + + /* init CPUs */ + if (cpu_model == NULL) { +#ifdef TARGET_MIPS64 + cpu_model = "R4000"; +#else + cpu_model = "24Kf"; +#endif + } + if (mips_find_by_name(cpu_model, &def) != 0) + def = NULL; env = cpu_init(); + cpu_mips_register(env, def); register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); + qemu_register_reset(main_cpu_reset, env); /* allocate RAM */ cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); + if (!mips_qemu_iomemtype) { + mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read, + mips_qemu_write, NULL); + } + cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); + /* Try to load a BIOS image. If this fails, we continue regardless, but initialize the hardware ourselves. When a kernel gets preloaded we also initialize the hardware, since the BIOS wasn't run. */ bios_offset = ram_size + vga_ram_size; - snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); - ret = load_image(buf, phys_ram_base + bios_offset); - if (ret == BIOS_SIZE) { - cpu_register_physical_memory((uint32_t)(0x1fc00000), + if (bios_name == NULL) + bios_name = BIOS_FILENAME; + snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); + bios_size = load_image(buf, phys_ram_base + bios_offset); + if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { + cpu_register_physical_memory(0x1fc00000, BIOS_SIZE, bios_offset | IO_MEM_ROM); } else { /* not fatal */ @@ -224,64 +193,59 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, buf); } - kernel_size = 0; if (kernel_filename) { - kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry); - if (kernel_size >= 0) - env->PC = entry; - else { - kernel_size = load_image(kernel_filename, - phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND); - if (kernel_size < 0) { - fprintf(stderr, "qemu: could not load kernel '%s'\n", - kernel_filename); - exit(1); - } - env->PC = KERNEL_LOAD_ADDR; - } - - /* load initrd */ - if (initrd_filename) { - if (load_image(initrd_filename, - phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND) - == (target_ulong) -1) { - fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", - initrd_filename); - exit(1); - } - } - - /* Store command line. */ - strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); - /* FIXME: little endian support */ - *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); - *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); + load_kernel (env, ram_size, kernel_filename, kernel_cmdline, + initrd_filename); + env->ram_size = ram_size; + env->kernel_filename = kernel_filename; + env->kernel_cmdline = kernel_cmdline; + env->initrd_filename = initrd_filename; } - /* Init internal devices */ + /* Init CPU internal devices */ + cpu_mips_irq_init_cpu(env); cpu_mips_clock_init(env); cpu_mips_irqctrl_init(); + /* The PIC is attached to the MIPS CPU INT0 pin */ + i8259 = i8259_init(env->irq[2]); + + rtc_state = rtc_init(0x70, i8259[8]); + /* Register 64 KB of ISA IO space at 0x14000000 */ - io_memory = cpu_register_io_memory(0, io_read, io_write, NULL); - cpu_register_physical_memory(0x14000000, 0x00010000, io_memory); + isa_mmio_init(0x14000000, 0x00010000); isa_mem_base = 0x10000000; - isa_pic = pic_init(pic_irq_request, env); - pit = pit_init(0x40, 0); - serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); - vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size, - vga_ram_size, 0, 0); + pit = pit_init(0x40, i8259[0]); + + for(i = 0; i < MAX_SERIAL_PORTS; i++) { + if (serial_hds[i]) { + serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]); + } + } + + isa_vga_init(ds, phys_ram_base + ram_size, ram_size, + vga_ram_size); if (nd_table[0].vlan) { if (nd_table[0].model == NULL || strcmp(nd_table[0].model, "ne2k_isa") == 0) { - isa_ne2000_init(0x300, 9, &nd_table[0]); + isa_ne2000_init(0x300, i8259[9], &nd_table[0]); + } else if (strcmp(nd_table[0].model, "?") == 0) { + fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n"); + exit (1); } else { fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); exit (1); } } + + for(i = 0; i < 2; i++) + isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], + bs_table[2 * i], bs_table[2 * i + 1]); + + i8042_init(i8259[1], i8259[12], 0x60); + ds1225y_init(0x9000, "nvram"); } QEMUMachine mips_machine = {