X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fmips_int.c;h=f4e22dcf858fd61faf30f34ac682cb1d27d9397c;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=b384b64d285be43b06ef77ced1d25fdc562efa1c;hpb=24c7b0e330fdbfcfe87f515d79e67156c57cbc4f;p=qemu

diff --git a/hw/mips_int.c b/hw/mips_int.c
index b384b64..f4e22dc 100644
--- a/hw/mips_int.c
+++ b/hw/mips_int.c
@@ -17,7 +17,7 @@ void cpu_mips_update_irq(CPUState *env)
         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 }
 
-void cpu_mips_irq_request(void *opaque, int irq, int level)
+static void cpu_mips_irq_request(void *opaque, int irq, int level)
 {
     CPUState *env = (CPUState *)opaque;
 
@@ -27,7 +27,18 @@ void cpu_mips_irq_request(void *opaque, int irq, int level)
     if (level) {
         env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
     } else {
-        env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP));
+        env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
     }
     cpu_mips_update_irq(env);
 }
+
+void cpu_mips_irq_init_cpu(CPUState *env)
+{
+    qemu_irq *qi;
+    int i;
+
+    qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
+    for (i = 0; i < 8; i++) {
+        env->irq[i] = qi[i];
+    }
+}