X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fmips_int.c;h=f4e22dcf858fd61faf30f34ac682cb1d27d9397c;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=7f9f15305b4e13c662472a0b9847cfd47eeb17e6;hpb=39d51eb8bcc603c02342d8f5e1f7a569e5f17e06;p=qemu

diff --git a/hw/mips_int.c b/hw/mips_int.c
index 7f9f153..f4e22dc 100644
--- a/hw/mips_int.c
+++ b/hw/mips_int.c
@@ -5,20 +5,19 @@
    IRQ may change */
 void cpu_mips_update_irq(CPUState *env)
 {
-    if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
-        (env->CP0_Status & (1 << CP0St_IE)) &&
-        !(env->hflags & MIPS_HFLAG_EXL) &&
-	!(env->hflags & MIPS_HFLAG_ERL) &&
-	!(env->hflags & MIPS_HFLAG_DM)) {
-        if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) {
+    if ((env->CP0_Status & (1 << CP0St_IE)) &&
+        !(env->CP0_Status & (1 << CP0St_EXL)) &&
+        !(env->CP0_Status & (1 << CP0St_ERL)) &&
+        !(env->hflags & MIPS_HFLAG_DM)) {
+        if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
+            !(env->interrupt_request & CPU_INTERRUPT_HARD)) {
             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 	}
-    } else {
+    } else
         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
-    }
 }
 
-void cpu_mips_irq_request(void *opaque, int irq, int level)
+static void cpu_mips_irq_request(void *opaque, int irq, int level)
 {
     CPUState *env = (CPUState *)opaque;
 
@@ -28,7 +27,18 @@ void cpu_mips_irq_request(void *opaque, int irq, int level)
     if (level) {
         env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
     } else {
-        env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP));
+        env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
     }
     cpu_mips_update_irq(env);
 }
+
+void cpu_mips_irq_init_cpu(CPUState *env)
+{
+    qemu_irq *qi;
+    int i;
+
+    qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
+    for (i = 0; i < 8; i++) {
+        env->irq[i] = qi[i];
+    }
+}