X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Fesp.c;h=10d4cadf24d209e7287b445af57c1e438bfde6d5;hb=2d069bab6ad7f8c74e49715f7c534e8e799c9855;hp=627d90cabd48911371dc4cf6d6fb82875c7c8102;hpb=5aca8c3b2fbada188ff86781fba24685d346cef9;p=qemu diff --git a/hw/esp.c b/hw/esp.c index 627d90c..10d4cad 100644 --- a/hw/esp.c +++ b/hw/esp.c @@ -51,6 +51,7 @@ do { printf("ESP: " fmt , ##args); } while (0) typedef struct ESPState ESPState; struct ESPState { + qemu_irq irq; BlockDriverState **bd; uint8_t rregs[ESP_REGS]; uint8_t wregs[ESP_REGS]; @@ -126,7 +127,7 @@ static int get_cmd(ESPState *s, uint8_t *buf) s->rregs[4] = STAT_IN; s->rregs[5] = INTR_DC; s->rregs[6] = SEQ_0; - espdma_raise_irq(s->dma_opaque); + qemu_irq_raise(s->irq); return 0; } s->current_dev = s->scsi_dev[target]; @@ -156,7 +157,7 @@ static void do_cmd(ESPState *s, uint8_t *buf) } s->rregs[5] = INTR_BS | INTR_FC; s->rregs[6] = SEQ_CD; - espdma_raise_irq(s->dma_opaque); + qemu_irq_raise(s->irq); } static void handle_satn(ESPState *s) @@ -178,7 +179,7 @@ static void handle_satn_stop(ESPState *s) s->rregs[4] = STAT_IN | STAT_TC | STAT_CD; s->rregs[5] = INTR_BS | INTR_FC; s->rregs[6] = SEQ_CD; - espdma_raise_irq(s->dma_opaque); + qemu_irq_raise(s->irq); } } @@ -198,7 +199,7 @@ static void write_response(ESPState *s) s->ti_wptr = 0; s->rregs[7] = 2; } - espdma_raise_irq(s->dma_opaque); + qemu_irq_raise(s->irq); } static void esp_dma_done(ESPState *s) @@ -209,7 +210,7 @@ static void esp_dma_done(ESPState *s) s->rregs[7] = 0; s->rregs[0] = 0; s->rregs[1] = 0; - espdma_raise_irq(s->dma_opaque); + qemu_irq_raise(s->irq); } static void esp_do_dma(ESPState *s) @@ -343,6 +344,12 @@ static void esp_reset(void *opaque) s->do_cmd = 0; } +static void parent_esp_reset(void *opaque, int irq, int level) +{ + if (level) + esp_reset(opaque); +} + static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) { ESPState *s = opaque; @@ -362,7 +369,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) } else { s->rregs[2] = s->ti_buf[s->ti_rptr++]; } - espdma_raise_irq(s->dma_opaque); + qemu_irq_raise(s->irq); } if (s->ti_size == 0) { s->ti_rptr = 0; @@ -373,7 +380,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) // interrupt // Clear interrupt/error status bits s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE); - espdma_clear_irq(s->dma_opaque); + qemu_irq_lower(s->irq); break; default: break; @@ -436,7 +443,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) DPRINTF("Bus reset (%2.2x)\n", val); s->rregs[5] = INTR_RST; if (!(s->wregs[8] & 0x40)) { - espdma_raise_irq(s->dma_opaque); + qemu_irq_raise(s->irq); } break; case 0x10: @@ -463,6 +470,9 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) DPRINTF("Set ATN & stop (%2.2x)\n", val); handle_satn_stop(s); break; + case 0x44: + DPRINTF("Enable selection (%2.2x)\n", val); + break; default: DPRINTF("Unhandled ESP command (%2.2x)\n", val); break; @@ -565,7 +575,7 @@ void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id) } void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr, - void *dma_opaque) + void *dma_opaque, qemu_irq irq, qemu_irq *reset) { ESPState *s; int esp_io_memory; @@ -575,8 +585,8 @@ void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr, return NULL; s->bd = bd; + s->irq = irq; s->dma_opaque = dma_opaque; - sparc32_dma_set_reset_data(dma_opaque, esp_reset, s); esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s); cpu_register_physical_memory(espaddr, ESP_SIZE, esp_io_memory); @@ -586,5 +596,7 @@ void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr, register_savevm("esp", espaddr, 3, esp_save, esp_load, s); qemu_register_reset(esp_reset, s); + *reset = *qemu_allocate_irqs(parent_esp_reset, s, 1); + return s; }