X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;f=hw%2Farm_gic.c;h=8cd7182cff12b422324070ee8625aedb7ccd18b9;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=250efad3603f34d6263f5a40e536ce7f1689947e;hpb=187337f8b0ec0813dd3876d1efe37d415fb81c2e;p=qemu

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 250efad..8cd7182 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * ARM AMBA Generic/Distributed Interrupt Controller
  *
  * Copyright (c) 2006 CodeSourcery.
@@ -115,7 +115,7 @@ static void gic_set_irq(void *opaque, int irq, int level)
     gic_state *s = (gic_state *)opaque;
     /* The first external input line is internal interrupt 32.  */
     irq += 32;
-    if (level == GIC_TEST_LEVEL(irq)) 
+    if (level == GIC_TEST_LEVEL(irq))
         return;
 
     if (level) {
@@ -460,7 +460,7 @@ static uint32_t gic_cpu_read(void *opaque, target_phys_addr_t offset)
     case 0x18: /* Highest Pending Interrupt */
         return s->current_pending;
     default:
-        cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "gic_cpu_read: Bad offset %x\n", offset);
         return 0;
     }
 }
@@ -484,7 +484,7 @@ static void gic_cpu_write(void *opaque, target_phys_addr_t offset,
     case 0x10: /* End Of Interrupt */
         return gic_complete_irq(s, value & 0x3ff);
     default:
-        cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "gic_cpu_write: Bad offset %x\n", offset);
         return;
     }
     gic_update(s);