X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;ds=sidebyside;f=hw%2Fsh7750_regs.h;h=c8fb328100227485cf410bb6fafb47fffc8c9988;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=85eab431237836eebef68fcc135c36d6c681d877;hpb=cd1a3f6840e9f4b57860ee0d151347e6ade73d11;p=qemu diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h index 85eab43..c8fb328 100644 --- a/hw/sh7750_regs.h +++ b/hw/sh7750_regs.h @@ -1169,231 +1169,6 @@ #define SH7750_DMAOR_DME 0x00000001 /* DMAC Master Enable */ /* - * Serial Communication Interface - SCI - * Serial Communication Interface with FIFO - SCIF - */ -/* SCI Receive Data Register (byte, read-only) - SCRDR1, SCFRDR2 */ -#define SH7750_SCRDR_REGOFS(n) ((n) == 1 ? 0xE00014 : 0xE80014) /* offset */ -#define SH7750_SCRDR(n) SH7750_P4_REG32(SH7750_SCRDR_REGOFS(n)) -#define SH7750_SCRDR1 SH7750_SCRDR(1) -#define SH7750_SCRDR2 SH7750_SCRDR(2) -#define SH7750_SCRDR_A7(n) SH7750_A7_REG32(SH7750_SCRDR_REGOFS(n)) -#define SH7750_SCRDR1_A7 SH7750_SCRDR_A7(1) -#define SH7750_SCRDR2_A7 SH7750_SCRDR_A7(2) - -/* SCI Transmit Data Register (byte) - SCTDR1, SCFTDR2 */ -#define SH7750_SCTDR_REGOFS(n) ((n) == 1 ? 0xE0000C : 0xE8000C) /* offset */ -#define SH7750_SCTDR(n) SH7750_P4_REG32(SH7750_SCTDR_REGOFS(n)) -#define SH7750_SCTDR1 SH7750_SCTDR(1) -#define SH7750_SCTDR2 SH7750_SCTDR(2) -#define SH7750_SCTDR_A7(n) SH7750_A7_REG32(SH7750_SCTDR_REGOFS(n)) -#define SH7750_SCTDR1_A7 SH7750_SCTDR_A7(1) -#define SH7750_SCTDR2_A7 SH7750_SCTDR_A7(2) - -/* SCI Serial Mode Register - SCSMR1(byte), SCSMR2(half) */ -#define SH7750_SCSMR_REGOFS(n) ((n) == 1 ? 0xE00000 : 0xE80000) /* offset */ -#define SH7750_SCSMR(n) SH7750_P4_REG32(SH7750_SCSMR_REGOFS(n)) -#define SH7750_SCSMR1 SH7750_SCSMR(1) -#define SH7750_SCSMR2 SH7750_SCSMR(2) -#define SH7750_SCSMR_A7(n) SH7750_A7_REG32(SH7750_SCSMR_REGOFS(n)) -#define SH7750_SCSMR1_A7 SH7750_SCSMR_A7(1) -#define SH7750_SCSMR2_A7 SH7750_SCSMR_A7(2) - -#define SH7750_SCSMR1_CA 0x80 /* Communication Mode (C/A\): */ -#define SH7750_SCSMR1_CA_ASYNC 0x00 /* Asynchronous Mode */ -#define SH7750_SCSMR1_CA_SYNC 0x80 /* Synchronous Mode */ -#define SH7750_SCSMR_CHR 0x40 /* Character Length: */ -#define SH7750_SCSMR_CHR_8 0x00 /* 8-bit data */ -#define SH7750_SCSMR_CHR_7 0x40 /* 7-bit data */ -#define SH7750_SCSMR_PE 0x20 /* Parity Enable */ -#define SH7750_SCSMR_PM 0x10 /* Parity Mode: */ -#define SH7750_SCSMR_PM_EVEN 0x00 /* Even Parity */ -#define SH7750_SCSMR_PM_ODD 0x10 /* Odd Parity */ -#define SH7750_SCSMR_STOP 0x08 /* Stop Bit Length: */ -#define SH7750_SCSMR_STOP_1 0x00 /* 1 stop bit */ -#define SH7750_SCSMR_STOP_2 0x08 /* 2 stop bit */ -#define SH7750_SCSMR1_MP 0x04 /* Multiprocessor Mode */ -#define SH7750_SCSMR_CKS 0x03 /* Clock Select */ -#define SH7750_SCSMR_CKS_S 0 -#define SH7750_SCSMR_CKS_DIV1 0x00 /* Periph clock */ -#define SH7750_SCSMR_CKS_DIV4 0x01 /* Periph clock / 4 */ -#define SH7750_SCSMR_CKS_DIV16 0x02 /* Periph clock / 16 */ -#define SH7750_SCSMR_CKS_DIV64 0x03 /* Periph clock / 64 */ - -/* SCI Serial Control Register - SCSCR1(byte), SCSCR2(half) */ -#define SH7750_SCSCR_REGOFS(n) ((n) == 1 ? 0xE00008 : 0xE80008) /* offset */ -#define SH7750_SCSCR(n) SH7750_P4_REG32(SH7750_SCSCR_REGOFS(n)) -#define SH7750_SCSCR1 SH7750_SCSCR(1) -#define SH7750_SCSCR2 SH7750_SCSCR(2) -#define SH7750_SCSCR_A7(n) SH7750_A7_REG32(SH7750_SCSCR_REGOFS(n)) -#define SH7750_SCSCR1_A7 SH7750_SCSCR_A7(1) -#define SH7750_SCSCR2_A7 SH7750_SCSCR_A7(2) - -#define SH7750_SCSCR_TIE 0x80 /* Transmit Interrupt Enable */ -#define SH7750_SCSCR_RIE 0x40 /* Receive Interrupt Enable */ -#define SH7750_SCSCR_TE 0x20 /* Transmit Enable */ -#define SH7750_SCSCR_RE 0x10 /* Receive Enable */ -#define SH7750_SCSCR1_MPIE 0x08 /* Multiprocessor Interrupt Enable */ -#define SH7750_SCSCR2_REIE 0x08 /* Receive Error Interrupt Enable */ -#define SH7750_SCSCR1_TEIE 0x04 /* Transmit End Interrupt Enable */ -#define SH7750_SCSCR1_CKE 0x03 /* Clock Enable: */ -#define SH7750_SCSCR_CKE_INTCLK 0x00 /* Use Internal Clock */ -#define SH7750_SCSCR_CKE_EXTCLK 0x02 /* Use External Clock from SCK */ -#define SH7750_SCSCR1_CKE_ASYNC_SCK_CLKOUT 0x01 /* Use SCK as a clock output - in asynchronous mode */ - -/* SCI Serial Status Register - SCSSR1(byte), SCSFR2(half) */ -#define SH7750_SCSSR_REGOFS(n) ((n) == 1 ? 0xE00010 : 0xE80010) /* offset */ -#define SH7750_SCSSR(n) SH7750_P4_REG32(SH7750_SCSSR_REGOFS(n)) -#define SH7750_SCSSR1 SH7750_SCSSR(1) -#define SH7750_SCSFR2 SH7750_SCSSR(2) -#define SH7750_SCSSR_A7(n) SH7750_A7_REG32(SH7750_SCSSR_REGOFS(n)) -#define SH7750_SCSSR1_A7 SH7750_SCSSR_A7(1) -#define SH7750_SCSFR2_A7 SH7750_SCSSR_A7(2) - -#define SH7750_SCSSR1_TDRE 0x80 /* Transmit Data Register Empty */ -#define SH7750_SCSSR1_RDRF 0x40 /* Receive Data Register Full */ -#define SH7750_SCSSR1_ORER 0x20 /* Overrun Error */ -#define SH7750_SCSSR1_FER 0x10 /* Framing Error */ -#define SH7750_SCSSR1_PER 0x08 /* Parity Error */ -#define SH7750_SCSSR1_TEND 0x04 /* Transmit End */ -#define SH7750_SCSSR1_MPB 0x02 /* Multiprocessor Bit */ -#define SH7750_SCSSR1_MPBT 0x01 /* Multiprocessor Bit Transfer */ - -#define SH7750_SCFSR2_PERN 0xF000 /* Number of Parity Errors */ -#define SH7750_SCFSR2_PERN_S 12 -#define SH7750_SCFSR2_FERN 0x0F00 /* Number of Framing Errors */ -#define SH7750_SCFSR2_FERN_S 8 -#define SH7750_SCFSR2_ER 0x0080 /* Receive Error */ -#define SH7750_SCFSR2_TEND 0x0040 /* Transmit End */ -#define SH7750_SCFSR2_TDFE 0x0020 /* Transmit FIFO Data Empty */ -#define SH7750_SCFSR2_BRK 0x0010 /* Break Detect */ -#define SH7750_SCFSR2_FER 0x0008 /* Framing Error */ -#define SH7750_SCFSR2_PER 0x0004 /* Parity Error */ -#define SH7750_SCFSR2_RDF 0x0002 /* Receive FIFO Data Full */ -#define SH7750_SCFSR2_DR 0x0001 /* Receive Data Ready */ - -/* SCI Serial Port Register - SCSPTR1(byte) */ -#define SH7750_SCSPTR1_REGOFS 0xE0001C /* offset */ -#define SH7750_SCSPTR1 SH7750_P4_REG32(SH7750_SCSPTR1_REGOFS) -#define SH7750_SCSPTR1_A7 SH7750_A7_REG32(SH7750_SCSPTR1_REGOFS) - -#define SH7750_SCSPTR1_EIO 0x80 /* Error Interrupt Only */ -#define SH7750_SCSPTR1_SPB1IO 0x08 /* 1: Output SPB1DT bit to SCK pin */ -#define SH7750_SCSPTR1_SPB1DT 0x04 /* Serial Port Clock Port Data */ -#define SH7750_SCSPTR1_SPB0IO 0x02 /* 1: Output SPB0DT bit to TxD pin */ -#define SH7750_SCSPTR1_SPB0DT 0x01 /* Serial Port Break Data */ - -/* SCIF Serial Port Register - SCSPTR2(half) */ -#define SH7750_SCSPTR2_REGOFS 0xE80020 /* offset */ -#define SH7750_SCSPTR2 SH7750_P4_REG32(SH7750_SCSPTR2_REGOFS) -#define SH7750_SCSPTR2_A7 SH7750_A7_REG32(SH7750_SCSPTR2_REGOFS) - -#define SH7750_SCSPTR2_RTSIO 0x80 /* 1: Output RTSDT bit to RTS2\ pin */ -#define SH7750_SCSPTR2_RTSDT 0x40 /* RTS Port Data */ -#define SH7750_SCSPTR2_CTSIO 0x20 /* 1: Output CTSDT bit to CTS2\ pin */ -#define SH7750_SCSPTR2_CTSDT 0x10 /* CTS Port Data */ -#define SH7750_SCSPTR2_SPB2IO 0x02 /* 1: Output SPBDT bit to TxD2 pin */ -#define SH7750_SCSPTR2_SPB2DT 0x01 /* Serial Port Break Data */ - -/* SCI Bit Rate Register - SCBRR1(byte), SCBRR2(byte) */ -#define SH7750_SCBRR_REGOFS(n) ((n) == 1 ? 0xE00004 : 0xE80004) /* offset */ -#define SH7750_SCBRR(n) SH7750_P4_REG32(SH7750_SCBRR_REGOFS(n)) -#define SH7750_SCBRR1 SH7750_SCBRR_P4(1) -#define SH7750_SCBRR2 SH7750_SCBRR_P4(2) -#define SH7750_SCBRR_A7(n) SH7750_A7_REG32(SH7750_SCBRR_REGOFS(n)) -#define SH7750_SCBRR1_A7 SH7750_SCBRR_A7(1) -#define SH7750_SCBRR2_A7 SH7750_SCBRR_A7(2) - -/* SCIF FIFO Control Register - SCFCR2(half) */ -#define SH7750_SCFCR2_REGOFS 0xE80018 /* offset */ -#define SH7750_SCFCR2 SH7750_P4_REG32(SH7750_SCFCR2_REGOFS) -#define SH7750_SCFCR2_A7 SH7750_A7_REG32(SH7750_SCFCR2_REGOFS) - -#define SH7750_SCFCR2_RSTRG 0x700 /* RTS2\ Output Active Trigger; RTS2\ - signal goes to high level when the - number of received data stored in - FIFO exceeds the trigger number */ -#define SH7750_SCFCR2_RSTRG_15 0x000 /* 15 bytes */ -#define SH7750_SCFCR2_RSTRG_1 0x000 /* 1 byte */ -#define SH7750_SCFCR2_RSTRG_4 0x000 /* 4 bytes */ -#define SH7750_SCFCR2_RSTRG_6 0x000 /* 6 bytes */ -#define SH7750_SCFCR2_RSTRG_8 0x000 /* 8 bytes */ -#define SH7750_SCFCR2_RSTRG_10 0x000 /* 10 bytes */ -#define SH7750_SCFCR2_RSTRG_14 0x000 /* 14 bytes */ - -#define SH7750_SCFCR2_RTRG 0x0C0 /* Receive FIFO Data Number Trigger, - Receive Data Full (RDF) Flag sets - when number of receive data bytes is - equal or greater than the trigger - number */ -#define SH7750_SCFCR2_RTRG_1 0x000 /* 1 byte */ -#define SH7750_SCFCR2_RTRG_4 0x040 /* 4 bytes */ -#define SH7750_SCFCR2_RTRG_8 0x080 /* 8 bytes */ -#define SH7750_SCFCR2_RTRG_14 0x0C0 /* 14 bytes */ - -#define SH7750_SCFCR2_TTRG 0x030 /* Transmit FIFO Data Number Trigger, - Transmit FIFO Data Register Empty (TDFE) - flag sets when the number of remaining - transmit data bytes is equal or less - than the trigger number */ -#define SH7750_SCFCR2_TTRG_8 0x000 /* 8 bytes */ -#define SH7750_SCFCR2_TTRG_4 0x010 /* 4 bytes */ -#define SH7750_SCFCR2_TTRG_2 0x020 /* 2 bytes */ -#define SH7750_SCFCR2_TTRG_1 0x030 /* 1 byte */ - -#define SH7750_SCFCR2_MCE 0x008 /* Modem Control Enable */ -#define SH7750_SCFCR2_TFRST 0x004 /* Transmit FIFO Data Register Reset, - invalidates the transmit data in the - transmit FIFO */ -#define SH7750_SCFCR2_RFRST 0x002 /* Receive FIFO Data Register Reset, - invalidates the receive data in the - receive FIFO data register and resets - it to the empty state */ -#define SH7750_SCFCR2_LOOP 0x001 /* Loopback Test */ - -/* SCIF FIFO Data Count Register - SCFDR2(half, read-only) */ -#define SH7750_SCFDR2_REGOFS 0xE8001C /* offset */ -#define SH7750_SCFDR2 SH7750_P4_REG32(SH7750_SCFDR2_REGOFS) -#define SH7750_SCFDR2_A7 SH7750_A7_REG32(SH7750_SCFDR2_REGOFS) - -#define SH7750_SCFDR2_T 0x1F00 /* Number of untransmitted data bytes - in transmit FIFO */ -#define SH7750_SCFDR2_T_S 8 -#define SH7750_SCFDR2_R 0x001F /* Number of received data bytes in - receive FIFO */ -#define SH7750_SCFDR2_R_S 0 - -/* SCIF Line Status Register - SCLSR2(half, read-only) */ -#define SH7750_SCLSR2_REGOFS 0xE80024 /* offset */ -#define SH7750_SCLSR2 SH7750_P4_REG32(SH7750_SCLSR2_REGOFS) -#define SH7750_SCLSR2_A7 SH7750_A7_REG32(SH7750_SCLSR2_REGOFS) - -#define SH7750_SCLSR2_ORER 0x0001 /* Overrun Error */ - -/* - * SCI-based Smart Card Interface - */ -/* Smart Card Mode Register - SCSCMR1(byte) */ -#define SH7750_SCSCMR1_REGOFS 0xE00018 /* offset */ -#define SH7750_SCSCMR1 SH7750_P4_REG32(SH7750_SCSCMR1_REGOFS) -#define SH7750_SCSCMR1_A7 SH7750_A7_REG32(SH7750_SCSCMR1_REGOFS) - -#define SH7750_SCSCMR1_SDIR 0x08 /* Smart Card Data Transfer Direction: */ -#define SH7750_SCSCMR1_SDIR_LSBF 0x00 /* LSB-first */ -#define SH7750_SCSCMR1_SDIR_MSBF 0x08 /* MSB-first */ - -#define SH7750_SCSCMR1_SINV 0x04 /* Smart Card Data Inversion */ -#define SH7750_SCSCMR1_SMIF 0x01 /* Smart Card Interface Mode Select */ - -/* Smart-card specific bits in other registers */ -/* SCSMR1: */ -#define SH7750_SCSMR1_GSM 0x80 /* GSM mode select */ - -/* SCSSR1: */ -#define SH7750_SCSSR1_ERS 0x10 /* Error Signal Status */ - -/* * I/O Ports */ /* Port Control Register A - PCTRA */ @@ -1466,48 +1241,6 @@ #define SH7750_ICR_IRLM_RAW 0x0080 /* IRL\ pins used as a four independent interrupt requests */ -/* Interrupt Priority Register A - IPRA (half) */ -#define SH7750_IPRA_REGOFS 0xD00004 /* offset */ -#define SH7750_IPRA SH7750_P4_REG32(SH7750_IPRA_REGOFS) -#define SH7750_IPRA_A7 SH7750_A7_REG32(SH7750_IPRA_REGOFS) - -#define SH7750_IPRA_TMU0 0xF000 /* TMU0 interrupt priority */ -#define SH7750_IPRA_TMU0_S 12 -#define SH7750_IPRA_TMU1 0x0F00 /* TMU1 interrupt priority */ -#define SH7750_IPRA_TMU1_S 8 -#define SH7750_IPRA_TMU2 0x00F0 /* TMU2 interrupt priority */ -#define SH7750_IPRA_TMU2_S 4 -#define SH7750_IPRA_RTC 0x000F /* RTC interrupt priority */ -#define SH7750_IPRA_RTC_S 0 - -/* Interrupt Priority Register B - IPRB (half) */ -#define SH7750_IPRB_REGOFS 0xD00008 /* offset */ -#define SH7750_IPRB SH7750_P4_REG32(SH7750_IPRB_REGOFS) -#define SH7750_IPRB_A7 SH7750_A7_REG32(SH7750_IPRB_REGOFS) - -#define SH7750_IPRB_WDT 0xF000 /* WDT interrupt priority */ -#define SH7750_IPRB_WDT_S 12 -#define SH7750_IPRB_REF 0x0F00 /* Memory Refresh unit interrupt - priority */ -#define SH7750_IPRB_REF_S 8 -#define SH7750_IPRB_SCI1 0x00F0 /* SCI1 interrupt priority */ -#define SH7750_IPRB_SCI1_S 4 - -/* Interrupt Priority Register ó - IPRó (half) */ -#define SH7750_IPRC_REGOFS 0xD00004 /* offset */ -#define SH7750_IPRC SH7750_P4_REG32(SH7750_IPRC_REGOFS) -#define SH7750_IPRC_A7 SH7750_A7_REG32(SH7750_IPRC_REGOFS) - -#define SH7750_IPRC_GPIO 0xF000 /* GPIO interrupt priority */ -#define SH7750_IPRC_GPIO_S 12 -#define SH7750_IPRC_DMAC 0x0F00 /* DMAC interrupt priority */ -#define SH7750_IPRC_DMAC_S 8 -#define SH7750_IPRC_SCIF 0x00F0 /* SCIF interrupt priority */ -#define SH7750_IPRC_SCIF_S 4 -#define SH7750_IPRC_HUDI 0x000F /* H-UDI interrupt priority */ -#define SH7750_IPRC_HUDI_S 0 - - /* * User Break Controller registers */