X-Git-Url: https://vcs.maemo.org/git/?a=blobdiff_plain;ds=sidebyside;f=hw%2Fcs4231.c;h=982980038887add04b1c7a59ad71bccfb066287b;hb=cd346349b45ef056f138a184f660b8c34c3213cc;hp=6df881d41bd665f00e01ef28c628dc6b9a184a0a;hpb=d537cf6c8624b27ce2b63431d2f8937f6356f652;p=qemu

diff --git a/hw/cs4231.c b/hw/cs4231.c
index 6df881d..9829800 100644
--- a/hw/cs4231.c
+++ b/hw/cs4231.c
@@ -30,6 +30,7 @@
  * In addition to Crystal CS4231 there is a DMA controller on Sparc.
  */
 #define CS_MAXADDR 0x3f
+#define CS_SIZE (CS_MAXADDR + 1)
 #define CS_REGS 16
 #define CS_DREGS 32
 #define CS_MAXDREG (CS_DREGS - 1)
@@ -78,11 +79,11 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
             break;
         }
         DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
-	break;
+        break;
     default:
         ret = s->regs[saddr];
         DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
-	break;
+        break;
     }
     return ret;
 }
@@ -121,7 +122,7 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
         break;
     default:
         s->regs[saddr] = val;
-	break;
+        break;
     }
 }
 
@@ -173,7 +174,7 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl)
         return;
 
     cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
-    cpu_register_physical_memory(base, CS_MAXADDR, cs_io_memory);
+    cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);
     register_savevm("cs4231", base, 1, cs_save, cs_load, s);
     qemu_register_reset(cs_reset, s);
     cs_reset(s);