Several corrections in the spitzkbd keymap (patch by Juergen Lock).

[qemu] / target-ppc / cpu.h

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 53f4af3..43b8c90 100644 (file)
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -82,20 +82,12 @@ typedef uint32_t ppc_gpr_t;
 #define ELF_MACHINE     EM_PPC
 #endif
 
-/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
- *                              have different cache line sizes
- */
-#define ICACHE_LINE_SIZE 32
-#define DCACHE_LINE_SIZE 32
-
 /*****************************************************************************/
 /* MMU model                                                                 */
 enum {
     POWERPC_MMU_UNKNOWN    = 0,
     /* Standard 32 bits PowerPC MMU                            */
     POWERPC_MMU_32B,
-    /* Standard 64 bits PowerPC MMU                            */
-    POWERPC_MMU_64B,
     /* PowerPC 601 MMU                                         */
     POWERPC_MMU_601,
     /* PowerPC 6xx MMU with software TLB                       */
@@ -112,8 +104,12 @@ enum {
     POWERPC_MMU_BOOKE,
     /* BookE FSL MMU model                                     */
     POWERPC_MMU_BOOKE_FSL,
+#if defined(TARGET_PPC64)
+    /* Standard 64 bits PowerPC MMU                            */
+    POWERPC_MMU_64B,
     /* 64 bits "bridge" PowerPC MMU                            */
     POWERPC_MMU_64BRIDGE,
+#endif /* defined(TARGET_PPC64) */
 };
 
 /*****************************************************************************/
@@ -142,10 +138,12 @@ enum {
     POWERPC_EXCP_7x5,
     /* PowerPC 74xx exception model     */
     POWERPC_EXCP_74xx,
-    /* PowerPC 970 exception model      */
-    POWERPC_EXCP_970,
     /* BookE exception model            */
     POWERPC_EXCP_BOOKE,
+#if defined(TARGET_PPC64)
+    /* PowerPC 970 exception model      */
+    POWERPC_EXCP_970,
+#endif /* defined(TARGET_PPC64) */
 };
 
 /*****************************************************************************/
@@ -517,6 +515,9 @@ struct CPUPPCState {
     /* 403 dedicated access protection registers */
     target_ulong pb[4];
 
+    int dcache_line_size;
+    int icache_line_size;
+
     /* Those resources are used during exception processing */
     /* CPU model definition */
     target_ulong msr_mask;
@@ -542,6 +543,7 @@ struct CPUPPCState {
     target_ulong excp_prefix;
     target_ulong ivor_mask;
     target_ulong ivpr_mask;
+    target_ulong hreset_vector;
 #endif
 
     /* Those resources are used only during code translation */
@@ -611,9 +613,9 @@ void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
 target_ulong ppc_load_xer (CPUPPCState *env);
 void ppc_store_xer (CPUPPCState *env, target_ulong value);
 target_ulong do_load_msr (CPUPPCState *env);
-void do_store_msr (CPUPPCState *env, target_ulong value);
+int do_store_msr (CPUPPCState *env, target_ulong value);
 #if defined(TARGET_PPC64)
-void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
+int ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
 #endif
 
 void do_compute_hflags (CPUPPCState *env);
@@ -656,6 +658,11 @@ void store_40x_sler (CPUPPCState *env, uint32_t val);
 void store_booke_tcr (CPUPPCState *env, target_ulong val);
 void store_booke_tsr (CPUPPCState *env, target_ulong val);
 void ppc_tlb_invalidate_all (CPUPPCState *env);
+void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
+#if defined(TARGET_PPC64)
+void ppc_slb_invalidate_all (CPUPPCState *env);
+void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
+#endif
 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
 #endif
 #endif
@@ -1043,6 +1050,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
 #define SPR_601_HID5     (0x3F5)
 #define SPR_40x_DAC1     (0x3F6)
 #define SPR_MSSCR0       (0x3F6)
+#define SPR_970_HID5     (0x3F6)
 #define SPR_MSSSR0       (0x3F7)
 #define SPR_DABRX        (0x3F7)
 #define SPR_40x_DAC2     (0x3F7)
@@ -1117,25 +1125,18 @@ enum {
 };
 
 enum {
-    /* PowerPC 401/403 input pins */
-    PPC401_INPUT_RESET      = 0,
-    PPC401_INPUT_CINT       = 1,
-    PPC401_INPUT_INT        = 2,
-    PPC401_INPUT_BERR       = 3,
-    PPC401_INPUT_HALT       = 4,
-};
-
-enum {
-    /* PowerPC 405 input pins */
-    PPC405_INPUT_RESET_CORE = 0,
-    PPC405_INPUT_RESET_CHIP = 1,
-    PPC405_INPUT_RESET_SYS  = 2,
-    PPC405_INPUT_CINT       = 3,
-    PPC405_INPUT_INT        = 4,
-    PPC405_INPUT_HALT       = 5,
-    PPC405_INPUT_DEBUG      = 6,
+    /* PowerPC 40x input pins */
+    PPC40x_INPUT_RESET_CORE = 0,
+    PPC40x_INPUT_RESET_CHIP = 1,
+    PPC40x_INPUT_RESET_SYS  = 2,
+    PPC40x_INPUT_CINT       = 3,
+    PPC40x_INPUT_INT        = 4,
+    PPC40x_INPUT_HALT       = 5,
+    PPC40x_INPUT_DEBUG      = 6,
+    PPC40x_INPUT_NB,
 };
 
+#if defined(TARGET_PPC64)
 enum {
     /* PowerPC 620 (and probably others) input pins */
     PPC620_INPUT_HRESET     = 0,
@@ -1158,6 +1159,7 @@ enum {
     PPC970_INPUT_INT        = 5,
     PPC970_INPUT_THINT      = 6,
 };
+#endif
 
 /* Hardware exceptions definitions */
 enum {