#define ELF_MACHINE EM_PPC
#endif
-/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
- * have different cache line sizes
- */
-#define ICACHE_LINE_SIZE 32
-#define DCACHE_LINE_SIZE 32
-
/*****************************************************************************/
/* MMU model */
enum {
POWERPC_MMU_UNKNOWN = 0,
/* Standard 32 bits PowerPC MMU */
POWERPC_MMU_32B,
- /* Standard 64 bits PowerPC MMU */
- POWERPC_MMU_64B,
/* PowerPC 601 MMU */
POWERPC_MMU_601,
/* PowerPC 6xx MMU with software TLB */
POWERPC_MMU_BOOKE,
/* BookE FSL MMU model */
POWERPC_MMU_BOOKE_FSL,
+#if defined(TARGET_PPC64)
+ /* Standard 64 bits PowerPC MMU */
+ POWERPC_MMU_64B,
/* 64 bits "bridge" PowerPC MMU */
POWERPC_MMU_64BRIDGE,
+#endif /* defined(TARGET_PPC64) */
};
/*****************************************************************************/
POWERPC_EXCP_7x5,
/* PowerPC 74xx exception model */
POWERPC_EXCP_74xx,
- /* PowerPC 970 exception model */
- POWERPC_EXCP_970,
/* BookE exception model */
POWERPC_EXCP_BOOKE,
+#if defined(TARGET_PPC64)
+ /* PowerPC 970 exception model */
+ POWERPC_EXCP_970,
+#endif /* defined(TARGET_PPC64) */
};
/*****************************************************************************/
/* 403 dedicated access protection registers */
target_ulong pb[4];
+ int dcache_line_size;
+ int icache_line_size;
+
/* Those resources are used during exception processing */
/* CPU model definition */
target_ulong msr_mask;
target_ulong excp_prefix;
target_ulong ivor_mask;
target_ulong ivpr_mask;
+ target_ulong hreset_vector;
#endif
/* Those resources are used only during code translation */
#define SPR_601_HID5 (0x3F5)
#define SPR_40x_DAC1 (0x3F6)
#define SPR_MSSCR0 (0x3F6)
+#define SPR_970_HID5 (0x3F6)
#define SPR_MSSSR0 (0x3F7)
#define SPR_DABRX (0x3F7)
#define SPR_40x_DAC2 (0x3F7)
PPC40x_INPUT_NB,
};
+#if defined(TARGET_PPC64)
enum {
/* PowerPC 620 (and probably others) input pins */
PPC620_INPUT_HRESET = 0,
PPC970_INPUT_INT = 5,
PPC970_INPUT_THINT = 6,
};
+#endif
/* Hardware exceptions definitions */
enum {