* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include <stdlib.h>
-#include <stdio.h>
-#include <stdarg.h>
-#include <string.h>
-#include <getopt.h>
-#include <inttypes.h>
-#include <unistd.h>
-#include <sys/mman.h>
-#include <fcntl.h>
-#include <signal.h>
-#include <time.h>
-#include <sys/time.h>
-#include <malloc.h>
-#include <termios.h>
-#include <sys/poll.h>
-#include <errno.h>
-#include <sys/wait.h>
-#include <netinet/in.h>
-
-#define NO_THUNK_TYPE_SIZE
-#include "thunk.h"
-
-#include "cpu.h"
-#include "exec-all.h"
-
#include "vl.h"
//#define DEBUG_VGA
uint8_t dac_write_index;
uint8_t dac_cache[3]; /* used when writing */
uint8_t palette[768];
+ uint32_t bank_offset;
#ifdef CONFIG_BOCHS_VBE
uint16_t vbe_index;
uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
uint32_t vbe_start_addr;
uint32_t vbe_line_offset;
+ uint32_t vbe_bank_mask;
#endif
/* display refresh support */
DisplayState *ds;
VGAState vga_state;
int vga_io_memory;
-static uint32_t vga_ioport_read(CPUState *env, uint32_t addr)
+static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
{
- VGAState *s = &vga_state;
+ VGAState *s = opaque;
int val, index;
/* check port range access depending on color/monochrome mode */
return val;
}
-static void vga_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
+static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
- VGAState *s = &vga_state;
+ VGAState *s = opaque;
int index, v;
/* check port range access depending on color/monochrome mode */
}
#ifdef CONFIG_BOCHS_VBE
-static uint32_t vbe_ioport_read(CPUState *env, uint32_t addr)
+static uint32_t vbe_ioport_read(void *opaque, uint32_t addr)
{
- VGAState *s = &vga_state;
+ VGAState *s = opaque;
uint32_t val;
addr &= 1;
return val;
}
-static void vbe_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
+static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
- VGAState *s = &vga_state;
+ VGAState *s = opaque;
addr &= 1;
if (addr == 0) {
#endif
switch(s->vbe_index) {
case VBE_DISPI_INDEX_ID:
- if (val != VBE_DISPI_ID0 &&
- val != VBE_DISPI_ID1 &&
- val != VBE_DISPI_ID2)
- return;
+ if (val == VBE_DISPI_ID0 ||
+ val == VBE_DISPI_ID1 ||
+ val == VBE_DISPI_ID2) {
+ s->vbe_regs[s->vbe_index] = val;
+ }
break;
case VBE_DISPI_INDEX_XRES:
- if ((val > VBE_DISPI_MAX_XRES) || ((val & 7) != 0))
- return;
+ if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
+ s->vbe_regs[s->vbe_index] = val;
+ }
break;
case VBE_DISPI_INDEX_YRES:
- if (val > VBE_DISPI_MAX_YRES)
- return;
+ if (val <= VBE_DISPI_MAX_YRES) {
+ s->vbe_regs[s->vbe_index] = val;
+ }
break;
case VBE_DISPI_INDEX_BPP:
if (val == 0)
val = 8;
- if (val != 4 && val != 8 && val != 15 &&
- val != 16 && val != 24 && val != 32)
- return;
+ if (val == 4 || val == 8 || val == 15 ||
+ val == 16 || val == 24 || val == 32) {
+ s->vbe_regs[s->vbe_index] = val;
+ }
break;
case VBE_DISPI_INDEX_BANK:
- val &= 0xff;
+ val &= s->vbe_bank_mask;
+ s->vbe_regs[s->vbe_index] = val;
+ s->bank_offset = (val << 16) - 0xa0000;
break;
case VBE_DISPI_INDEX_ENABLE:
if (val & VBE_DISPI_ENABLED) {
s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
}
- /* we initialize graphic mode force graphic mode
- (should be done in BIOS) */
- s->gr[6] |= 1;
+ /* we initialize the VGA graphic mode (should be done
+ in BIOS) */
+ s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
s->cr[0x17] |= 3; /* no CGA modes */
s->cr[0x13] = s->vbe_line_offset >> 3;
/* width */
}
s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
s->cr[0x09] &= ~0x9f; /* no double scan */
+ s->vbe_regs[s->vbe_index] = val;
+ } else {
+ /* XXX: the bios should do that */
+ s->bank_offset = -0xa0000;
+ }
+ break;
+ case VBE_DISPI_INDEX_VIRT_WIDTH:
+ {
+ int w, h, line_offset;
+
+ if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
+ return;
+ w = val;
+ if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
+ line_offset = w >> 1;
+ else
+ line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
+ h = s->vram_size / line_offset;
+ /* XXX: support weird bochs semantics ? */
+ if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
+ return;
+ s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
+ s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
+ s->vbe_line_offset = line_offset;
+ }
+ break;
+ case VBE_DISPI_INDEX_X_OFFSET:
+ case VBE_DISPI_INDEX_Y_OFFSET:
+ {
+ int x;
+ s->vbe_regs[s->vbe_index] = val;
+ s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
+ x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
+ if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
+ s->vbe_start_addr += x >> 1;
+ else
+ s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
+ s->vbe_start_addr >>= 2;
}
break;
default:
break;
}
- s->vbe_regs[s->vbe_index] = val;
}
}
#endif
addr -= 0xa0000;
break;
case 1:
- addr -= 0xa0000;
- if (addr >= 0x10000)
+ if (addr >= 0xb0000)
return 0xff;
+ addr += s->bank_offset;
break;
case 2:
addr -= 0xb0000;
}
/* called for accesses between 0xa0000 and 0xc0000 */
-void vga_mem_writeb(uint32_t addr, uint32_t val, uint32_t vaddr)
+static void vga_mem_writeb(uint32_t addr, uint32_t val, uint32_t vaddr)
{
VGAState *s = &vga_state;
int memory_map_mode, plane, write_mode, b, func_select;
addr -= 0xa0000;
break;
case 1:
- addr -= 0xa0000;
- if (addr >= 0x10000)
+ if (addr >= 0xb0000)
return;
+ addr += s->bank_offset;
break;
case 2:
addr -= 0xb0000;
}
}
-void vga_mem_writew(uint32_t addr, uint32_t val, uint32_t vaddr)
+static void vga_mem_writew(uint32_t addr, uint32_t val, uint32_t vaddr)
{
vga_mem_writeb(addr, val & 0xff, vaddr);
vga_mem_writeb(addr + 1, (val >> 8) & 0xff, vaddr);
}
-void vga_mem_writel(uint32_t addr, uint32_t val, uint32_t vaddr)
+static void vga_mem_writel(uint32_t addr, uint32_t val, uint32_t vaddr)
{
vga_mem_writeb(addr, val & 0xff, vaddr);
vga_mem_writeb(addr + 1, (val >> 8) & 0xff, vaddr);
}
}
-/* draw text terminal (very limited, just for simple boot debug
- messages) */
-static int last_cursor_pos;
-
-void vga_draw_dumb(VGAState *s)
-{
- int c, i, cursor_pos, eol;
-
- cursor_pos = s->cr[0x0f] | (s->cr[0x0e] << 8);
- eol = 0;
- for(i = last_cursor_pos; i < cursor_pos; i++) {
- /* XXX: should use vga RAM */
- c = phys_ram_base[0xb8000 + (i) * 2];
- if (c >= ' ') {
- putchar(c);
- eol = 0;
- } else {
- if (!eol)
- putchar('\n');
- eol = 1;
- }
- }
- fflush(stdout);
- last_cursor_pos = cursor_pos;
-}
-
void vga_update_display(void)
{
VGAState *s = &vga_state;
int full_update, graphic_mode;
if (s->ds->depth == 0) {
- vga_draw_dumb(s);
+ /* nothing to do */
} else {
+ switch(s->ds->depth) {
+ case 8:
+ s->rgb_to_pixel = rgb_to_pixel8_dup;
+ break;
+ case 15:
+ s->rgb_to_pixel = rgb_to_pixel15_dup;
+ break;
+ default:
+ case 16:
+ s->rgb_to_pixel = rgb_to_pixel16_dup;
+ break;
+ case 32:
+ s->rgb_to_pixel = rgb_to_pixel32_dup;
+ break;
+ }
+
full_update = 0;
graphic_mode = s->gr[6] & 1;
if (graphic_mode != s->graphic_mode) {
}
}
-void vga_reset(VGAState *s)
+static void vga_reset(VGAState *s)
{
memset(s, 0, sizeof(VGAState));
#ifdef CONFIG_S3VGA
s->graphic_mode = -1; /* force full update */
}
-CPUReadMemoryFunc *vga_mem_read[3] = {
+static CPUReadMemoryFunc *vga_mem_read[3] = {
vga_mem_readb,
vga_mem_readw,
vga_mem_readl,
};
-CPUWriteMemoryFunc *vga_mem_write[3] = {
+static CPUWriteMemoryFunc *vga_mem_write[3] = {
vga_mem_writeb,
vga_mem_writew,
vga_mem_writel,
};
+static void vga_save(QEMUFile *f, void *opaque)
+{
+ VGAState *s = opaque;
+ int i;
+
+ qemu_put_be32s(f, &s->latch);
+ qemu_put_8s(f, &s->sr_index);
+ qemu_put_buffer(f, s->sr, 8);
+ qemu_put_8s(f, &s->gr_index);
+ qemu_put_buffer(f, s->gr, 16);
+ qemu_put_8s(f, &s->ar_index);
+ qemu_put_buffer(f, s->ar, 21);
+ qemu_put_be32s(f, &s->ar_flip_flop);
+ qemu_put_8s(f, &s->cr_index);
+ qemu_put_buffer(f, s->cr, 256);
+ qemu_put_8s(f, &s->msr);
+ qemu_put_8s(f, &s->fcr);
+ qemu_put_8s(f, &s->st00);
+ qemu_put_8s(f, &s->st01);
+
+ qemu_put_8s(f, &s->dac_state);
+ qemu_put_8s(f, &s->dac_sub_index);
+ qemu_put_8s(f, &s->dac_read_index);
+ qemu_put_8s(f, &s->dac_write_index);
+ qemu_put_buffer(f, s->dac_cache, 3);
+ qemu_put_buffer(f, s->palette, 768);
+
+ qemu_put_be32s(f, &s->bank_offset);
+#ifdef CONFIG_BOCHS_VBE
+ qemu_put_byte(f, 1);
+ qemu_put_be16s(f, &s->vbe_index);
+ for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
+ qemu_put_be16s(f, &s->vbe_regs[i]);
+ qemu_put_be32s(f, &s->vbe_start_addr);
+ qemu_put_be32s(f, &s->vbe_line_offset);
+ qemu_put_be32s(f, &s->vbe_bank_mask);
+#else
+ qemu_put_byte(f, 0);
+#endif
+}
+
+static int vga_load(QEMUFile *f, void *opaque, int version_id)
+{
+ VGAState *s = opaque;
+ int is_vbe, i;
+
+ if (version_id != 1)
+ return -EINVAL;
+
+ qemu_get_be32s(f, &s->latch);
+ qemu_get_8s(f, &s->sr_index);
+ qemu_get_buffer(f, s->sr, 8);
+ qemu_get_8s(f, &s->gr_index);
+ qemu_get_buffer(f, s->gr, 16);
+ qemu_get_8s(f, &s->ar_index);
+ qemu_get_buffer(f, s->ar, 21);
+ qemu_get_be32s(f, &s->ar_flip_flop);
+ qemu_get_8s(f, &s->cr_index);
+ qemu_get_buffer(f, s->cr, 256);
+ qemu_get_8s(f, &s->msr);
+ qemu_get_8s(f, &s->fcr);
+ qemu_get_8s(f, &s->st00);
+ qemu_get_8s(f, &s->st01);
+
+ qemu_get_8s(f, &s->dac_state);
+ qemu_get_8s(f, &s->dac_sub_index);
+ qemu_get_8s(f, &s->dac_read_index);
+ qemu_get_8s(f, &s->dac_write_index);
+ qemu_get_buffer(f, s->dac_cache, 3);
+ qemu_get_buffer(f, s->palette, 768);
+
+ qemu_get_be32s(f, &s->bank_offset);
+ is_vbe = qemu_get_byte(f);
+#ifdef CONFIG_BOCHS_VBE
+ if (!is_vbe)
+ return -EINVAL;
+ qemu_get_be16s(f, &s->vbe_index);
+ for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
+ qemu_get_be16s(f, &s->vbe_regs[i]);
+ qemu_get_be32s(f, &s->vbe_start_addr);
+ qemu_get_be32s(f, &s->vbe_line_offset);
+ qemu_get_be32s(f, &s->vbe_bank_mask);
+#else
+ if (is_vbe)
+ return -EINVAL;
+#endif
+
+ /* force refresh */
+ s->graphic_mode = -1;
+ return 0;
+}
+
int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
vga_reset(s);
- switch(ds->depth) {
- case 8:
- s->rgb_to_pixel = rgb_to_pixel8_dup;
- break;
- case 15:
- s->rgb_to_pixel = rgb_to_pixel15_dup;
- break;
- default:
- case 16:
- s->rgb_to_pixel = rgb_to_pixel16_dup;
- break;
- case 32:
- s->rgb_to_pixel = rgb_to_pixel32_dup;
- break;
- }
-
s->vram_ptr = vga_ram_base;
s->vram_offset = vga_ram_offset;
s->vram_size = vga_ram_size;
s->ds = ds;
- register_ioport_write(0x3c0, 16, vga_ioport_write, 1);
+ register_savevm("vga", 0, 1, vga_save, vga_load, s);
+
+ register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
- register_ioport_write(0x3b4, 2, vga_ioport_write, 1);
- register_ioport_write(0x3d4, 2, vga_ioport_write, 1);
- register_ioport_write(0x3ba, 1, vga_ioport_write, 1);
- register_ioport_write(0x3da, 1, vga_ioport_write, 1);
+ register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
+ register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
+ register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
+ register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
- register_ioport_read(0x3c0, 16, vga_ioport_read, 1);
+ register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
- register_ioport_read(0x3b4, 2, vga_ioport_read, 1);
- register_ioport_read(0x3d4, 2, vga_ioport_read, 1);
- register_ioport_read(0x3ba, 1, vga_ioport_read, 1);
- register_ioport_read(0x3da, 1, vga_ioport_read, 1);
+ register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
+ register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
+ register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
+ register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
+ s->bank_offset = -0xa0000;
#ifdef CONFIG_BOCHS_VBE
s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
- register_ioport_read(0x1ce, 1, vbe_ioport_read, 2);
- register_ioport_read(0x1cf, 1, vbe_ioport_read, 2);
+ s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
+ register_ioport_read(0x1ce, 1, 2, vbe_ioport_read, s);
+ register_ioport_read(0x1cf, 1, 2, vbe_ioport_read, s);
- register_ioport_write(0x1ce, 1, vbe_ioport_write, 2);
- register_ioport_write(0x1cf, 1, vbe_ioport_write, 2);
+ register_ioport_write(0x1ce, 1, 2, vbe_ioport_write, s);
+ register_ioport_write(0x1cf, 1, 2, vbe_ioport_write, s);
#endif
vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write);
#endif
return 0;
}
+
+/********************************************************/
+/* vga screen dump */
+
+static int vga_save_w, vga_save_h;
+
+static void vga_save_dpy_update(DisplayState *s,
+ int x, int y, int w, int h)
+{
+}
+
+static void vga_save_dpy_resize(DisplayState *s, int w, int h)
+{
+ s->linesize = w * 4;
+ s->data = qemu_malloc(h * s->linesize);
+ vga_save_w = w;
+ vga_save_h = h;
+}
+
+static void vga_save_dpy_refresh(DisplayState *s)
+{
+}
+
+static int ppm_save(const char *filename, uint8_t *data,
+ int w, int h, int linesize)
+{
+ FILE *f;
+ uint8_t *d, *d1;
+ unsigned int v;
+ int y, x;
+
+ f = fopen(filename, "wb");
+ if (!f)
+ return -1;
+ fprintf(f, "P6\n%d %d\n%d\n",
+ w, h, 255);
+ d1 = data;
+ for(y = 0; y < h; y++) {
+ d = d1;
+ for(x = 0; x < w; x++) {
+ v = *(uint32_t *)d;
+ fputc((v >> 16) & 0xff, f);
+ fputc((v >> 8) & 0xff, f);
+ fputc((v) & 0xff, f);
+ d += 4;
+ }
+ d1 += linesize;
+ }
+ fclose(f);
+ return 0;
+}
+
+/* save the vga display in a PPM image even if no display is
+ available */
+void vga_screen_dump(const char *filename)
+{
+ VGAState *s = &vga_state;
+ DisplayState *saved_ds, ds1, *ds = &ds1;
+
+ /* XXX: this is a little hackish */
+ s->last_width = -1;
+ s->last_height = -1;
+ saved_ds = s->ds;
+
+ memset(ds, 0, sizeof(DisplayState));
+ ds->dpy_update = vga_save_dpy_update;
+ ds->dpy_resize = vga_save_dpy_resize;
+ ds->dpy_refresh = vga_save_dpy_refresh;
+ ds->depth = 32;
+
+ s->ds = ds;
+ s->graphic_mode = -1;
+ vga_update_display();
+
+ if (ds->data) {
+ ppm_save(filename, ds->data, vga_save_w, vga_save_h,
+ s->ds->linesize);
+ qemu_free(ds->data);
+ }
+ s->ds = saved_ds;
+}
projects / qemu / blobdiff