-/*
- * ARM Versatile Platform Baseboard System emulation.
+/*
+ * ARM Versatile Platform/Application Baseboard System emulation.
*
- * Copyright (c) 2005-2006 CodeSourcery.
+ * Copyright (c) 2005-2007 CodeSourcery.
* Written by Paul Brook
*
* This code is licenced under the GPL.
#include "vl.h"
#include "arm_pic.h"
-#define KERNEL_ARGS_ADDR 0x100
-#define KERNEL_LOAD_ADDR 0x00010000
-#define INITRD_LOAD_ADDR 0x00800000
-
/* Primary interrupt controller. */
typedef struct vpb_sic_state
{
- arm_pic_handler handler;
uint32_t base;
uint32_t level;
uint32_t mask;
uint32_t pic_enable;
- void *parent;
+ qemu_irq *parent;
int irq;
} vpb_sic_state;
uint32_t flags;
flags = s->level & s->mask;
- pic_set_irq_new(s->parent, s->irq, flags != 0);
+ qemu_set_irq(s->parent[s->irq], flags != 0);
}
static void vpb_sic_update_pic(vpb_sic_state *s)
mask = 1u << i;
if (!(s->pic_enable & mask))
continue;
- pic_set_irq_new(s->parent, i, (s->level & mask) != 0);
+ qemu_set_irq(s->parent[i], (s->level & mask) != 0);
}
}
else
s->level &= ~(1u << irq);
if (s->pic_enable & (1u << irq))
- pic_set_irq_new(s->parent, irq, level);
+ qemu_set_irq(s->parent[irq], level);
vpb_sic_update(s);
}
case 8: /* PICENABLE */
return s->pic_enable;
default:
- printf ("vpb_sic_read: Bad register offset 0x%x\n", offset);
+ printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
return 0;
}
}
vpb_sic_update_pic(s);
break;
default:
- printf ("vpb_sic_write: Bad register offset 0x%x\n", offset);
+ printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
return;
}
vpb_sic_update(s);
vpb_sic_write
};
-static vpb_sic_state *vpb_sic_init(uint32_t base, void *parent, int irq)
+static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
{
vpb_sic_state *s;
+ qemu_irq *qi;
int iomemtype;
s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
if (!s)
return NULL;
- s->handler = vpb_sic_set_irq;
+ qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
s->base = base;
s->parent = parent;
s->irq = irq;
iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
vpb_sic_writefn, s);
- cpu_register_physical_memory(base, 0x00000fff, iomemtype);
+ cpu_register_physical_memory(base, 0x00001000, iomemtype);
/* ??? Save/restore. */
- return s;
+ return qi;
}
/* Board init. */
-/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
-static uint32_t bootloader[] = {
- 0xe3a00000, /* mov r0, #0 */
- 0xe3a01083, /* mov r1, #0x83 */
- 0xe3811c01, /* orr r1, r1, #0x100 */
- 0xe59f2000, /* ldr r2, [pc, #0] */
- 0xe59ff000, /* ldr pc, [pc, #0] */
- 0, /* Address of kernel args. Set by integratorcp_init. */
- 0 /* Kernel entry point. Set by integratorcp_init. */
-};
-
-static void set_kernel_args(uint32_t ram_size, int initrd_size,
- const char *kernel_cmdline)
-{
- uint32_t *p;
-
- p = (uint32_t *)(phys_ram_base + KERNEL_ARGS_ADDR);
- /* ATAG_CORE */
- stl_raw(p++, 5);
- stl_raw(p++, 0x54410001);
- stl_raw(p++, 1);
- stl_raw(p++, 0x1000);
- stl_raw(p++, 0);
- /* ATAG_MEM */
- stl_raw(p++, 4);
- stl_raw(p++, 0x54410002);
- stl_raw(p++, ram_size);
- stl_raw(p++, 0);
- if (initrd_size) {
- /* ATAG_INITRD2 */
- stl_raw(p++, 4);
- stl_raw(p++, 0x54420005);
- stl_raw(p++, INITRD_LOAD_ADDR);
- stl_raw(p++, initrd_size);
- }
- if (kernel_cmdline && *kernel_cmdline) {
- /* ATAG_CMDLINE */
- int cmdline_size;
-
- cmdline_size = strlen(kernel_cmdline);
- memcpy (p + 2, kernel_cmdline, cmdline_size + 1);
- cmdline_size = (cmdline_size >> 2) + 1;
- stl_raw(p++, cmdline_size + 2);
- stl_raw(p++, 0x54410009);
- p += cmdline_size;
- }
- /* ATAG_END */
- stl_raw(p++, 0);
- stl_raw(p++, 0);
-}
+/* The AB and PB boards both use the same core, just with different
+ peripherans and expansion busses. For now we emulate a subset of the
+ PB peripherals and just change the board ID. */
-static void vpb_init(int ram_size, int vga_ram_size, int boot_device,
+static void versatile_init(int ram_size, int vga_ram_size, int boot_device,
DisplayState *ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename)
+ const char *initrd_filename, const char *cpu_model,
+ int board_id)
{
CPUState *env;
- int kernel_size;
- int initrd_size;
+ qemu_irq *pic;
+ qemu_irq *sic;
+ void *scsi_hba;
+ PCIBus *pci_bus;
+ NICInfo *nd;
int n;
- void *pic;
- void *sic;
+ int done_smc = 0;
env = cpu_init();
- cpu_arm_set_model(env, ARM_CPUID_ARM926);
+ if (!cpu_model)
+ cpu_model = "arm926";
+ cpu_arm_set_model(env, cpu_model);
/* ??? RAM shoud repeat to fill physical memory space. */
/* SDRAM at address zero. */
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
+ arm_sysctl_init(0x10000000, 0x41007004);
pic = arm_pic_init_cpu(env);
- pic = pl190_init(0x10140000, pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
+ pic = pl190_init(0x10140000, pic[0], pic[1]);
sic = vpb_sic_init(0x10003000, pic, 31);
- pl050_init(0x10006000, sic, 3, 0);
- pl050_init(0x10007000, sic, 4, 1);
-
- /* TODO: Init PCI NICs. */
- if (nd_table[0].vlan) {
- if (nd_table[0].model == NULL
- || strcmp(nd_table[0].model, "smc91c111") == 0) {
- smc91c111_init(&nd_table[0], 0x10010000, sic, 25);
+ pl050_init(0x10006000, sic[3], 0);
+ pl050_init(0x10007000, sic[4], 1);
+
+ pci_bus = pci_vpb_init(sic, 27, 0);
+ /* The Versatile PCI bridge does not provide access to PCI IO space,
+ so many of the qemu PCI devices are not useable. */
+ for(n = 0; n < nb_nics; n++) {
+ nd = &nd_table[n];
+ if (!nd->model)
+ nd->model = done_smc ? "rtl8139" : "smc91c111";
+ if (strcmp(nd->model, "smc91c111") == 0) {
+ smc91c111_init(nd, 0x10010000, sic[25]);
} else {
- fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
- exit (1);
+ pci_nic_init(pci_bus, nd, -1);
+ }
+ }
+ if (usb_enabled) {
+ usb_ohci_init_pci(pci_bus, 3, -1);
+ }
+ scsi_hba = lsi_scsi_init(pci_bus, -1);
+ for (n = 0; n < MAX_DISKS; n++) {
+ if (bs_table[n]) {
+ lsi_scsi_attach(scsi_hba, bs_table[n], n);
}
}
- pl011_init(0x101f1000, pic, 12, serial_hds[0]);
- pl011_init(0x101f2000, pic, 13, serial_hds[1]);
- pl011_init(0x101f3000, pic, 14, serial_hds[2]);
- pl011_init(0x10009000, sic, 6, serial_hds[3]);
+ pl011_init(0x101f1000, pic[12], serial_hds[0]);
+ pl011_init(0x101f2000, pic[13], serial_hds[1]);
+ pl011_init(0x101f3000, pic[14], serial_hds[2]);
+ pl011_init(0x10009000, sic[6], serial_hds[3]);
- pl080_init(0x10130000, pic, 17);
- sp804_init(0x101e2000, pic, 4);
- sp804_init(0x101e3000, pic, 5);
+ pl080_init(0x10130000, pic[17], 8);
+ sp804_init(0x101e2000, pic[4]);
+ sp804_init(0x101e3000, pic[5]);
/* The versatile/PB actually has a modified Color LCD controller
that includes hardware cursor support from the PL111. */
- pl110_init(ds, 0x10120000, pic, 16, 1);
+ pl110_init(ds, 0x10120000, pic[16], 1);
+
+ pl181_init(0x10005000, sd_bdrv, sic[22], sic[1]);
+#if 0
+ /* Disabled because there's no way of specifying a block device. */
+ pl181_init(0x1000b000, NULL, sic, 23, 2);
+#endif
+ /* Add PL031 Real Time Clock. */
+ pl031_init(0x101e8000,pic[10]);
+
+ /* Memory map for Versatile/PB: */
/* 0x10000000 System registers. */
/* 0x10001000 PCI controller config registers. */
/* 0x10002000 Serial bus interface. */
/* 0x10003000 Secondary interrupt controller. */
/* 0x10004000 AACI (audio). */
- /* 0x10005000 MMCI0. */
+ /* 0x10005000 MMCI0. */
/* 0x10006000 KMI0 (keyboard). */
/* 0x10007000 KMI1 (mouse). */
/* 0x10008000 Character LCD Interface. */
/* 0x10009000 UART3. */
/* 0x1000a000 Smart card 1. */
- /* 0x1000b000 MMCI1. */
+ /* 0x1000b000 MMCI1. */
/* 0x10010000 Ethernet. */
/* 0x10020000 USB. */
/* 0x10100000 SSMC. */
/* 0x101f3000 UART2. */
/* 0x101f4000 SSPI. */
- /* Load the kernel. */
- if (!kernel_filename) {
- fprintf(stderr, "Kernel image must be specified\n");
- exit(1);
- }
- kernel_size = load_image(kernel_filename,
- phys_ram_base + KERNEL_LOAD_ADDR);
- if (kernel_size < 0) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
- exit(1);
- }
- if (initrd_filename) {
- initrd_size = load_image(initrd_filename,
- phys_ram_base + INITRD_LOAD_ADDR);
- if (initrd_size < 0) {
- fprintf(stderr, "qemu: could not load initrd '%s'\n",
- initrd_filename);
- exit(1);
- }
- } else {
- initrd_size = 0;
- }
- bootloader[5] = KERNEL_ARGS_ADDR;
- bootloader[6] = KERNEL_LOAD_ADDR;
- for (n = 0; n < sizeof(bootloader) / 4; n++)
- stl_raw(phys_ram_base + (n * 4), bootloader[n]);
- set_kernel_args(ram_size, initrd_size, kernel_cmdline);
+ arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline,
+ initrd_filename, board_id, 0x0);
+}
+
+static void vpb_init(int ram_size, int vga_ram_size, int boot_device,
+ DisplayState *ds, const char **fd_filename, int snapshot,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+ versatile_init(ram_size, vga_ram_size, boot_device,
+ ds, fd_filename, snapshot,
+ kernel_filename, kernel_cmdline,
+ initrd_filename, cpu_model, 0x183);
+}
+
+static void vab_init(int ram_size, int vga_ram_size, int boot_device,
+ DisplayState *ds, const char **fd_filename, int snapshot,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+ versatile_init(ram_size, vga_ram_size, boot_device,
+ ds, fd_filename, snapshot,
+ kernel_filename, kernel_cmdline,
+ initrd_filename, cpu_model, 0x25e);
}
QEMUMachine versatilepb_machine = {
"ARM Versatile/PB (ARM926EJ-S)",
vpb_init,
};
+
+QEMUMachine versatileab_machine = {
+ "versatileab",
+ "ARM Versatile/AB (ARM926EJ-S)",
+ vab_init,
+};
projects / qemu / blobdiff