* QEMU USB OHCI Emulation
* Copyright (c) 2004 Gianni Tedesco
* Copyright (c) 2006 CodeSourcery
+ * Copyright (c) 2006 Openedhand Ltd.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
uint32_t ctrl;
} OHCIPort;
+enum ohci_type {
+ OHCI_TYPE_PCI,
+ OHCI_TYPE_PXA
+};
+
typedef struct {
- struct PCIDevice pci_dev;
+ qemu_irq irq;
+ enum ohci_type type;
target_phys_addr_t mem_base;
int mem;
int num_ports;
+ const char *name;
QEMUTimer *eof_timer;
int64_t sof_time;
uint32_t rhdesc_a, rhdesc_b;
uint32_t rhstatus;
OHCIPort rhport[OHCI_MAX_PORTS];
+
+ /* PXA27x Non-OHCI events */
+ uint32_t hstatus;
+ uint32_t hmask;
+ uint32_t hreset;
+ uint32_t htest;
+
+ /* Active packets. */
+ uint32_t old_ctl;
+ USBPacket usb_packet;
+ uint8_t usb_buf[8192];
+ uint32_t async_td;
+ int async_complete;
+
} OHCIState;
/* Host Controller Communications Area */
uint32_t done;
};
+static void ohci_bus_stop(OHCIState *ohci);
+
/* Bitfields for the first word of an Endpoint Desciptor. */
#define OHCI_ED_FA_SHIFT 0
#define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
#define OHCI_CC_BUFFEROVERRUN 0xc
#define OHCI_CC_BUFFERUNDERRUN 0xd
+#define OHCI_HRESET_FSBIR (1 << 0)
+
/* Update IRQ levels */
static inline void ohci_intr_update(OHCIState *ohci)
{
(ohci->intr_status & ohci->intr))
level = 1;
- pci_set_irq(&ohci->pci_dev, 0, level);
+ qemu_set_irq(ohci->irq, level);
}
/* Set an interrupt */
else
port->ctrl &= ~OHCI_PORT_LSDA;
port->port.dev = dev;
+
+ /* notify of remote-wakeup */
+ if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND)
+ ohci_set_interrupt(s, OHCI_INTR_RD);
+
/* send the attach message */
- dev->handle_packet(dev,
- USB_MSG_ATTACH, 0, 0, NULL, 0);
+ usb_send_msg(dev, USB_MSG_ATTACH);
dprintf("usb-ohci: Attached port %d\n", port1->index);
} else {
/* set connect status */
dev = port->port.dev;
if (dev) {
/* send the detach message */
- dev->handle_packet(dev,
- USB_MSG_DETACH, 0, 0, NULL, 0);
+ usb_send_msg(dev, USB_MSG_DETACH);
}
port->port.dev = NULL;
dprintf("usb-ohci: Detached port %d\n", port1->index);
}
/* Reset the controller */
-static void ohci_reset(OHCIState *ohci)
+static void ohci_reset(void *opaque)
{
+ OHCIState *ohci = opaque;
OHCIPort *port;
int i;
+ ohci_bus_stop(ohci);
ohci->ctl = 0;
+ ohci->old_ctl = 0;
ohci->status = 0;
ohci->intr_status = 0;
ohci->intr = OHCI_INTR_MIE;
if (port->port.dev)
ohci_attach(&port->port, port->port.dev);
}
- dprintf("usb-ohci: Reset %s\n", ohci->pci_dev.name);
+ if (ohci->async_td) {
+ usb_cancel_packet(&ohci->usb_packet);
+ ohci->async_td = 0;
+ }
+ dprintf("usb-ohci: Reset %s\n", ohci->name);
}
/* Get an array of dwords from main memory */
if (n == len)
return;
ptr = td->be & ~0xfffu;
+ buf += n;
cpu_physical_memory_rw(ptr, buf, len - n, write);
}
+static void ohci_process_lists(OHCIState *ohci);
+
+static void ohci_async_complete_packet(USBPacket * packet, void *opaque)
+{
+ OHCIState *ohci = opaque;
+#ifdef DEBUG_PACKET
+ dprintf("Async packet complete\n");
+#endif
+ ohci->async_complete = 1;
+ ohci_process_lists(ohci);
+}
+
/* Service a transport descriptor.
Returns nonzero to terminate processing of this endpoint. */
{
int dir;
size_t len = 0;
- uint8_t buf[8192];
char *str = NULL;
int pid;
int ret;
struct ohci_td td;
uint32_t addr;
int flag_r;
+ int completion;
addr = ed->head & OHCI_DPTR_MASK;
+ /* See if this TD has already been submitted to the device. */
+ completion = (addr == ohci->async_td);
+ if (completion && !ohci->async_complete) {
+#ifdef DEBUG_PACKET
+ dprintf("Skipping async TD\n");
+#endif
+ return 1;
+ }
if (!ohci_read_td(addr, &td)) {
fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
return 0;
return 1;
}
if (td.cbp && td.be) {
- len = (td.be - td.cbp) + 1;
- if (len && dir != OHCI_TD_DIR_IN) {
- ohci_copy_td(&td, buf, len, 0);
+ if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
+ len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
+ } else {
+ len = (td.be - td.cbp) + 1;
+ }
+
+ if (len && dir != OHCI_TD_DIR_IN && !completion) {
+ ohci_copy_td(&td, ohci->usb_buf, len, 0);
}
}
if (len >= 0 && dir != OHCI_TD_DIR_IN) {
dprintf(" data:");
for (i = 0; i < len; i++)
- printf(" %.2x", buf[i]);
+ printf(" %.2x", ohci->usb_buf[i]);
dprintf("\n");
}
#endif
- ret = USB_RET_NODEV;
- for (i = 0; i < ohci->num_ports; i++) {
- dev = ohci->rhport[i].port.dev;
- if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
- continue;
-
- ret = dev->handle_packet(dev, pid, OHCI_BM(ed->flags, ED_FA),
- OHCI_BM(ed->flags, ED_EN), buf, len);
- if (ret != USB_RET_NODEV)
- break;
- }
+ if (completion) {
+ ret = ohci->usb_packet.len;
+ ohci->async_td = 0;
+ ohci->async_complete = 0;
+ } else {
+ ret = USB_RET_NODEV;
+ for (i = 0; i < ohci->num_ports; i++) {
+ dev = ohci->rhport[i].port.dev;
+ if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
+ continue;
+
+ if (ohci->async_td) {
+ /* ??? The hardware should allow one active packet per
+ endpoint. We only allow one active packet per controller.
+ This should be sufficient as long as devices respond in a
+ timely manner.
+ */
#ifdef DEBUG_PACKET
- dprintf("ret=%d\n", ret);
+ dprintf("Too many pending packets\n");
#endif
+ return 1;
+ }
+ ohci->usb_packet.pid = pid;
+ ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
+ ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
+ ohci->usb_packet.data = ohci->usb_buf;
+ ohci->usb_packet.len = len;
+ ohci->usb_packet.complete_cb = ohci_async_complete_packet;
+ ohci->usb_packet.complete_opaque = ohci;
+ ret = dev->handle_packet(dev, &ohci->usb_packet);
+ if (ret != USB_RET_NODEV)
+ break;
+ }
+#ifdef DEBUG_PACKET
+ dprintf("ret=%d\n", ret);
+#endif
+ if (ret == USB_RET_ASYNC) {
+ ohci->async_td = addr;
+ return 1;
+ }
+ }
if (ret >= 0) {
if (dir == OHCI_TD_DIR_IN) {
- ohci_copy_td(&td, buf, ret, 1);
+ ohci_copy_td(&td, ohci->usb_buf, ret, 1);
#ifdef DEBUG_PACKET
dprintf(" data:");
for (i = 0; i < ret; i++)
- printf(" %.2x", buf[i]);
+ printf(" %.2x", ohci->usb_buf[i]);
dprintf("\n");
#endif
} else {
next_ed = ed.next & OHCI_DPTR_MASK;
- if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K))
+ if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
+ uint32_t addr;
+ /* Cancel pending packets for ED that have been paused. */
+ addr = ed.head & OHCI_DPTR_MASK;
+ if (ohci->async_td && addr == ohci->async_td) {
+ usb_cancel_packet(&ohci->usb_packet);
+ ohci->async_td = 0;
+ }
continue;
+ }
/* Skip isochronous endpoints. */
if (ed.flags & OHCI_ED_F)
ohci_set_interrupt(ohci, OHCI_INTR_SF);
}
+/* Process Control and Bulk lists. */
+static void ohci_process_lists(OHCIState *ohci)
+{
+ if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
+ if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
+ dprintf("usb-ohci: head %x, cur %x\n", ohci->ctrl_head, ohci->ctrl_cur);
+ if (!ohci_service_ed_list(ohci, ohci->ctrl_head)) {
+ ohci->ctrl_cur = 0;
+ ohci->status &= ~OHCI_STATUS_CLF;
+ }
+ }
+
+ if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
+ if (!ohci_service_ed_list(ohci, ohci->bulk_head)) {
+ ohci->bulk_cur = 0;
+ ohci->status &= ~OHCI_STATUS_BLF;
+ }
+ }
+}
+
/* Do frame processing on frame boundary */
static void ohci_frame_boundary(void *opaque)
{
n = ohci->frame_number & 0x1f;
ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]));
}
- if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
- if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
- dprintf("usb-ohci: head %x, cur %x\n", ohci->ctrl_head, ohci->ctrl_cur);
- if (!ohci_service_ed_list(ohci, ohci->ctrl_head)) {
- ohci->ctrl_cur = 0;
- ohci->status &= ~OHCI_STATUS_CLF;
- }
- }
- if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
- if (!ohci_service_ed_list(ohci, ohci->bulk_head)) {
- ohci->bulk_cur = 0;
- ohci->status &= ~OHCI_STATUS_BLF;
- }
+ /* Cancel all pending packets if either of the lists has been disabled. */
+ if (ohci->async_td &&
+ ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
+ usb_cancel_packet(&ohci->usb_packet);
+ ohci->async_td = 0;
}
+ ohci->old_ctl = ohci->ctl;
+ ohci_process_lists(ohci);
/* Frame boundary, so do EOF stuf here */
ohci->frt = ohci->fit;
ohci);
if (ohci->eof_timer == NULL) {
- fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n",
- ohci->pci_dev.name);
+ fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n", ohci->name);
/* TODO: Signal unrecoverable error */
return 0;
}
- dprintf("usb-ohci: %s: USB Operational\n", ohci->pci_dev.name);
+ dprintf("usb-ohci: %s: USB Operational\n", ohci->name);
ohci_sof(ohci);
{
if (ohci->eof_timer)
qemu_del_timer(ohci->eof_timer);
+ ohci->eof_timer = NULL;
}
/* Sets a flag in a port status register but only set it if the port is
if (val != ohci->fi) {
dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
- ohci->pci_dev.name, ohci->fi, ohci->fi);
+ ohci->name, ohci->fi, ohci->fi);
}
ohci->fi = val;
break;
case OHCI_USB_SUSPEND:
ohci_bus_stop(ohci);
- dprintf("usb-ohci: %s: USB Suspended\n", ohci->pci_dev.name);
+ dprintf("usb-ohci: %s: USB Suspended\n", ohci->name);
break;
case OHCI_USB_RESUME:
- dprintf("usb-ohci: %s: USB Resume\n", ohci->pci_dev.name);
+ dprintf("usb-ohci: %s: USB Resume\n", ohci->name);
break;
case OHCI_USB_RESET:
- dprintf("usb-ohci: %s: USB Reset\n", ohci->pci_dev.name);
+ ohci_reset(ohci);
+ dprintf("usb-ohci: %s: USB Reset\n", ohci->name);
break;
}
}
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
dprintf("usb-ohci: port %d: RESET\n", portnum);
- port->port.dev->handle_packet(port->port.dev, USB_MSG_RESET,
- 0, 0, NULL, 0);
+ usb_send_msg(port->port.dev, USB_MSG_RESET);
port->ctrl &= ~OHCI_PORT_PRS;
/* ??? Should this also set OHCI_PORT_PESC. */
port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
case 20: /* HcRhStatus */
return ohci->rhstatus;
+ /* PXA27x specific registers */
+ case 24: /* HcStatus */
+ return ohci->hstatus & ohci->hmask;
+
+ case 25: /* HcHReset */
+ return ohci->hreset;
+
+ case 26: /* HcHInterruptEnable */
+ return ohci->hmask;
+
+ case 27: /* HcHInterruptTest */
+ return ohci->htest;
+
default:
fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
return 0xffffffff;
ohci_set_hub_status(ohci, val);
break;
+ /* PXA27x specific registers */
+ case 24: /* HcStatus */
+ ohci->hstatus &= ~(val & ohci->hmask);
+
+ case 25: /* HcHReset */
+ ohci->hreset = val & ~OHCI_HRESET_FSBIR;
+ if (val & OHCI_HRESET_FSBIR)
+ ohci_reset(ohci);
+ break;
+
+ case 26: /* HcHInterruptEnable */
+ ohci->hmask = val;
+ break;
+
+ case 27: /* HcHInterruptTest */
+ ohci->htest = val;
+ break;
+
default:
fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
break;
ohci_mem_write
};
-static void ohci_mapfunc(PCIDevice *pci_dev, int i,
- uint32_t addr, uint32_t size, int type)
+static void usb_ohci_init(OHCIState *ohci, int num_ports, int devfn,
+ qemu_irq irq, enum ohci_type type, const char *name)
{
- OHCIState *ohci = (OHCIState *)pci_dev;
- ohci->mem_base = addr;
- cpu_register_physical_memory(addr, size, ohci->mem);
-}
-
-void usb_ohci_init(struct PCIBus *bus, int num_ports, int devfn)
-{
- OHCIState *ohci;
- int vid = 0x106b;
- int did = 0x003f;
int i;
-
if (usb_frame_time == 0) {
#if OHCI_TIME_WARP
usb_frame_time = ticks_per_sec;
usb_frame_time, usb_bit_time);
}
- ohci = (OHCIState *)pci_register_device(bus, "OHCI USB", sizeof(*ohci),
- devfn, NULL, NULL);
+ ohci->mem = cpu_register_io_memory(0, ohci_readfn, ohci_writefn, ohci);
+ ohci->name = name;
+
+ ohci->irq = irq;
+ ohci->type = type;
+
+ ohci->num_ports = num_ports;
+ for (i = 0; i < num_ports; i++) {
+ qemu_register_usb_port(&ohci->rhport[i].port, ohci, i, ohci_attach);
+ }
+
+ ohci->async_td = 0;
+ qemu_register_reset(ohci_reset, ohci);
+ ohci_reset(ohci);
+}
+
+typedef struct {
+ PCIDevice pci_dev;
+ OHCIState state;
+} OHCIPCIState;
+
+static void ohci_mapfunc(PCIDevice *pci_dev, int i,
+ uint32_t addr, uint32_t size, int type)
+{
+ OHCIPCIState *ohci = (OHCIPCIState *)pci_dev;
+ ohci->state.mem_base = addr;
+ cpu_register_physical_memory(addr, size, ohci->state.mem);
+}
+
+void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn)
+{
+ OHCIPCIState *ohci;
+ int vid = 0x106b;
+ int did = 0x003f;
+
+ ohci = (OHCIPCIState *)pci_register_device(bus, "OHCI USB", sizeof(*ohci),
+ devfn, NULL, NULL);
if (ohci == NULL) {
fprintf(stderr, "usb-ohci: Failed to register PCI device\n");
return;
ohci->pci_dev.config[0x0b] = 0xc;
ohci->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
- ohci->mem = cpu_register_io_memory(0, ohci_readfn, ohci_writefn, ohci);
+ usb_ohci_init(&ohci->state, num_ports, devfn, ohci->pci_dev.irq[0],
+ OHCI_TYPE_PCI, ohci->pci_dev.name);
pci_register_io_region((struct PCIDevice *)ohci, 0, 256,
PCI_ADDRESS_SPACE_MEM, ohci_mapfunc);
+}
- ohci->num_ports = num_ports;
- for (i = 0; i < num_ports; i++) {
- qemu_register_usb_port(&ohci->rhport[i].port, ohci, i, ohci_attach);
- }
+void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
+ qemu_irq irq)
+{
+ OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
- ohci_reset(ohci);
+ usb_ohci_init(ohci, num_ports, devfn, irq,
+ OHCI_TYPE_PXA, "OHCI USB");
+ ohci->mem_base = base;
+
+ cpu_register_physical_memory(ohci->mem_base, 0x1000, ohci->mem);
}
projects / qemu / blobdiff