/*
- * QEMU Sun4m System Emulator
+ * QEMU TCX Frame buffer
*
- * Copyright (c) 2003-2004 Fabrice Bellard
+ * Copyright (c) 2003-2005 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
#define MAXX 1024
#define MAXY 768
-#define XSZ (8*80)
-#define YSZ (24*11)
-#define XOFF (MAXX-XSZ)
-#define YOFF (MAXY-YSZ)
+#define TCX_DAC_NREGS 16
typedef struct TCXState {
uint32_t addr;
DisplayState *ds;
uint8_t *vram;
+ unsigned long vram_offset;
+ uint16_t width, height;
+ uint8_t r[256], g[256], b[256];
+ uint8_t dac_index, dac_state;
} TCXState;
-static TCXState *ts;
+static void tcx_draw_line32(TCXState *s1, uint8_t *d,
+ const uint8_t *s, int width)
+{
+ int x;
+ uint8_t val;
+
+ for(x = 0; x < width; x++) {
+ val = *s++;
+ *d++ = s1->b[val];
+ *d++ = s1->g[val];
+ *d++ = s1->r[val];
+ d++;
+ }
+}
-void vga_update_display()
+static void tcx_draw_line24(TCXState *s1, uint8_t *d,
+ const uint8_t *s, int width)
{
- dpy_update(ts->ds, 0, 0, XSZ, YSZ);
+ int x;
+ uint8_t val;
+
+ for(x = 0; x < width; x++) {
+ val = *s++;
+ *d++ = s1->b[val];
+ *d++ = s1->g[val];
+ *d++ = s1->r[val];
+ }
}
-void vga_invalidate_display() {}
+static void tcx_draw_line8(TCXState *s1, uint8_t *d,
+ const uint8_t *s, int width)
+{
+ int x;
+ uint8_t val;
-static uint32_t tcx_mem_readb(void *opaque, target_phys_addr_t addr)
+ for(x = 0; x < width; x++) {
+ val = *s++;
+ /* XXX translate between palettes? */
+ *d++ = val;
+ }
+}
+
+/* Fixed line length 1024 allows us to do nice tricks not possible on
+ VGA... */
+void tcx_update_display(void *opaque)
+{
+ TCXState *ts = opaque;
+ uint32_t page;
+ int y, page_min, page_max, y_start, dd, ds;
+ uint8_t *d, *s;
+ void (*f)(TCXState *s1, uint8_t *d, const uint8_t *s, int width);
+
+ if (ts->ds->depth == 0)
+ return;
+ page = ts->vram_offset;
+ y_start = -1;
+ page_min = 0x7fffffff;
+ page_max = -1;
+ d = ts->ds->data;
+ s = ts->vram;
+ dd = ts->ds->linesize;
+ ds = 1024;
+
+ switch (ts->ds->depth) {
+ case 32:
+ f = tcx_draw_line32;
+ break;
+ case 24:
+ f = tcx_draw_line24;
+ break;
+ default:
+ case 8:
+ f = tcx_draw_line8;
+ break;
+ case 0:
+ return;
+ }
+
+ for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
+ if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
+ if (y_start < 0)
+ y_start = y;
+ if (page < page_min)
+ page_min = page;
+ if (page > page_max)
+ page_max = page;
+ f(ts, d, s, ts->width);
+ d += dd;
+ s += ds;
+ f(ts, d, s, ts->width);
+ d += dd;
+ s += ds;
+ f(ts, d, s, ts->width);
+ d += dd;
+ s += ds;
+ f(ts, d, s, ts->width);
+ d += dd;
+ s += ds;
+ } else {
+ if (y_start >= 0) {
+ /* flush to display */
+ dpy_update(ts->ds, 0, y_start,
+ ts->width, y - y_start);
+ y_start = -1;
+ }
+ d += dd * 4;
+ s += ds * 4;
+ }
+ }
+ if (y_start >= 0) {
+ /* flush to display */
+ dpy_update(ts->ds, 0, y_start,
+ ts->width, y - y_start);
+ }
+ /* reset modified pages */
+ if (page_max != -1) {
+ cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
+ VGA_DIRTY_FLAG);
+ }
+}
+
+void tcx_invalidate_display(void *opaque)
{
TCXState *s = opaque;
- uint32_t saddr;
- unsigned int x, y;
+ int i;
- saddr = addr - s->addr - YOFF*MAXX - XOFF;
- y = saddr / MAXX;
- x = saddr - y * MAXX;
- if (x < XSZ && y < YSZ) {
- return s->vram[y * XSZ + x];
+ for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
+ cpu_physical_memory_set_dirty(s->vram_offset + i);
}
- return 0;
}
-static uint32_t tcx_mem_readw(void *opaque, target_phys_addr_t addr)
+static void tcx_save(QEMUFile *f, void *opaque)
{
- uint32_t v;
-#ifdef TARGET_WORDS_BIGENDIAN
- v = tcx_mem_readb(opaque, addr) << 8;
- v |= tcx_mem_readb(opaque, addr + 1);
-#else
- v = tcx_mem_readb(opaque, addr);
- v |= tcx_mem_readb(opaque, addr + 1) << 8;
-#endif
- return v;
+ TCXState *s = opaque;
+
+ qemu_put_be32s(f, (uint32_t *)&s->addr);
+ qemu_put_be32s(f, (uint32_t *)&s->vram);
+ qemu_put_be16s(f, (uint16_t *)&s->height);
+ qemu_put_be16s(f, (uint16_t *)&s->width);
+ qemu_put_buffer(f, s->r, 256);
+ qemu_put_buffer(f, s->g, 256);
+ qemu_put_buffer(f, s->b, 256);
+ qemu_put_8s(f, &s->dac_index);
+ qemu_put_8s(f, &s->dac_state);
}
-static uint32_t tcx_mem_readl(void *opaque, target_phys_addr_t addr)
+static int tcx_load(QEMUFile *f, void *opaque, int version_id)
{
- uint32_t v;
-#ifdef TARGET_WORDS_BIGENDIAN
- v = tcx_mem_readb(opaque, addr) << 24;
- v |= tcx_mem_readb(opaque, addr + 1) << 16;
- v |= tcx_mem_readb(opaque, addr + 2) << 8;
- v |= tcx_mem_readb(opaque, addr + 3);
-#else
- v = tcx_mem_readb(opaque, addr);
- v |= tcx_mem_readb(opaque, addr + 1) << 8;
- v |= tcx_mem_readb(opaque, addr + 2) << 16;
- v |= tcx_mem_readb(opaque, addr + 3) << 24;
-#endif
- return v;
+ TCXState *s = opaque;
+
+ if (version_id != 1)
+ return -EINVAL;
+
+ qemu_get_be32s(f, (uint32_t *)&s->addr);
+ qemu_get_be32s(f, (uint32_t *)&s->vram);
+ qemu_get_be16s(f, (uint16_t *)&s->height);
+ qemu_get_be16s(f, (uint16_t *)&s->width);
+ qemu_get_buffer(f, s->r, 256);
+ qemu_get_buffer(f, s->g, 256);
+ qemu_get_buffer(f, s->b, 256);
+ qemu_get_8s(f, &s->dac_index);
+ qemu_get_8s(f, &s->dac_state);
+ return 0;
}
-static void tcx_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void tcx_reset(void *opaque)
{
TCXState *s = opaque;
- uint32_t saddr;
- unsigned int x, y;
- char *sptr;
-
- saddr = addr - s->addr - YOFF*MAXX - XOFF;
- y = saddr / MAXX;
- x = saddr - y * MAXX;
- if (x < XSZ && y < YSZ) {
- sptr = s->ds->data;
- if (sptr) {
- if (s->ds->depth == 24 || s->ds->depth == 32) {
- /* XXX need to do CLUT translation */
- sptr[y * s->ds->linesize + x*4] = val & 0xff;
- sptr[y * s->ds->linesize + x*4+1] = val & 0xff;
- sptr[y * s->ds->linesize + x*4+2] = val & 0xff;
- }
- else if (s->ds->depth == 8) {
- sptr[y * s->ds->linesize + x] = val & 0xff;
- }
- }
- cpu_physical_memory_set_dirty(addr);
- s->vram[y * XSZ + x] = val & 0xff;
- }
+
+ /* Initialize palette */
+ memset(s->r, 0, 256);
+ memset(s->g, 0, 256);
+ memset(s->b, 0, 256);
+ s->r[255] = s->g[255] = s->b[255] = 255;
+ memset(s->vram, 0, MAXX*MAXY);
+ cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + MAXX*MAXY,
+ VGA_DIRTY_FLAG);
+ s->dac_index = 0;
+ s->dac_state = 0;
}
-static void tcx_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- tcx_mem_writeb(opaque, addr, (val >> 8) & 0xff);
- tcx_mem_writeb(opaque, addr + 1, val & 0xff);
-#else
- tcx_mem_writeb(opaque, addr, val & 0xff);
- tcx_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-#endif
+ return 0;
}
-static void tcx_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- tcx_mem_writeb(opaque, addr, (val >> 24) & 0xff);
- tcx_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
- tcx_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
- tcx_mem_writeb(opaque, addr + 3, val & 0xff);
-#else
- tcx_mem_writeb(opaque, addr, val & 0xff);
- tcx_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
- tcx_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
- tcx_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
-#endif
+ TCXState *s = opaque;
+ uint32_t saddr;
+
+ saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
+ switch (saddr) {
+ case 0:
+ s->dac_index = val >> 24;
+ s->dac_state = 0;
+ break;
+ case 1:
+ switch (s->dac_state) {
+ case 0:
+ s->r[s->dac_index] = val >> 24;
+ s->dac_state++;
+ break;
+ case 1:
+ s->g[s->dac_index] = val >> 24;
+ s->dac_state++;
+ break;
+ case 2:
+ s->b[s->dac_index] = val >> 24;
+ default:
+ s->dac_state = 0;
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ return;
}
-static CPUReadMemoryFunc *tcx_mem_read[3] = {
- tcx_mem_readb,
- tcx_mem_readw,
- tcx_mem_readl,
+static CPUReadMemoryFunc *tcx_dac_read[3] = {
+ tcx_dac_readl,
+ tcx_dac_readl,
+ tcx_dac_readl,
};
-static CPUWriteMemoryFunc *tcx_mem_write[3] = {
- tcx_mem_writeb,
- tcx_mem_writew,
- tcx_mem_writel,
+static CPUWriteMemoryFunc *tcx_dac_write[3] = {
+ tcx_dac_writel,
+ tcx_dac_writel,
+ tcx_dac_writel,
};
-void tcx_init(DisplayState *ds, uint32_t addr)
+void *tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
+ unsigned long vram_offset, int vram_size, int width, int height)
{
TCXState *s;
- int tcx_io_memory;
+ int io_memory;
s = qemu_mallocz(sizeof(TCXState));
if (!s)
- return;
+ return NULL;
s->ds = ds;
s->addr = addr;
- ts = s;
- tcx_io_memory = cpu_register_io_memory(0, tcx_mem_read, tcx_mem_write, s);
- cpu_register_physical_memory(addr, 0x100000,
- tcx_io_memory);
- s->vram = qemu_mallocz(XSZ*YSZ);
- dpy_resize(s->ds, XSZ, YSZ);
+ s->vram = vram_base;
+ s->vram_offset = vram_offset;
+ s->width = width;
+ s->height = height;
+
+ cpu_register_physical_memory(addr + 0x800000, vram_size, vram_offset);
+ io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
+ cpu_register_physical_memory(addr + 0x200000, TCX_DAC_NREGS, io_memory);
+
+ register_savevm("tcx", addr, 1, tcx_save, tcx_load, s);
+ qemu_register_reset(tcx_reset, s);
+ tcx_reset(s);
+ dpy_resize(s->ds, width, height);
+ return s;
}
-void vga_screen_dump(const char *filename)
+void tcx_screen_dump(void *opaque, const char *filename)
{
- TCXState *s = ts;
+ TCXState *s = opaque;
FILE *f;
- uint8_t *d, *d1;
- unsigned int v;
+ uint8_t *d, *d1, v;
int y, x;
f = fopen(filename, "wb");
if (!f)
- return -1;
- fprintf(f, "P6\n%d %d\n%d\n",
- XSZ, YSZ, 255);
+ return;
+ fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
d1 = s->vram;
- for(y = 0; y < YSZ; y++) {
+ for(y = 0; y < s->height; y++) {
d = d1;
- for(x = 0; x < XSZ; x++) {
+ for(x = 0; x < s->width; x++) {
v = *d;
- fputc((v) & 0xff, f);
- fputc((v) & 0xff, f);
- fputc((v) & 0xff, f);
+ fputc(s->r[v], f);
+ fputc(s->g[v], f);
+ fputc(s->b[v], f);
d++;
}
- d1 += XSZ;
+ d1 += MAXX;
}
fclose(f);
return;
projects / qemu / blobdiff