#define MAX_CPUS 16
struct hwdef {
- target_ulong iommu_base, slavio_base;
- target_ulong intctl_base, counter_base, nvram_base, ms_kb_base, serial_base;
- target_ulong fd_base;
- target_ulong dma_base, esp_base, le_base;
- target_ulong tcx_base, cs_base;
+ target_phys_addr_t iommu_base, slavio_base;
+ target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
+ target_phys_addr_t serial_base, fd_base;
+ target_phys_addr_t dma_base, esp_base, le_base;
+ target_phys_addr_t tcx_base, cs_base, power_base;
long vram_size, nvram_size;
// IRQ numbers are not PIL ones, but master interrupt controller register
// bit numbers
- int intctl_g_intr, esp_irq, le_irq, cpu_irq, clock_irq, clock1_irq;
+ int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
int machine_id; // For NVRAM
uint32_t intbit_to_level[32];
m48t59_write(nvram, addr + max - 1, '\0');
}
+static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
+ const unsigned char *str)
+{
+ uint32_t len;
+
+ len = strlen(str) + 1;
+ nvram_set_string(nvram, addr, str, len);
+
+ return addr + len;
+}
+
+static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
+ uint32_t end)
+{
+ unsigned int i, sum;
+
+ // Length divided by 16
+ m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
+ m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
+ // Checksum
+ sum = m48t59_read(nvram, start);
+ for (i = 0; i < 14; i++) {
+ sum += m48t59_read(nvram, start + 2 + i);
+ sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
+ }
+ m48t59_write(nvram, start + 1, sum & 0xff);
+}
+
static m48t59_t *nvram;
extern int nographic;
int machine_id)
{
unsigned char tmp = 0;
- int i, j;
+ unsigned int i, j;
+ uint32_t start, end;
// Try to match PPC NVRAM
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
nvram_set_word(nvram, 0x56, height);
nvram_set_word(nvram, 0x58, depth);
+ // OpenBIOS nvram variables
+ // Variable partition
+ start = 252;
+ m48t59_write(nvram, start, 0x70);
+ nvram_set_string(nvram, start + 4, "system", 12);
+
+ end = start + 16;
+ for (i = 0; i < nb_prom_envs; i++)
+ end = nvram_set_var(nvram, end, prom_envs[i]);
+
+ m48t59_write(nvram, end++ , 0);
+ end = start + ((end - start + 15) & ~15);
+ nvram_finish_partition(nvram, start, end);
+
+ // free partition
+ start = end;
+ m48t59_write(nvram, start, 0x7f);
+ nvram_set_string(nvram, start + 4, "free", 12);
+
+ end = 0x1fd0;
+ nvram_finish_partition(nvram, start, end);
+
// Sun4m specific use
- i = 0x1fd8;
+ start = i = 0x1fd8;
m48t59_write(nvram, i++, 0x01);
m48t59_write(nvram, i++, machine_id);
j = 0;
m48t59_write(nvram, i, macaddr[j]);
/* Calculate checksum */
- for (i = 0x1fd8; i < 0x1fe7; i++) {
- tmp ^= m48t59_read(nvram, i);
+ for (i = start; i < start + 15; i++) {
+ tmp ^= m48t59_read(nvram, i);
}
- m48t59_write(nvram, 0x1fe7, tmp);
+ m48t59_write(nvram, start + 15, tmp);
}
static void *slavio_intctl;
static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
+
+ cpu_reset(env);
+ env->halted = 0;
+}
+
+static void secondary_cpu_reset(void *opaque)
+{
+ CPUState *env = opaque;
+
cpu_reset(env);
+ env->halted = 1;
}
static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
{
CPUState *env, *envs[MAX_CPUS];
unsigned int i;
- void *iommu, *dma, *main_esp, *main_lance = NULL;
+ void *iommu, *espdma, *ledma, *main_esp;
const sparc_def_t *def;
- qemu_irq *slavio_irq;
+ qemu_irq *slavio_irq, *slavio_cpu_irq,
+ *espdma_irq, *ledma_irq;
/* init CPUs */
sparc_find_by_name(cpu_model, &def);
env = cpu_init();
cpu_sparc_register(env, def);
envs[i] = env;
- if (i != 0)
+ if (i == 0) {
+ qemu_register_reset(main_cpu_reset, env);
+ } else {
+ qemu_register_reset(secondary_cpu_reset, env);
env->halted = 1;
+ }
register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
- qemu_register_reset(main_cpu_reset, env);
}
/* allocate RAM */
cpu_register_physical_memory(0, ram_size, 0);
iommu = iommu_init(hwdef->iommu_base);
slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
- hwdef->intctl_base + 0x10000,
+ hwdef->intctl_base + 0x10000ULL,
&hwdef->intbit_to_level[0],
- &slavio_irq);
+ &slavio_irq, &slavio_cpu_irq,
+ hwdef->clock_irq);
for(i = 0; i < smp_cpus; i++) {
slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
}
- dma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
- slavio_irq[hwdef->le_irq], iommu);
-
+ espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
+ iommu, &espdma_irq);
+ ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
+ slavio_irq[hwdef->le_irq], iommu, &ledma_irq);
+
+ if (graphic_depth != 8 && graphic_depth != 24) {
+ fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
+ exit (1);
+ }
tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size,
- hwdef->vram_size, graphic_width, graphic_height);
+ hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
if (nd_table[0].vlan) {
if (nd_table[0].model == NULL
|| strcmp(nd_table[0].model, "lance") == 0) {
- main_lance = lance_init(&nd_table[0], hwdef->le_base, dma,
- slavio_irq[hwdef->le_irq]);
+ lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
exit (1);
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
hwdef->nvram_size, 8);
for (i = 0; i < MAX_CPUS; i++) {
- slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE,
- hwdef->clock_irq, 0, i, slavio_intctl);
+ slavio_timer_init(hwdef->counter_base +
+ (target_phys_addr_t)(i * TARGET_PAGE_SIZE),
+ slavio_cpu_irq[i], 0);
}
- slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2,
- (unsigned int)-1, slavio_intctl);
+ slavio_timer_init(hwdef->counter_base + 0x10000ULL,
+ slavio_irq[hwdef->clock1_irq], 2);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
serial_hds[1], serial_hds[0]);
fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table);
- main_esp = esp_init(bs_table, hwdef->esp_base, dma);
+ main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq);
for (i = 0; i < MAX_DISKS; i++) {
if (bs_table[i]) {
}
}
- slavio_misc = slavio_misc_init(hwdef->slavio_base,
+ slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base,
slavio_irq[hwdef->me_irq]);
- if (hwdef->cs_base != (target_ulong)-1)
+ if (hwdef->cs_base != (target_phys_addr_t)-1)
cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
- sparc32_dma_set_reset_data(dma, main_esp, main_lance);
}
static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device,
.iommu_base = 0x10000000,
.tcx_base = 0x50000000,
.cs_base = 0x6c000000,
- .slavio_base = 0x71000000,
+ .slavio_base = 0x70000000,
.ms_kb_base = 0x71000000,
.serial_base = 0x71100000,
.nvram_base = 0x71200000,
.dma_base = 0x78400000,
.esp_base = 0x78800000,
.le_base = 0x78c00000,
+ .power_base = 0x7a000000,
.vram_size = 0x00100000,
.nvram_size = 0x2000,
.esp_irq = 18,
},
/* SS-10 */
{
- .iommu_base = 0xe0000000, // XXX Actually at 0xfe0000000ULL (36 bits)
- .tcx_base = 0x20000000, // 0xe20000000ULL,
+ .iommu_base = 0xfe0000000ULL,
+ .tcx_base = 0xe20000000ULL,
.cs_base = -1,
- .slavio_base = 0xf1000000, // 0xff1000000ULL,
- .ms_kb_base = 0xf1000000, // 0xff1000000ULL,
- .serial_base = 0xf1100000, // 0xff1100000ULL,
- .nvram_base = 0xf1200000, // 0xff1200000ULL,
- .fd_base = 0xf1700000, // 0xff1700000ULL,
- .counter_base = 0xf1300000, // 0xff1300000ULL,
- .intctl_base = 0xf1400000, // 0xff1400000ULL,
- .dma_base = 0xf0400000, // 0xef0400000ULL,
- .esp_base = 0xf0800000, // 0xef0800000ULL,
- .le_base = 0xf0c00000, // 0xef0c00000ULL,
+ .slavio_base = 0xff0000000ULL,
+ .ms_kb_base = 0xff1000000ULL,
+ .serial_base = 0xff1100000ULL,
+ .nvram_base = 0xff1200000ULL,
+ .fd_base = 0xff1700000ULL,
+ .counter_base = 0xff1300000ULL,
+ .intctl_base = 0xff1400000ULL,
+ .dma_base = 0xef0400000ULL,
+ .esp_base = 0xef0800000ULL,
+ .le_base = 0xef0c00000ULL,
+ .power_base = 0xefa000000ULL,
.vram_size = 0x00100000,
.nvram_size = 0x2000,
.esp_irq = 18,
static void sun4m_common_init(int ram_size, int boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
- unsigned int machine)
+ unsigned int machine, int max_ram)
{
+ if ((unsigned int)ram_size > (unsigned int)max_ram) {
+ fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
+ (unsigned int)ram_size / (1024 * 1024),
+ (unsigned int)max_ram / (1024 * 1024));
+ exit(1);
+ }
sun4m_hw_init(&hwdefs[machine], ram_size, ds, cpu_model);
sun4m_load_kernel(hwdefs[machine].vram_size, ram_size, boot_device,
cpu_model = "Fujitsu MB86904";
sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model,
- 0);
+ 0, 0x10000000);
}
/* SPARCstation 10 hardware initialisation */
cpu_model = "TI SuperSparc II";
sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model,
- 1);
+ 1, PROM_ADDR); // XXX prom overlap, actually first 4GB ok
}
QEMUMachine ss5_machine = {
projects / qemu / blobdiff