TCX 24 bit model support

[qemu] / hw / sun4m.c

diff --git a/hw/sun4m.c b/hw/sun4m.c
index b41dd25..c24e52a 100644 (file)
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -234,8 +234,12 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
     dma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
                            slavio_irq[hwdef->le_irq], iommu);
 
+    if (graphic_depth != 8 && graphic_depth != 24) {
+        fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
+        exit (1);
+    }
     tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size,
-             hwdef->vram_size, graphic_width, graphic_height);
+             hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
     if (nd_table[0].vlan) {
         if (nd_table[0].model == NULL
             || strcmp(nd_table[0].model, "lance") == 0) {
@@ -376,7 +380,7 @@ static const struct hwdef hwdefs[] = {
     /* SS-10 */
     {
         .iommu_base   = 0xe0000000, // XXX Actually at 0xfe0000000ULL (36 bits)
-        .tcx_base     = 0x21000000, // 0xe21000000ULL,
+        .tcx_base     = 0x20000000, // 0xe20000000ULL,
         .cs_base      = -1,
         .slavio_base  = 0xf1000000, // 0xff1000000ULL,
         .ms_kb_base   = 0xf1000000, // 0xff1000000ULL,