/*
* QEMU Sun4m System Emulator
*
- * Copyright (c) 2003-2004 Fabrice Bellard
+ * Copyright (c) 2003-2005 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* THE SOFTWARE.
*/
#include "vl.h"
-#include "m48t08.h"
#define KERNEL_LOAD_ADDR 0x00004000
#define CMDLINE_ADDR 0x007ff000
// bits
#define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */
#define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */
+#define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */
#define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */
#define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */
#define PHYS_JJ_ESP_IRQ 18
#define PHYS_JJ_SER_IRQ 15
#define PHYS_JJ_FDC 0x71400000 /* Floppy */
#define PHYS_JJ_FLOPPY_IRQ 22
+#define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */
/* TSC handling */
{
}
-static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value)
+static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
{
- m48t08_write(nvram, addr++, (value >> 8) & 0xff);
- m48t08_write(nvram, addr++, value & 0xff);
+ m48t59_write(nvram, addr++, (value >> 8) & 0xff);
+ m48t59_write(nvram, addr++, value & 0xff);
}
-static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value)
+static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
{
- m48t08_write(nvram, addr++, value >> 24);
- m48t08_write(nvram, addr++, (value >> 16) & 0xff);
- m48t08_write(nvram, addr++, (value >> 8) & 0xff);
- m48t08_write(nvram, addr++, value & 0xff);
+ m48t59_write(nvram, addr++, value >> 24);
+ m48t59_write(nvram, addr++, (value >> 16) & 0xff);
+ m48t59_write(nvram, addr++, (value >> 8) & 0xff);
+ m48t59_write(nvram, addr++, value & 0xff);
}
-static void nvram_set_string (m48t08_t *nvram, uint32_t addr,
+static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
const unsigned char *str, uint32_t max)
{
unsigned int i;
for (i = 0; i < max && str[i] != '\0'; i++) {
- m48t08_write(nvram, addr + i, str[i]);
+ m48t59_write(nvram, addr + i, str[i]);
}
- m48t08_write(nvram, addr + max - 1, '\0');
+ m48t59_write(nvram, addr + max - 1, '\0');
}
-static m48t08_t *nvram;
+static m48t59_t *nvram;
extern int nographic;
-static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline,
+static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
int boot_device, uint32_t RAM_size,
uint32_t kernel_size,
int width, int height, int depth)
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
// NVRAM_size, arch not applicable
- m48t08_write(nvram, 0x2F, nographic & 0xff);
+ m48t59_write(nvram, 0x2F, nographic & 0xff);
nvram_set_lword(nvram, 0x30, RAM_size);
- m48t08_write(nvram, 0x34, boot_device & 0xff);
+ m48t59_write(nvram, 0x34, boot_device & 0xff);
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
nvram_set_lword(nvram, 0x3C, kernel_size);
if (cmdline) {
// Sun4m specific use
i = 0x1fd8;
- m48t08_write(nvram, i++, 0x01);
- m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */
+ m48t59_write(nvram, i++, 0x01);
+ m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */
j = 0;
- m48t08_write(nvram, i++, macaddr[j++]);
- m48t08_write(nvram, i++, macaddr[j++]);
- m48t08_write(nvram, i++, macaddr[j++]);
- m48t08_write(nvram, i++, macaddr[j++]);
- m48t08_write(nvram, i++, macaddr[j++]);
- m48t08_write(nvram, i, macaddr[j]);
+ m48t59_write(nvram, i++, macaddr[j++]);
+ m48t59_write(nvram, i++, macaddr[j++]);
+ m48t59_write(nvram, i++, macaddr[j++]);
+ m48t59_write(nvram, i++, macaddr[j++]);
+ m48t59_write(nvram, i++, macaddr[j++]);
+ m48t59_write(nvram, i, macaddr[j]);
/* Calculate checksum */
for (i = 0x1fd8; i < 0x1fe7; i++) {
- tmp ^= m48t08_read(nvram, i);
+ tmp ^= m48t59_read(nvram, i);
}
- m48t08_write(nvram, 0x1fe7, tmp);
+ m48t59_write(nvram, 0x1fe7, tmp);
}
static void *slavio_intctl;
return iommu_translate_local(iommu, addr);
}
+static void *slavio_misc;
+
+void qemu_system_powerdown(void)
+{
+ slavio_set_power_fail(slavio_misc, 1);
+}
+
/* Sun4m hardware initialisation */
-void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename)
+static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
+ DisplayState *ds, const char **fd_filename, int snapshot,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename)
{
char buf[1024];
int ret, linux_boot;
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
- nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);
+ nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
- slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]);
+ // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
+ // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
+ slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);
fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA);
+ slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);
prom_offset = ram_size + vram_size;
}
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
}
+
+QEMUMachine sun4m_machine = {
+ "sun4m",
+ "Sun4m platform",
+ sun4m_init,
+};
projects / qemu / blobdiff