/*
* SH7750 device
- *
+ *
+ * Copyright (c) 2007 Magnus Damm
* Copyright (c) 2005 Samuel Tardieu
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
#include "vl.h"
#include "sh7750_regs.h"
#include "sh7750_regnames.h"
-
-typedef struct {
- uint8_t data[16];
- uint8_t length; /* Number of characters in the FIFO */
- uint8_t write_idx; /* Index of first character to write */
- uint8_t read_idx; /* Index of first character to read */
-} fifo;
+#include "sh_intc.h"
#define NB_DEVICES 4
uint32_t periph_freq;
/* SDRAM controller */
uint16_t rfcr;
- /* First serial port */
- CharDriverState *serial1;
- uint8_t scscr1;
- uint8_t scsmr1;
- uint8_t scbrr1;
- uint8_t scssr1;
- uint8_t scssr1_read;
- uint8_t sctsr1;
- uint8_t sctsr1_loaded;
- uint8_t sctdr1;
- uint8_t scrdr1;
- /* Second serial port */
- CharDriverState *serial2;
- uint16_t sclsr2;
- uint16_t scscr2;
- uint16_t scfcr2;
- uint16_t scfsr2;
- uint16_t scsmr2;
- uint8_t scbrr2;
- fifo serial2_receive_fifo;
- fifo serial2_transmit_fifo;
- /* Timers */
- uint8_t tstr;
- /* Timer 0 */
- QEMUTimer *timer0;
- uint16_t tcr0;
- uint32_t tcor0;
- uint32_t tcnt0;
/* IO ports */
uint16_t gpioic;
uint32_t pctra;
uint16_t periph_pdtrb; /* Imposed by the peripherals */
uint16_t periph_portdirb; /* Direction seen from the peripherals */
sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
+
+ uint16_t icr;
/* Cache */
uint32_t ccr;
-} SH7750State;
-
-/**********************************************************************
- Timers
-**********************************************************************/
-
-/* XXXXX At this time, timer0 works in underflow only mode, that is
- the value of tcnt0 is read at alarm computation time and cannot
- be read back by the guest OS */
-
-static void start_timer0(SH7750State * s)
-{
- uint64_t now, next, prescaler;
-
- if ((s->tcr0 & 6) == 6) {
- fprintf(stderr, "rtc clock for timer 0 not supported\n");
- assert(0);
- }
-
- if ((s->tcr0 & 7) == 5) {
- fprintf(stderr, "timer 0 configuration not supported\n");
- assert(0);
- }
-
- if ((s->tcr0 & 4) == 4)
- prescaler = 1024;
- else
- prescaler = 4 << (s->tcr0 & 3);
-
- now = qemu_get_clock(vm_clock);
- /* XXXXX */
- next =
- now + muldiv64(prescaler * s->tcnt0, ticks_per_sec,
- s->periph_freq);
- if (next == now)
- next = now + 1;
- fprintf(stderr, "now=%016" PRIx64 ", next=%016" PRIx64 "\n", now, next);
- fprintf(stderr, "timer will underflow in %f seconds\n",
- (float) (next - now) / (float) ticks_per_sec);
-
- qemu_mod_timer(s->timer0, next);
-}
-
-static void timer_start_changed(SH7750State * s)
-{
- if (s->tstr & SH7750_TSTR_STR0) {
- start_timer0(s);
- } else {
- fprintf(stderr, "timer 0 is stopped\n");
- qemu_del_timer(s->timer0);
- }
-}
-
-static void timer0_cb(void *opaque)
-{
- SH7750State *s = opaque;
-
- s->tcnt0 = (uint32_t) 0; /* XXXXX */
- if (--s->tcnt0 == (uint32_t) - 1) {
- fprintf(stderr, "timer 0 underflow\n");
- s->tcnt0 = s->tcor0;
- s->tcr0 |= SH7750_TCR_UNF;
- if (s->tcr0 & SH7750_TCR_UNIE) {
- fprintf(stderr,
- "interrupt generation for timer 0 not supported\n");
- assert(0);
- }
- }
- start_timer0(s);
-}
-
-static void init_timers(SH7750State * s)
-{
- s->tcor0 = 0xffffffff;
- s->tcnt0 = 0xffffffff;
- s->timer0 = qemu_new_timer(vm_clock, &timer0_cb, s);
-}
-
-/**********************************************************************
- First serial port
-**********************************************************************/
-
-static int serial1_can_receive(void *opaque)
-{
- SH7750State *s = opaque;
-
- return s->scscr1 & SH7750_SCSCR_RE;
-}
-
-static void serial1_receive_char(SH7750State * s, uint8_t c)
-{
- if (s->scssr1 & SH7750_SCSSR1_RDRF) {
- s->scssr1 |= SH7750_SCSSR1_ORER;
- return;
- }
-
- s->scrdr1 = c;
- s->scssr1 |= SH7750_SCSSR1_RDRF;
-}
-
-static void serial1_receive(void *opaque, const uint8_t * buf, int size)
-{
- SH7750State *s = opaque;
- int i;
-
- for (i = 0; i < size; i++) {
- serial1_receive_char(s, buf[i]);
- }
-}
-
-static void serial1_event(void *opaque, int event)
-{
- assert(0);
-}
-
-static void serial1_maybe_send(SH7750State * s)
-{
- uint8_t c;
-
- if (s->scssr1 & SH7750_SCSSR1_TDRE)
- return;
- c = s->sctdr1;
- s->scssr1 |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND;
- if (s->scscr1 & SH7750_SCSCR_TIE) {
- fprintf(stderr, "interrupts for serial port 1 not implemented\n");
- assert(0);
- }
- /* XXXXX Check for errors in write */
- qemu_chr_write(s->serial1, &c, 1);
-}
-
-static void serial1_change_scssr1(SH7750State * s, uint8_t mem_value)
-{
- uint8_t new_flags;
-
- /* If transmit disable, TDRE and TEND stays up */
- if ((s->scscr1 & SH7750_SCSCR_TE) == 0) {
- mem_value |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND;
- }
-
- /* Only clear bits which have been read before and do not set any bit
- in the flags */
- new_flags = s->scssr1 & ~s->scssr1_read; /* Preserve unread flags */
- new_flags &= mem_value | ~s->scssr1_read; /* Clear read flags */
-
- s->scssr1 = (new_flags & 0xf8) | (mem_value & 1);
- s->scssr1_read &= mem_value;
-
- /* If TDRE has been cleared, TEND will also be cleared */
- if ((s->scssr1 & SH7750_SCSSR1_TDRE) == 0) {
- s->scssr1 &= ~SH7750_SCSSR1_TEND;
- }
-
- /* Check for transmission to start */
- serial1_maybe_send(s);
-}
-
-static void serial1_update_parameters(SH7750State * s)
-{
- QEMUSerialSetParams ssp;
-
- if (s->scsmr1 & SH7750_SCSMR_CHR_7)
- ssp.data_bits = 7;
- else
- ssp.data_bits = 8;
- if (s->scsmr1 & SH7750_SCSMR_PE) {
- if (s->scsmr1 & SH7750_SCSMR_PM_ODD)
- ssp.parity = 'O';
- else
- ssp.parity = 'E';
- } else
- ssp.parity = 'N';
- if (s->scsmr1 & SH7750_SCSMR_STOP_2)
- ssp.stop_bits = 2;
- else
- ssp.stop_bits = 1;
- fprintf(stderr, "SCSMR1=%04x SCBRR1=%02x\n", s->scsmr1, s->scbrr1);
- ssp.speed = s->periph_freq /
- (32 * s->scbrr1 * (1 << (2 * (s->scsmr1 & 3)))) - 1;
- fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
- ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed);
- qemu_chr_ioctl(s->serial1, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
-}
-
-static void scscr1_changed(SH7750State * s)
-{
- if (s->scscr1 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
- if (!s->serial1) {
- fprintf(stderr, "serial port 1 not bound to anything\n");
- assert(0);
- }
- serial1_update_parameters(s);
- }
- if ((s->scscr1 & SH7750_SCSCR_RE) == 0) {
- s->scssr1 |= SH7750_SCSSR1_TDRE;
- }
-}
-
-static void init_serial1(SH7750State * s, int serial_nb)
-{
- CharDriverState *chr;
-
- s->scssr1 = 0x84;
- chr = serial_hds[serial_nb];
- if (!chr) {
- fprintf(stderr,
- "no serial port associated to SH7750 first serial port\n");
- return;
- }
-
- s->serial1 = chr;
- qemu_chr_add_read_handler(chr, serial1_can_receive,
- serial1_receive, s);
- qemu_chr_add_event_handler(chr, serial1_event);
-}
-
-/**********************************************************************
- Second serial port
-**********************************************************************/
-
-static int serial2_can_receive(void *opaque)
-{
- SH7750State *s = opaque;
- static uint8_t max_fifo_size[] = { 15, 1, 4, 6, 8, 10, 12, 14 };
-
- return s->serial2_receive_fifo.length <
- max_fifo_size[(s->scfcr2 >> 9) & 7];
-}
-
-static void serial2_adjust_receive_flags(SH7750State * s)
-{
- static uint8_t max_fifo_size[] = { 1, 4, 8, 14 };
-
- /* XXXXX Add interrupt generation */
- if (s->serial2_receive_fifo.length >=
- max_fifo_size[(s->scfcr2 >> 7) & 3]) {
- s->scfsr2 |= SH7750_SCFSR2_RDF;
- s->scfsr2 &= ~SH7750_SCFSR2_DR;
- } else {
- s->scfsr2 &= ~SH7750_SCFSR2_RDF;
- if (s->serial2_receive_fifo.length > 0)
- s->scfsr2 |= SH7750_SCFSR2_DR;
- else
- s->scfsr2 &= ~SH7750_SCFSR2_DR;
- }
-}
-
-static void serial2_append_char(SH7750State * s, uint8_t c)
-{
- if (s->serial2_receive_fifo.length == 16) {
- /* Overflow */
- s->sclsr2 |= SH7750_SCLSR2_ORER;
- return;
- }
-
- s->serial2_receive_fifo.data[s->serial2_receive_fifo.write_idx++] = c;
- s->serial2_receive_fifo.length++;
- serial2_adjust_receive_flags(s);
-}
-
-static void serial2_receive(void *opaque, const uint8_t * buf, int size)
-{
- SH7750State *s = opaque;
- int i;
-
- for (i = 0; i < size; i++)
- serial2_append_char(s, buf[i]);
-}
-
-static void serial2_event(void *opaque, int event)
-{
- /* XXXXX */
- assert(0);
-}
-
-static void serial2_update_parameters(SH7750State * s)
-{
- QEMUSerialSetParams ssp;
-
- if (s->scsmr2 & SH7750_SCSMR_CHR_7)
- ssp.data_bits = 7;
- else
- ssp.data_bits = 8;
- if (s->scsmr2 & SH7750_SCSMR_PE) {
- if (s->scsmr2 & SH7750_SCSMR_PM_ODD)
- ssp.parity = 'O';
- else
- ssp.parity = 'E';
- } else
- ssp.parity = 'N';
- if (s->scsmr2 & SH7750_SCSMR_STOP_2)
- ssp.stop_bits = 2;
- else
- ssp.stop_bits = 1;
- fprintf(stderr, "SCSMR2=%04x SCBRR2=%02x\n", s->scsmr2, s->scbrr2);
- ssp.speed = s->periph_freq /
- (32 * s->scbrr2 * (1 << (2 * (s->scsmr2 & 3)))) - 1;
- fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
- ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed);
- qemu_chr_ioctl(s->serial2, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
-}
-
-static void scscr2_changed(SH7750State * s)
-{
- if (s->scscr2 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
- if (!s->serial2) {
- fprintf(stderr, "serial port 2 not bound to anything\n");
- assert(0);
- }
- serial2_update_parameters(s);
- }
-}
-
-static void init_serial2(SH7750State * s, int serial_nb)
-{
- CharDriverState *chr;
-
- s->scfsr2 = 0x0060;
- chr = serial_hds[serial_nb];
- if (!chr) {
- fprintf(stderr,
- "no serial port associated to SH7750 second serial port\n");
- return;
- }
-
- s->serial2 = chr;
- qemu_chr_add_read_handler(chr, serial2_can_receive,
- serial2_receive, s);
- qemu_chr_add_event_handler(chr, serial2_event);
-}
+ struct intc_desc intc;
+} SH7750State;
-static void init_serial_ports(SH7750State * s)
-{
- init_serial1(s, 0);
- init_serial2(s, 1);
-}
/**********************************************************************
I/O ports
static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
{
- SH7750State *s = opaque;
- uint8_t r;
-
switch (addr) {
- case SH7750_SCSSR1_A7:
- r = s->scssr1;
- s->scssr1_read |= r;
- return s->scssr1;
- case SH7750_SCRDR1_A7:
- s->scssr1 &= ~SH7750_SCSSR1_RDRF;
- return s->scrdr1;
default:
error_access("byte read", addr);
assert(0);
static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
{
SH7750State *s = opaque;
- uint16_t r;
switch (addr) {
+ case SH7750_FRQCR_A7:
+ return 0;
case SH7750_RFCR_A7:
fprintf(stderr,
"Read access to refresh count register, incrementing\n");
return s->rfcr++;
- case SH7750_TCR0_A7:
- return s->tcr0;
- case SH7750_SCLSR2_A7:
- /* Read and clear overflow bit */
- r = s->sclsr2;
- s->sclsr2 = 0;
- return r;
- case SH7750_SCSFR2_A7:
- return s->scfsr2;
case SH7750_PDTRA_A7:
return porta_lines(s);
case SH7750_PDTRB_A7:
return portb_lines(s);
+ case 0x1fd00000:
+ return s->icr;
default:
error_access("word read", addr);
assert(0);
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
- SH7750State *s = opaque;
-
switch (addr) {
/* PRECHARGE ? XXXXX */
case SH7750_PRECHARGE0_A7:
case SH7750_PRECHARGE1_A7:
ignore_access("byte write", addr);
return;
- case SH7750_SCBRR2_A7:
- s->scbrr2 = mem_value;
- return;
- case SH7750_TSTR_A7:
- s->tstr = mem_value;
- timer_start_changed(s);
- return;
- case SH7750_SCSCR1_A7:
- s->scscr1 = mem_value;
- scscr1_changed(s);
- return;
- case SH7750_SCSMR1_A7:
- s->scsmr1 = mem_value;
- return;
- case SH7750_SCBRR1_A7:
- s->scbrr1 = mem_value;
- return;
- case SH7750_SCTDR1_A7:
- s->scssr1 &= ~SH7750_SCSSR1_TEND;
- s->sctdr1 = mem_value;
- return;
- case SH7750_SCSSR1_A7:
- serial1_change_scssr1(s, mem_value);
- return;
default:
error_access("byte write", addr);
assert(0);
switch (addr) {
/* SDRAM controller */
- case SH7750_SCBRR1_A7:
- case SH7750_SCBRR2_A7:
case SH7750_BCR2_A7:
case SH7750_BCR3_A7:
case SH7750_RTCOR_A7:
fprintf(stderr, "Write access to refresh count register\n");
s->rfcr = mem_value;
return;
- case SH7750_SCLSR2_A7:
- s->sclsr2 = mem_value;
- return;
- case SH7750_SCSCR2_A7:
- s->scscr2 = mem_value;
- scscr2_changed(s);
- return;
- case SH7750_SCFCR2_A7:
- s->scfcr2 = mem_value;
- return;
- case SH7750_SCSMR2_A7:
- s->scsmr2 = mem_value;
- return;
- case SH7750_TCR0_A7:
- s->tcr0 = mem_value;
- return;
case SH7750_GPIOIC_A7:
s->gpioic = mem_value;
if (mem_value != 0) {
assert(0);
}
return;
+ case 0x1fd00000:
+ s->icr = mem_value;
+ return;
default:
error_access("word write", addr);
assert(0);
s->portpullupb = portpullup(mem_value);
portb_changed(s, temp);
return;
- case SH7750_TCNT0_A7:
- s->tcnt0 = mem_value & 0xf;
- return;
case SH7750_MMUCR_A7:
s->cpu->mmucr = mem_value;
return;
sh7750_mem_writel
};
+/* sh775x interrupt controller tables for sh_intc.c
+ * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+ */
+
+enum {
+ UNUSED = 0,
+
+ /* interrupt sources */
+ IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
+ HUDI, GPIOI,
+ DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
+ DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
+ DMAC_DMAE,
+ PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
+ PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
+ TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
+ RTC_ATI, RTC_PRI, RTC_CUI,
+ SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
+ SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
+ WDT,
+ REF_RCMI, REF_ROVI,
+
+ /* interrupt groups */
+ DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
+
+ NR_SOURCES,
+};
+
+static struct intc_vect vectors[] = {
+ INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
+ INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
+ INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
+ INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
+ INTC_VECT(RTC_CUI, 0x4c0),
+ INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
+ INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
+ INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
+ INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
+ INTC_VECT(WDT, 0x560),
+ INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
+};
+
+static struct intc_group groups[] = {
+ INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
+ INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
+ INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
+ INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
+ INTC_GROUP(REF, REF_RCMI, REF_ROVI),
+};
+
+static struct intc_prio_reg prio_registers[] = {
+ { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+ { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
+ { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
+ { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
+ { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
+ TMU4, TMU3,
+ PCIC1, PCIC0_PCISERR } },
+};
+
+/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
+
+static struct intc_vect vectors_dma4[] = {
+ INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
+ INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
+ INTC_VECT(DMAC_DMAE, 0x6c0),
+};
+
+static struct intc_group groups_dma4[] = {
+ INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
+ DMAC_DMTE3, DMAC_DMAE),
+};
+
+/* SH7750R and SH7751R both have 8-channel DMA controllers */
+
+static struct intc_vect vectors_dma8[] = {
+ INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
+ INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
+ INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
+ INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
+ INTC_VECT(DMAC_DMAE, 0x6c0),
+};
+
+static struct intc_group groups_dma8[] = {
+ INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
+ DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
+ DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
+};
+
+/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
+
+static struct intc_vect vectors_tmu34[] = {
+ INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
+};
+
+static struct intc_mask_reg mask_registers[] = {
+ { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, TMU4, TMU3,
+ PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
+ PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
+ PCIC1_PCIDMA3, PCIC0_PCISERR } },
+};
+
+/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
+
+static struct intc_vect vectors_irlm[] = {
+ INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
+ INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
+};
+
+/* SH7751 and SH7751R both have PCI */
+
+static struct intc_vect vectors_pci[] = {
+ INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
+ INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
+ INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
+ INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
+};
+
+static struct intc_group groups_pci[] = {
+ INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
+ PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
+};
+
+#define SH_CPU_SH7750 (1 << 0)
+#define SH_CPU_SH7750S (1 << 1)
+#define SH_CPU_SH7750R (1 << 2)
+#define SH_CPU_SH7751 (1 << 3)
+#define SH_CPU_SH7751R (1 << 4)
+#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
+#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
+
SH7750State *sh7750_init(CPUSH4State * cpu)
{
SH7750State *s;
int sh7750_io_memory;
+ int cpu_model = SH_CPU_SH7751R; /* for now */
s = qemu_mallocz(sizeof(SH7750State));
s->cpu = cpu;
sh7750_mem_read,
sh7750_mem_write, s);
cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
- init_timers(s);
- init_serial_ports(s);
+
+ sh_intc_init(&s->intc, NR_SOURCES,
+ _INTC_ARRAY(mask_registers),
+ _INTC_ARRAY(prio_registers));
+
+ sh_intc_register_sources(&s->intc,
+ _INTC_ARRAY(vectors),
+ _INTC_ARRAY(groups));
+
+ sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]);
+ sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
+ s->periph_freq, serial_hds[1]);
+
+ tmu012_init(0x1fd80000,
+ TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
+ s->periph_freq);
+
+
+ if (cpu_model & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
+ sh_intc_register_sources(&s->intc,
+ _INTC_ARRAY(vectors_dma4),
+ _INTC_ARRAY(groups_dma4));
+ }
+
+ if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
+ sh_intc_register_sources(&s->intc,
+ _INTC_ARRAY(vectors_dma8),
+ _INTC_ARRAY(groups_dma8));
+ }
+
+ if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
+ sh_intc_register_sources(&s->intc,
+ _INTC_ARRAY(vectors_tmu34),
+ _INTC_ARRAY(NULL));
+ tmu012_init(0x1e100000, 0, s->periph_freq);
+ }
+
+ if (cpu_model & (SH_CPU_SH7751_ALL)) {
+ sh_intc_register_sources(&s->intc,
+ _INTC_ARRAY(vectors_pci),
+ _INTC_ARRAY(groups_pci));
+ }
+
+ if (cpu_model & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
+ sh_intc_register_sources(&s->intc,
+ _INTC_ARRAY(vectors_irlm),
+ _INTC_ARRAY(NULL));
+ }
+
return s;
}
projects / qemu / blobdiff