CR8 support

[qemu] / hw / serial.c

diff --git a/hw/serial.c b/hw/serial.c
index e1225ec..3fe482c 100644 (file)
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -21,26 +21,6 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
-#include <stdlib.h>
-#include <stdio.h>
-#include <stdarg.h>
-#include <string.h>
-#include <getopt.h>
-#include <inttypes.h>
-#include <unistd.h>
-#include <sys/mman.h>
-#include <fcntl.h>
-#include <signal.h>
-#include <time.h>
-#include <sys/time.h>
-#include <malloc.h>
-#include <termios.h>
-#include <sys/poll.h>
-#include <errno.h>
-#include <sys/wait.h>
-#include <netinet/in.h>
-
-#include "cpu.h"
 #include "vl.h"
 
 //#define DEBUG_SERIAL
@@ -90,7 +70,7 @@
 #define UART_LSR_OE    0x02    /* Overrun error indicator */
 #define UART_LSR_DR    0x01    /* Receiver data ready */
 
-typedef struct SerialState {
+struct SerialState {
     uint8_t divider;
     uint8_t rbr; /* receive register */
     uint8_t ier;
@@ -104,14 +84,11 @@ typedef struct SerialState {
        it can be reset while reading iir */
     int thr_ipending;
     int irq;
-} SerialState;
-
-SerialState serial_ports[1];
+    CharDriverState *chr;
+};
 
-void serial_update_irq(void)
+static void serial_update_irq(SerialState *s)
 {
-    SerialState *s = &serial_ports[0];
-
     if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
         s->iir = UART_IIR_RDI;
     } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
@@ -126,11 +103,10 @@ void serial_update_irq(void)
     }
 }
 
-void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
+static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 {
-    SerialState *s = &serial_ports[0];
+    SerialState *s = opaque;
     unsigned char ch;
-    int ret;
     
     addr &= 7;
 #ifdef DEBUG_SERIAL
@@ -144,24 +120,24 @@ void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
         } else {
             s->thr_ipending = 0;
             s->lsr &= ~UART_LSR_THRE;
-            serial_update_irq();
-
+            serial_update_irq(s);
             ch = val;
-            do {
-                ret = write(1, &ch, 1);
-            } while (ret != 1);
+            qemu_chr_write(s->chr, &ch, 1);
             s->thr_ipending = 1;
             s->lsr |= UART_LSR_THRE;
             s->lsr |= UART_LSR_TEMT;
-            serial_update_irq();
+            serial_update_irq(s);
         }
         break;
     case 1:
         if (s->lcr & UART_LCR_DLAB) {
             s->divider = (s->divider & 0x00ff) | (val << 8);
         } else {
-            s->ier = val;
-            serial_update_irq();
+            s->ier = val & 0x0f;
+            if (s->lsr & UART_LSR_THRE) {
+                s->thr_ipending = 1;
+            }
+            serial_update_irq(s);
         }
         break;
     case 2:
@@ -170,7 +146,7 @@ void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
         s->lcr = val;
         break;
     case 4:
-        s->mcr = val;
+        s->mcr = val & 0x1f;
         break;
     case 5:
         break;
@@ -183,9 +159,9 @@ void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
     }
 }
 
-uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
+static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 {
-    SerialState *s = &serial_ports[0];
+    SerialState *s = opaque;
     uint32_t ret;
 
     addr &= 7;
@@ -197,7 +173,7 @@ uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
         } else {
             ret = s->rbr;
             s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
-            serial_update_irq();
+            serial_update_irq(s);
         }
         break;
     case 1:
@@ -212,7 +188,7 @@ uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
         /* reset THR pending bit */
         if ((ret & 0x7) == UART_IIR_THRI)
             s->thr_ipending = 0;
-        serial_update_irq();
+        serial_update_irq(s);
         break;
     case 3:
         ret = s->lcr;
@@ -244,38 +220,60 @@ uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
     return ret;
 }
 
-int serial_can_receive(void)
+static int serial_can_receive(SerialState *s)
 {
-    SerialState *s = &serial_ports[0];
     return !(s->lsr & UART_LSR_DR);
 }
 
-void serial_receive_byte(int ch)
+static void serial_receive_byte(SerialState *s, int ch)
 {
-    SerialState *s = &serial_ports[0];
-
     s->rbr = ch;
     s->lsr |= UART_LSR_DR;
-    serial_update_irq();
+    serial_update_irq(s);
 }
 
-void serial_receive_break(void)
+static void serial_receive_break(SerialState *s)
 {
-    SerialState *s = &serial_ports[0];
-
     s->rbr = 0;
     s->lsr |= UART_LSR_BI | UART_LSR_DR;
-    serial_update_irq();
+    serial_update_irq(s);
 }
 
-void serial_init(int base, int irq)
+static int serial_can_receive1(void *opaque)
 {
-    SerialState *s = &serial_ports[0];
+    SerialState *s = opaque;
+    return serial_can_receive(s);
+}
 
+static void serial_receive1(void *opaque, const uint8_t *buf, int size)
+{
+    SerialState *s = opaque;
+    serial_receive_byte(s, buf[0]);
+}
+
+static void serial_event(void *opaque, int event)
+{
+    SerialState *s = opaque;
+    if (event == CHR_EVENT_BREAK)
+        serial_receive_break(s);
+}
+
+/* If fd is zero, it means that the serial device uses the console */
+SerialState *serial_init(int base, int irq, CharDriverState *chr)
+{
+    SerialState *s;
+
+    s = qemu_mallocz(sizeof(SerialState));
+    if (!s)
+        return NULL;
     s->irq = irq;
     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
     s->iir = UART_IIR_NO_INT;
-    
-    register_ioport_write(base, 8, serial_ioport_write, 1);
-    register_ioport_read(base, 8, serial_ioport_read, 1);
+
+    register_ioport_write(base, 8, 1, serial_ioport_write, s);
+    register_ioport_read(base, 8, 1, serial_ioport_read, s);
+    s->chr = chr;
+    qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
+    qemu_chr_add_event_handler(chr, serial_event);
+    return s;
 }