case 1:
/* Idle */
- if (!(s->cm_regs[CCCR] & (1 << 31))) { /* CPDIS */
+ if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
break;
}
pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
i2s->status &= 0xe0;
+ if (i2s->fifo_len < 16 || !i2s->enable)
+ i2s->status |= 1 << 0; /* TNF */
if (i2s->rx_len)
i2s->status |= 1 << 1; /* RNE */
if (i2s->enable)
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
s->cm_base = 0x41300000;
- s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
+ s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
pxa2xx_cm_writefn, s);
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
/* GPIO1 resets the processor */
- /* The handler can be overriden by board-specific code */
+ /* The handler can be overridden by board-specific code */
pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
return s;
}
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
s->cm_base = 0x41300000;
- s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
+ s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
pxa2xx_cm_writefn, s);
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
/* GPIO1 resets the processor */
- /* The handler can be overriden by board-specific code */
+ /* The handler can be overridden by board-specific code */
pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
return s;
}