Add PowerPC power-management state check callback.

[qemu] / hw / pxa2xx.c

diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 087acd0..6109fc1 100644 (file)
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -69,16 +69,9 @@ static struct {
 #define PCMD0  0x80    /* Power Manager I2C Command register File 0 */
 #define PCMD31 0xfc    /* Power Manager I2C Command register File 31 */
 
-static uint32_t pxa2xx_i2c_read(void *, target_phys_addr_t);
-static void pxa2xx_i2c_write(void *, target_phys_addr_t, uint32_t);
-
 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
 {
     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
-    if (addr > s->pm_base + PCMD31) {
-        /* Special case: PWRI2C registers appear in the same range.  */
-        return pxa2xx_i2c_read(s->i2c[1], addr);
-    }
     addr -= s->pm_base;
 
     switch (addr) {
@@ -99,11 +92,6 @@ static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
                 uint32_t value)
 {
     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
-    if (addr > s->pm_base + PCMD31) {
-        /* Special case: PWRI2C registers appear in the same range.  */
-        pxa2xx_i2c_write(s->i2c[1], addr, value);
-        return;
-    }
     addr -= s->pm_base;
 
     switch (addr) {
@@ -292,7 +280,7 @@ static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
 
         case 1:
             /* Idle */
-            if (!(s->cm_regs[CCCR] & (1 << 31))) {     /* CPDIS */
+            if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) {        /* CPDIS */
                 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
                 break;
             }
@@ -1484,7 +1472,7 @@ static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
 }
 
 struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
-                qemu_irq irq, int ioregister)
+                qemu_irq irq, uint32_t page_size)
 {
     int iomemtype;
     struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
@@ -1497,11 +1485,9 @@ struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
     s->slave.send = pxa2xx_i2c_tx;
     s->bus = i2c_init_bus();
 
-    if (ioregister) {
-        iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
-                        pxa2xx_i2c_writefn, s);
-        cpu_register_physical_memory(s->base & 0xfffff000, 0xfff, iomemtype);
-    }
+    iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
+                    pxa2xx_i2c_writefn, s);
+    cpu_register_physical_memory(s->base & ~page_size, page_size, iomemtype);
 
     register_savevm("pxa2xx_i2c", base, 0,
                     pxa2xx_i2c_save, pxa2xx_i2c_load, s);
@@ -1544,6 +1530,8 @@ static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
     pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
 
     i2s->status &= 0xe0;
+    if (i2s->fifo_len < 16 || !i2s->enable)
+        i2s->status |= 1 << 0;                 /* TNF */
     if (i2s->rx_len)
         i2s->status |= 1 << 1;                 /* RNE */
     if (i2s->enable)
@@ -1739,7 +1727,7 @@ static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
 
     iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
                     pxa2xx_i2s_writefn, s);
-    cpu_register_physical_memory(s->base & 0xfff00000, 0xfffff, iomemtype);
+    cpu_register_physical_memory(s->base & 0xfff00000, 0x100000, iomemtype);
 
     register_savevm("pxa2xx_i2s", base, 0,
                     pxa2xx_i2s_save, pxa2xx_i2s_load, s);
@@ -2002,7 +1990,7 @@ static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
 
     iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
                     pxa2xx_fir_writefn, s);
-    cpu_register_physical_memory(s->base, 0xfff, iomemtype);
+    cpu_register_physical_memory(s->base, 0x1000, iomemtype);
 
     if (chr)
         qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
@@ -2071,11 +2059,11 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
         s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
 
     s->cm_base = 0x41300000;
-    s->cm_regs[CCCR >> 4] = 0x02000210;        /* 416.0 MHz */
+    s->cm_regs[CCCR >> 2] = 0x02000210;        /* 416.0 MHz */
     s->clkcfg = 0x00000009;            /* Turbo mode active */
     iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
                     pxa2xx_cm_writefn, s);
-    cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
+    cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
     register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
 
     cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
@@ -2086,9 +2074,15 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
     s->mm_regs[MECR >> 2] = 0x00000001;        /* Two PC Card sockets */
     iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
                     pxa2xx_mm_writefn, s);
-    cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
+    cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
     register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
 
+    s->pm_base = 0x40f00000;
+    iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
+                    pxa2xx_pm_writefn, s);
+    cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
+    register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
+
     for (i = 0; pxa27x_ssp[i].io_base; i ++);
     s->ssp = (struct pxa2xx_ssp_s **)
             qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
@@ -2101,7 +2095,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
 
         iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
                         pxa2xx_ssp_writefn, &ssp[i]);
-        cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
+        cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
         register_savevm("pxa2xx_ssp", i, 0,
                         pxa2xx_ssp_save, pxa2xx_ssp_load, s);
     }
@@ -2116,26 +2110,17 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
     s->rtc_base = 0x40900000;
     iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
                     pxa2xx_rtc_writefn, s);
-    cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
+    cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
     pxa2xx_rtc_init(s);
     register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
 
-    /* Note that PM registers are in the same page with PWRI2C registers.
-     * As a workaround we don't map PWRI2C into memory and we expect
-     * PM handlers to call PWRI2C handlers when appropriate.  */
-    s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1);
-    s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0);
-
-    s->pm_base = 0x40f00000;
-    iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
-                    pxa2xx_pm_writefn, s);
-    cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
-    register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
+    s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
+    s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
 
     s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
 
     /* GPIO1 resets the processor */
-    /* The handler can be overriden by board-specific code */
+    /* The handler can be overridden by board-specific code */
     pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
     return s;
 }
@@ -2183,11 +2168,11 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
         s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
 
     s->cm_base = 0x41300000;
-    s->cm_regs[CCCR >> 4] = 0x02000210;        /* 416.0 MHz */
+    s->cm_regs[CCCR >> 2] = 0x02000210;        /* 416.0 MHz */
     s->clkcfg = 0x00000009;            /* Turbo mode active */
     iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
                     pxa2xx_cm_writefn, s);
-    cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
+    cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
     register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
 
     cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
@@ -2198,9 +2183,15 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
     s->mm_regs[MECR >> 2] = 0x00000001;        /* Two PC Card sockets */
     iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
                     pxa2xx_mm_writefn, s);
-    cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
+    cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
     register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
 
+    s->pm_base = 0x40f00000;
+    iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
+                    pxa2xx_pm_writefn, s);
+    cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
+    register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
+
     for (i = 0; pxa255_ssp[i].io_base; i ++);
     s->ssp = (struct pxa2xx_ssp_s **)
             qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
@@ -2213,7 +2204,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
 
         iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
                         pxa2xx_ssp_writefn, &ssp[i]);
-        cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
+        cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
         register_savevm("pxa2xx_ssp", i, 0,
                         pxa2xx_ssp_save, pxa2xx_ssp_load, s);
     }
@@ -2228,26 +2219,17 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
     s->rtc_base = 0x40900000;
     iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
                     pxa2xx_rtc_writefn, s);
-    cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
+    cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
     pxa2xx_rtc_init(s);
     register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
 
-    /* Note that PM registers are in the same page with PWRI2C registers.
-     * As a workaround we don't map PWRI2C into memory and we expect
-     * PM handlers to call PWRI2C handlers when appropriate.  */
-    s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1);
-    s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0);
-
-    s->pm_base = 0x40f00000;
-    iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
-                    pxa2xx_pm_writefn, s);
-    cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
-    register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
+    s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
+    s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
 
     s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
 
     /* GPIO1 resets the processor */
-    /* The handler can be overriden by board-specific code */
+    /* The handler can be overridden by board-specific code */
     pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
     return s;
 }