#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
-static uint32_t pxa2xx_i2c_read(void *, target_phys_addr_t);
-static void pxa2xx_i2c_write(void *, target_phys_addr_t, uint32_t);
-
static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- if (addr > s->pm_base + PCMD31) {
- /* Special case: PWRI2C registers appear in the same range. */
- return pxa2xx_i2c_read(s->i2c[1], addr);
- }
addr -= s->pm_base;
switch (addr) {
uint32_t value)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- if (addr > s->pm_base + PCMD31) {
- /* Special case: PWRI2C registers appear in the same range. */
- pxa2xx_i2c_write(s->i2c[1], addr, value);
- return;
- }
addr -= s->pm_base;
switch (addr) {
pxa2xx_pm_write,
};
+static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
+{
+ struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ int i;
+
+ for (i = 0; i < 0x40; i ++)
+ qemu_put_be32s(f, &s->pm_regs[i]);
+}
+
+static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
+{
+ struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ int i;
+
+ for (i = 0; i < 0x40; i ++)
+ qemu_get_be32s(f, &s->pm_regs[i]);
+
+ return 0;
+}
+
#define CCCR 0x00 /* Core Clock Configuration register */
#define CKEN 0x04 /* Clock Enable register */
#define OSCC 0x08 /* Oscillator Configuration register */
pxa2xx_cm_write,
};
+static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
+{
+ struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ int i;
+
+ for (i = 0; i < 4; i ++)
+ qemu_put_be32s(f, &s->cm_regs[i]);
+ qemu_put_be32s(f, &s->clkcfg);
+ qemu_put_be32s(f, &s->pmnc);
+}
+
+static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
+{
+ struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ int i;
+
+ for (i = 0; i < 4; i ++)
+ qemu_get_be32s(f, &s->cm_regs[i]);
+ qemu_get_be32s(f, &s->clkcfg);
+ qemu_get_be32s(f, &s->pmnc);
+
+ return 0;
+}
+
static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
case 1:
/* Idle */
- if (!(s->cm_regs[CCCR] & (1 << 31))) { /* CPDIS */
+ if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
break;
}
pxa2xx_mm_write,
};
+static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
+{
+ struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ int i;
+
+ for (i = 0; i < 0x1a; i ++)
+ qemu_put_be32s(f, &s->mm_regs[i]);
+}
+
+static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
+{
+ struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ int i;
+
+ for (i = 0; i < 0x1a; i ++)
+ qemu_get_be32s(f, &s->mm_regs[i]);
+
+ return 0;
+}
+
/* Synchronous Serial Ports */
struct pxa2xx_ssp_s {
target_phys_addr_t base;
pxa2xx_ssp_write,
};
+static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
+{
+ struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
+ int i;
+
+ qemu_put_be32(f, s->enable);
+
+ qemu_put_be32s(f, &s->sscr[0]);
+ qemu_put_be32s(f, &s->sscr[1]);
+ qemu_put_be32s(f, &s->sspsp);
+ qemu_put_be32s(f, &s->ssto);
+ qemu_put_be32s(f, &s->ssitr);
+ qemu_put_be32s(f, &s->sssr);
+ qemu_put_8s(f, &s->sstsa);
+ qemu_put_8s(f, &s->ssrsa);
+ qemu_put_8s(f, &s->ssacd);
+
+ qemu_put_byte(f, s->rx_level);
+ for (i = 0; i < s->rx_level; i ++)
+ qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
+}
+
+static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
+{
+ struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
+ int i;
+
+ s->enable = qemu_get_be32(f);
+
+ qemu_get_be32s(f, &s->sscr[0]);
+ qemu_get_be32s(f, &s->sscr[1]);
+ qemu_get_be32s(f, &s->sspsp);
+ qemu_get_be32s(f, &s->ssto);
+ qemu_get_be32s(f, &s->ssitr);
+ qemu_get_be32s(f, &s->sssr);
+ qemu_get_8s(f, &s->sstsa);
+ qemu_get_8s(f, &s->ssrsa);
+ qemu_get_8s(f, &s->ssacd);
+
+ s->rx_level = qemu_get_byte(f);
+ s->rx_start = 0;
+ for (i = 0; i < s->rx_level; i ++)
+ s->rx_fifo[i] = qemu_get_byte(f);
+
+ return 0;
+}
+
/* Real-Time Clock */
#define RCNR 0x00 /* RTC Counter register */
#define RTAR 0x04 /* RTC Alarm register */
}
}
-static void pxa2xx_rtc_reset(struct pxa2xx_state_s *s)
+static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
+ pxa2xx_rtc_read,
+ pxa2xx_rtc_read,
+ pxa2xx_rtc_read,
+};
+
+static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
+ pxa2xx_rtc_write,
+ pxa2xx_rtc_write,
+ pxa2xx_rtc_write,
+};
+
+static void pxa2xx_rtc_init(struct pxa2xx_state_s *s)
{
struct tm *tm;
time_t ti;
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
}
-static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
- pxa2xx_rtc_read,
- pxa2xx_rtc_read,
- pxa2xx_rtc_read,
-};
+static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
+{
+ struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
-static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
- pxa2xx_rtc_write,
- pxa2xx_rtc_write,
- pxa2xx_rtc_write,
-};
+ pxa2xx_rtc_hzupdate(s);
+ pxa2xx_rtc_piupdate(s);
+ pxa2xx_rtc_swupdate(s);
+
+ qemu_put_be32s(f, &s->rttr);
+ qemu_put_be32s(f, &s->rtsr);
+ qemu_put_be32s(f, &s->rtar);
+ qemu_put_be32s(f, &s->rdar1);
+ qemu_put_be32s(f, &s->rdar2);
+ qemu_put_be32s(f, &s->ryar1);
+ qemu_put_be32s(f, &s->ryar2);
+ qemu_put_be32s(f, &s->swar1);
+ qemu_put_be32s(f, &s->swar2);
+ qemu_put_be32s(f, &s->piar);
+ qemu_put_be32s(f, &s->last_rcnr);
+ qemu_put_be32s(f, &s->last_rdcr);
+ qemu_put_be32s(f, &s->last_rycr);
+ qemu_put_be32s(f, &s->last_swcr);
+ qemu_put_be32s(f, &s->last_rtcpicr);
+ qemu_put_be64s(f, &s->last_hz);
+ qemu_put_be64s(f, &s->last_sw);
+ qemu_put_be64s(f, &s->last_pi);
+}
+
+static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
+{
+ struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+
+ qemu_get_be32s(f, &s->rttr);
+ qemu_get_be32s(f, &s->rtsr);
+ qemu_get_be32s(f, &s->rtar);
+ qemu_get_be32s(f, &s->rdar1);
+ qemu_get_be32s(f, &s->rdar2);
+ qemu_get_be32s(f, &s->ryar1);
+ qemu_get_be32s(f, &s->ryar2);
+ qemu_get_be32s(f, &s->swar1);
+ qemu_get_be32s(f, &s->swar2);
+ qemu_get_be32s(f, &s->piar);
+ qemu_get_be32s(f, &s->last_rcnr);
+ qemu_get_be32s(f, &s->last_rdcr);
+ qemu_get_be32s(f, &s->last_rycr);
+ qemu_get_be32s(f, &s->last_swcr);
+ qemu_get_be32s(f, &s->last_rtcpicr);
+ qemu_get_be64s(f, &s->last_hz);
+ qemu_get_be64s(f, &s->last_sw);
+ qemu_get_be64s(f, &s->last_pi);
+
+ pxa2xx_rtc_alarm_update(s, s->rtsr);
+
+ return 0;
+}
/* I2C Interface */
struct pxa2xx_i2c_s {
pxa2xx_i2c_write,
};
+static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
+{
+ struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
+
+ qemu_put_be16s(f, &s->control);
+ qemu_put_be16s(f, &s->status);
+ qemu_put_8s(f, &s->ibmr);
+ qemu_put_8s(f, &s->data);
+
+ i2c_bus_save(f, s->bus);
+ i2c_slave_save(f, &s->slave);
+}
+
+static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
+{
+ struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
+
+ qemu_get_be16s(f, &s->control);
+ qemu_get_be16s(f, &s->status);
+ qemu_get_8s(f, &s->ibmr);
+ qemu_get_8s(f, &s->data);
+
+ i2c_bus_load(f, s->bus);
+ i2c_slave_load(f, &s->slave);
+ return 0;
+}
+
struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
- qemu_irq irq, int ioregister)
+ qemu_irq irq, uint32_t page_size)
{
int iomemtype;
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
s->slave.send = pxa2xx_i2c_tx;
s->bus = i2c_init_bus();
- if (ioregister) {
- iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
- pxa2xx_i2c_writefn, s);
- cpu_register_physical_memory(s->base & 0xfffff000, 0xfff, iomemtype);
- }
+ iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
+ pxa2xx_i2c_writefn, s);
+ cpu_register_physical_memory(s->base & ~page_size, page_size, iomemtype);
+
+ register_savevm("pxa2xx_i2c", base, 0,
+ pxa2xx_i2c_save, pxa2xx_i2c_load, s);
return s;
}
pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
i2s->status &= 0xe0;
+ if (i2s->fifo_len < 16 || !i2s->enable)
+ i2s->status |= 1 << 0; /* TNF */
if (i2s->rx_len)
i2s->status |= 1 << 1; /* RNE */
if (i2s->enable)
pxa2xx_i2s_write,
};
+static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
+{
+ struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
+
+ qemu_put_be32s(f, &s->control[0]);
+ qemu_put_be32s(f, &s->control[1]);
+ qemu_put_be32s(f, &s->status);
+ qemu_put_be32s(f, &s->mask);
+ qemu_put_be32s(f, &s->clk);
+
+ qemu_put_be32(f, s->enable);
+ qemu_put_be32(f, s->rx_len);
+ qemu_put_be32(f, s->tx_len);
+ qemu_put_be32(f, s->fifo_len);
+}
+
+static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
+{
+ struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
+
+ qemu_get_be32s(f, &s->control[0]);
+ qemu_get_be32s(f, &s->control[1]);
+ qemu_get_be32s(f, &s->status);
+ qemu_get_be32s(f, &s->mask);
+ qemu_get_be32s(f, &s->clk);
+
+ s->enable = qemu_get_be32(f);
+ s->rx_len = qemu_get_be32(f);
+ s->tx_len = qemu_get_be32(f);
+ s->fifo_len = qemu_get_be32(f);
+
+ return 0;
+}
+
static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
{
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
pxa2xx_i2s_writefn, s);
- cpu_register_physical_memory(s->base & 0xfff00000, 0xfffff, iomemtype);
+ cpu_register_physical_memory(s->base & 0xfff00000, 0x100000, iomemtype);
+
+ register_savevm("pxa2xx_i2s", base, 0,
+ pxa2xx_i2s_save, pxa2xx_i2s_load, s);
return s;
}
{
}
+static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
+{
+ struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
+ int i;
+
+ qemu_put_be32(f, s->enable);
+
+ qemu_put_8s(f, &s->control[0]);
+ qemu_put_8s(f, &s->control[1]);
+ qemu_put_8s(f, &s->control[2]);
+ qemu_put_8s(f, &s->status[0]);
+ qemu_put_8s(f, &s->status[1]);
+
+ qemu_put_byte(f, s->rx_len);
+ for (i = 0; i < s->rx_len; i ++)
+ qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
+}
+
+static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
+{
+ struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
+ int i;
+
+ s->enable = qemu_get_be32(f);
+
+ qemu_get_8s(f, &s->control[0]);
+ qemu_get_8s(f, &s->control[1]);
+ qemu_get_8s(f, &s->control[2]);
+ qemu_get_8s(f, &s->status[0]);
+ qemu_get_8s(f, &s->status[1]);
+
+ s->rx_len = qemu_get_byte(f);
+ s->rx_start = 0;
+ for (i = 0; i < s->rx_len; i ++)
+ s->rx_fifo[i] = qemu_get_byte(f);
+
+ return 0;
+}
+
static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
qemu_irq irq, struct pxa2xx_dma_state_s *dma,
CharDriverState *chr)
iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
pxa2xx_fir_writefn, s);
- cpu_register_physical_memory(s->base, 0xfff, iomemtype);
+ cpu_register_physical_memory(s->base, 0x1000, iomemtype);
if (chr)
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
pxa2xx_fir_rx, pxa2xx_fir_event, s);
+ register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
+
return s;
}
s->env = cpu_init();
cpu_arm_set_model(s->env, revision ?: "pxa270");
+ register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
/* SDRAM & Internal Memory Storage */
cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
s->cm_base = 0x41300000;
- s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
+ s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
pxa2xx_cm_writefn, s);
- cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
+ cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
+ register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
pxa2xx_mm_writefn, s);
- cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
+ cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
+ register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
+
+ s->pm_base = 0x40f00000;
+ iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
+ pxa2xx_pm_writefn, s);
+ cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
+ register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
for (i = 0; pxa27x_ssp[i].io_base; i ++);
s->ssp = (struct pxa2xx_ssp_s **)
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
pxa2xx_ssp_writefn, &ssp[i]);
- cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
+ cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
+ register_savevm("pxa2xx_ssp", i, 0,
+ pxa2xx_ssp_save, pxa2xx_ssp_load, s);
}
if (usb_enabled) {
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
pxa2xx_rtc_writefn, s);
- cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
- pxa2xx_rtc_reset(s);
-
- /* Note that PM registers are in the same page with PWRI2C registers.
- * As a workaround we don't map PWRI2C into memory and we expect
- * PM handlers to call PWRI2C handlers when appropriate. */
- s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1);
- s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0);
+ cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
+ pxa2xx_rtc_init(s);
+ register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
- s->pm_base = 0x40f00000;
- iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
- pxa2xx_pm_writefn, s);
- cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
+ s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
+ s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
/* GPIO1 resets the processor */
- /* The handler can be overriden by board-specific code */
+ /* The handler can be overridden by board-specific code */
pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
return s;
}
s->env = cpu_init();
cpu_arm_set_model(s->env, "pxa255");
+ register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
/* SDRAM & Internal Memory Storage */
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
s->cm_base = 0x41300000;
- s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
+ s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
pxa2xx_cm_writefn, s);
- cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
+ cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
+ register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
pxa2xx_mm_writefn, s);
- cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
+ cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
+ register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
+
+ s->pm_base = 0x40f00000;
+ iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
+ pxa2xx_pm_writefn, s);
+ cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
+ register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
for (i = 0; pxa255_ssp[i].io_base; i ++);
s->ssp = (struct pxa2xx_ssp_s **)
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
pxa2xx_ssp_writefn, &ssp[i]);
- cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
+ cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
+ register_savevm("pxa2xx_ssp", i, 0,
+ pxa2xx_ssp_save, pxa2xx_ssp_load, s);
}
if (usb_enabled) {
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
pxa2xx_rtc_writefn, s);
- cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
- pxa2xx_rtc_reset(s);
+ cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
+ pxa2xx_rtc_init(s);
+ register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
- /* Note that PM registers are in the same page with PWRI2C registers.
- * As a workaround we don't map PWRI2C into memory and we expect
- * PM handlers to call PWRI2C handlers when appropriate. */
- s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1);
- s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0);
-
- s->pm_base = 0x40f00000;
- iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
- pxa2xx_pm_writefn, s);
- cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
+ s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
+ s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
/* GPIO1 resets the processor */
- /* The handler can be overriden by board-specific code */
+ /* The handler can be overridden by board-specific code */
pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
return s;
}
projects / qemu / blobdiff