/*
* QEMU generic PowerPC hardware System Emulator
- *
+ *
* Copyright (c) 2003-2007 Jocelyn Mayer
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
#include "m48t59.h"
//#define PPC_DEBUG_IRQ
+//#define PPC_DEBUG_TB
extern FILE *logfile;
extern int loglevel;
-void ppc_set_irq (CPUState *env, int n_IRQ, int level)
+static void cpu_ppc_tb_stop (CPUState *env);
+static void cpu_ppc_tb_start (CPUState *env);
+
+static void ppc_set_irq (CPUState *env, int n_IRQ, int level)
{
if (level) {
env->pending_interrupts |= 1 << n_IRQ;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
#if defined(PPC_DEBUG_IRQ)
- printf("%s: %p n_IRQ %d level %d => pending %08x req %08x\n", __func__,
- env, n_IRQ, level, env->pending_interrupts, env->interrupt_request);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
+ __func__, env, n_IRQ, level,
+ env->pending_interrupts, env->interrupt_request);
+ }
#endif
}
int cur_level;
#if defined(PPC_DEBUG_IRQ)
- printf("%s: env %p pin %d level %d\n", __func__, env, pin, level);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
+ env, pin, level);
+ }
#endif
cur_level = (env->irq_input_state >> pin) & 1;
/* Don't generate spurious events */
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
switch (pin) {
+ case PPC6xx_INPUT_TBEN:
+ /* Level sensitive - active high */
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: %s the time base\n",
+ __func__, level ? "start" : "stop");
+ }
+#endif
+ if (level) {
+ cpu_ppc_tb_start(env);
+ } else {
+ cpu_ppc_tb_stop(env);
+ }
case PPC6xx_INPUT_INT:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
- printf("%s: set the external IRQ state to %d\n", __func__, level);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: set the external IRQ state to %d\n",
+ __func__, level);
+ }
#endif
ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
break;
case PPC6xx_INPUT_SMI:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
- printf("%s: set the SMI IRQ state to %d\n", __func__, level);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
+ __func__, level);
+ }
#endif
ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
break;
*/
if (cur_level == 1 && level == 0) {
#if defined(PPC_DEBUG_IRQ)
- printf("%s: raise machine check state\n", __func__);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: raise machine check state\n",
+ __func__);
+ }
#endif
ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
}
case PPC6xx_INPUT_CKSTP_IN:
/* Level sensitive - active low */
/* XXX: TODO: relay the signal to CKSTP_OUT pin */
+ /* XXX: Note that the only way to restart the CPU is to reset it */
if (level) {
#if defined(PPC_DEBUG_IRQ)
- printf("%s: stop the CPU\n", __func__);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: stop the CPU\n", __func__);
+ }
#endif
env->halted = 1;
- } else {
-#if defined(PPC_DEBUG_IRQ)
- printf("%s: restart the CPU\n", __func__);
-#endif
- env->halted = 0;
}
break;
case PPC6xx_INPUT_HRESET:
if (level) {
#if 0 // XXX: TOFIX
#if defined(PPC_DEBUG_IRQ)
- printf("%s: reset the CPU\n", __func__);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: reset the CPU\n", __func__);
+ }
#endif
cpu_reset(env);
#endif
break;
case PPC6xx_INPUT_SRESET:
#if defined(PPC_DEBUG_IRQ)
- printf("%s: set the RESET IRQ state to %d\n", __func__, level);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
+ __func__, level);
+ }
#endif
ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
break;
default:
/* Unknown pin - do nothing */
#if defined(PPC_DEBUG_IRQ)
- printf("%s: unknown IRQ pin %d\n", __func__, pin);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
+ }
#endif
return;
}
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
}
-/* PowerPC 405 internal IRQ controller */
-static void ppc405_set_irq (void *opaque, int pin, int level)
+#if defined(TARGET_PPC64)
+/* PowerPC 970 internal IRQ controller */
+static void ppc970_set_irq (void *opaque, int pin, int level)
{
CPUState *env = opaque;
int cur_level;
#if defined(PPC_DEBUG_IRQ)
- printf("%s: env %p pin %d level %d\n", __func__, env, pin, level);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
+ env, pin, level);
+ }
#endif
cur_level = (env->irq_input_state >> pin) & 1;
/* Don't generate spurious events */
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
switch (pin) {
- case PPC405_INPUT_RESET_SYS:
- /* XXX: TODO: reset all peripherals */
- /* No break here */
- case PPC405_INPUT_RESET_CHIP:
- /* XXX: TODO: reset on-chip peripherals */
- /* No break here */
- case PPC405_INPUT_RESET_CORE:
- /* XXX: TODO: update DBSR[MRR] */
+ case PPC970_INPUT_INT:
+ /* Level sensitive - active high */
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: set the external IRQ state to %d\n",
+ __func__, level);
+ }
+#endif
+ ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
+ break;
+ case PPC970_INPUT_THINT:
+ /* Level sensitive - active high */
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
+ level);
+ }
+#endif
+ ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
+ break;
+ case PPC970_INPUT_MCP:
+ /* Negative edge sensitive */
+ /* XXX: TODO: actual reaction may depends on HID0 status
+ * 603/604/740/750: check HID0[EMCP]
+ */
+ if (cur_level == 1 && level == 0) {
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: raise machine check state\n",
+ __func__);
+ }
+#endif
+ ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
+ }
+ break;
+ case PPC970_INPUT_CKSTP:
+ /* Level sensitive - active low */
+ /* XXX: TODO: relay the signal to CKSTP_OUT pin */
+ if (level) {
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: stop the CPU\n", __func__);
+ }
+#endif
+ env->halted = 1;
+ } else {
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: restart the CPU\n", __func__);
+ }
+#endif
+ env->halted = 0;
+ }
+ break;
+ case PPC970_INPUT_HRESET:
+ /* Level sensitive - active low */
if (level) {
#if 0 // XXX: TOFIX
#if defined(PPC_DEBUG_IRQ)
- printf("%s: reset the CPU\n", __func__);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: reset the CPU\n", __func__);
+ }
#endif
cpu_reset(env);
#endif
}
break;
- case PPC405_INPUT_CINT:
- /* Level sensitive - active high */
+ case PPC970_INPUT_SRESET:
#if defined(PPC_DEBUG_IRQ)
- printf("%s: set the critical IRQ state to %d\n", __func__, level);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
+ __func__, level);
+ }
#endif
- /* XXX: TOFIX */
ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
break;
- case PPC405_INPUT_INT:
+ case PPC970_INPUT_TBEN:
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
+ level);
+ }
+#endif
+ /* XXX: TODO */
+ break;
+ default:
+ /* Unknown pin - do nothing */
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
+ }
+#endif
+ return;
+ }
+ if (level)
+ env->irq_input_state |= 1 << pin;
+ else
+ env->irq_input_state &= ~(1 << pin);
+ }
+}
+
+void ppc970_irq_init (CPUState *env)
+{
+ env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
+}
+#endif /* defined(TARGET_PPC64) */
+
+/* PowerPC 40x internal IRQ controller */
+static void ppc40x_set_irq (void *opaque, int pin, int level)
+{
+ CPUState *env = opaque;
+ int cur_level;
+
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
+ env, pin, level);
+ }
+#endif
+ cur_level = (env->irq_input_state >> pin) & 1;
+ /* Don't generate spurious events */
+ if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
+ switch (pin) {
+ case PPC40x_INPUT_RESET_SYS:
+ if (level) {
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: reset the PowerPC system\n",
+ __func__);
+ }
+#endif
+ ppc40x_system_reset(env);
+ }
+ break;
+ case PPC40x_INPUT_RESET_CHIP:
+ if (level) {
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: reset the PowerPC chip\n", __func__);
+ }
+#endif
+ ppc40x_chip_reset(env);
+ }
+ break;
+ case PPC40x_INPUT_RESET_CORE:
+ /* XXX: TODO: update DBSR[MRR] */
+ if (level) {
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: reset the PowerPC core\n", __func__);
+ }
+#endif
+ ppc40x_core_reset(env);
+ }
+ break;
+ case PPC40x_INPUT_CINT:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
- printf("%s: set the external IRQ state to %d\n", __func__, level);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: set the critical IRQ state to %d\n",
+ __func__, level);
+ }
+#endif
+ ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
+ break;
+ case PPC40x_INPUT_INT:
+ /* Level sensitive - active high */
+#if defined(PPC_DEBUG_IRQ)
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: set the external IRQ state to %d\n",
+ __func__, level);
+ }
#endif
ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
break;
- case PPC405_INPUT_HALT:
+ case PPC40x_INPUT_HALT:
/* Level sensitive - active low */
if (level) {
#if defined(PPC_DEBUG_IRQ)
- printf("%s: stop the CPU\n", __func__);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: stop the CPU\n", __func__);
+ }
#endif
env->halted = 1;
} else {
#if defined(PPC_DEBUG_IRQ)
- printf("%s: restart the CPU\n", __func__);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: restart the CPU\n", __func__);
+ }
#endif
env->halted = 0;
}
break;
- case PPC405_INPUT_DEBUG:
+ case PPC40x_INPUT_DEBUG:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
- printf("%s: set the external IRQ state to %d\n", __func__, level);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: set the debug pin state to %d\n",
+ __func__, level);
+ }
#endif
- ppc_set_irq(env, EXCP_40x_DEBUG, level);
+ ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
break;
default:
/* Unknown pin - do nothing */
#if defined(PPC_DEBUG_IRQ)
- printf("%s: unknown IRQ pin %d\n", __func__, pin);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
+ }
#endif
return;
}
}
}
-void ppc405_irq_init (CPUState *env)
+void ppc40x_irq_init (CPUState *env)
{
- printf("%s\n", __func__);
- env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7);
+ env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
+ env, PPC40x_INPUT_NB);
}
/*****************************************************************************/
/* PowerPC time base and decrementer emulation */
-//#define DEBUG_TB
-
struct ppc_tb_t {
/* Time base management */
- int64_t tb_offset; /* Compensation */
- uint32_t tb_freq; /* TB frequency */
+ int64_t tb_offset; /* Compensation */
+ int64_t atb_offset; /* Compensation */
+ uint32_t tb_freq; /* TB frequency */
/* Decrementer management */
- uint64_t decr_next; /* Tick for next decr interrupt */
+ uint64_t decr_next; /* Tick for next decr interrupt */
+ uint32_t decr_freq; /* decrementer frequency */
struct QEMUTimer *decr_timer;
+#if defined(TARGET_PPC64H)
+ /* Hypervisor decrementer management */
+ uint64_t hdecr_next; /* Tick for next hdecr interrupt */
+ struct QEMUTimer *hdecr_timer;
+ uint64_t purr_load;
+ uint64_t purr_start;
+#endif
void *opaque;
};
-static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
+static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, uint64_t vmclk,
+ int64_t tb_offset)
{
/* TB time in tb periods */
- return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
- tb_env->tb_freq, ticks_per_sec);
+ return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset;
}
uint32_t cpu_ppc_load_tbl (CPUState *env)
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
- tb = cpu_ppc_get_tb(tb_env);
-#ifdef DEBUG_TB
- {
- static int last_time;
- int now;
- now = time(NULL);
- if (last_time != now) {
- last_time = now;
- printf("%s: tb=0x%016lx %d %08lx\n",
- __func__, tb, now, tb_env->tb_offset);
- }
+ tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
+#if defined(PPC_DEBUG_TB)
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
}
#endif
return tb & 0xFFFFFFFF;
}
-uint32_t cpu_ppc_load_tbu (CPUState *env)
+static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
- tb = cpu_ppc_get_tb(tb_env);
-#ifdef DEBUG_TB
- printf("%s: tb=0x%016lx\n", __func__, tb);
+ tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
+#if defined(PPC_DEBUG_TB)
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+ }
#endif
return tb >> 32;
}
-static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
+uint32_t cpu_ppc_load_tbu (CPUState *env)
+{
+ return _cpu_ppc_load_tbu(env);
+}
+
+static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk,
+ int64_t *tb_offsetp,
+ uint64_t value)
{
- tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
- - qemu_get_clock(vm_clock);
-#ifdef DEBUG_TB
- printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
+ *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec);
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value,
+ *tb_offsetp);
+ }
#endif
}
+void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+ uint64_t tb;
+
+ tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
+ tb &= 0xFFFFFFFF00000000ULL;
+ cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
+ &tb_env->tb_offset, tb | (uint64_t)value);
+}
+
+static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+ uint64_t tb;
+
+ tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
+ tb &= 0x00000000FFFFFFFFULL;
+ cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
+ &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
+}
+
void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
{
+ _cpu_ppc_store_tbu(env, value);
+}
+
+uint32_t cpu_ppc_load_atbl (CPUState *env)
+{
ppc_tb_t *tb_env = env->tb_env;
+ uint64_t tb;
- cpu_ppc_store_tb(tb_env,
- ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
+ tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
+#if defined(PPC_DEBUG_TB)
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+ }
+#endif
+
+ return tb & 0xFFFFFFFF;
}
-void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
+uint32_t cpu_ppc_load_atbu (CPUState *env)
{
ppc_tb_t *tb_env = env->tb_env;
+ uint64_t tb;
+
+ tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
+#if defined(PPC_DEBUG_TB)
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+ }
+#endif
- cpu_ppc_store_tb(tb_env,
- ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
+ return tb >> 32;
}
-uint32_t cpu_ppc_load_decr (CPUState *env)
+void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+ uint64_t tb;
+
+ tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
+ tb &= 0xFFFFFFFF00000000ULL;
+ cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
+ &tb_env->atb_offset, tb | (uint64_t)value);
+}
+
+void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+ uint64_t tb;
+
+ tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
+ tb &= 0x00000000FFFFFFFFULL;
+ cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
+ &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
+}
+
+static void cpu_ppc_tb_stop (CPUState *env)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+ uint64_t tb, atb, vmclk;
+
+ /* If the time base is already frozen, do nothing */
+ if (tb_env->tb_freq != 0) {
+ vmclk = qemu_get_clock(vm_clock);
+ /* Get the time base */
+ tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
+ /* Get the alternate time base */
+ atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
+ /* Store the time base value (ie compute the current offset) */
+ cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
+ /* Store the alternate time base value (compute the current offset) */
+ cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
+ /* Set the time base frequency to zero */
+ tb_env->tb_freq = 0;
+ /* Now, the time bases are frozen to tb_offset / atb_offset value */
+ }
+}
+
+static void cpu_ppc_tb_start (CPUState *env)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+ uint64_t tb, atb, vmclk;
+
+ /* If the time base is not frozen, do nothing */
+ if (tb_env->tb_freq == 0) {
+ vmclk = qemu_get_clock(vm_clock);
+ /* Get the time base from tb_offset */
+ tb = tb_env->tb_offset;
+ /* Get the alternate time base from atb_offset */
+ atb = tb_env->atb_offset;
+ /* Restore the tb frequency from the decrementer frequency */
+ tb_env->tb_freq = tb_env->decr_freq;
+ /* Store the time base value */
+ cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
+ /* Store the alternate time base value */
+ cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
+ }
+}
+
+static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,
+ uint64_t *next)
{
ppc_tb_t *tb_env = env->tb_env;
uint32_t decr;
diff = tb_env->decr_next - qemu_get_clock(vm_clock);
if (diff >= 0)
- decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
+ decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec);
else
- decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
-#if defined(DEBUG_TB)
- printf("%s: 0x%08x\n", __func__, decr);
+ decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec);
+#if defined(PPC_DEBUG_TB)
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
+ }
#endif
return decr;
}
+uint32_t cpu_ppc_load_decr (CPUState *env)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+
+ return _cpu_ppc_load_decr(env, &tb_env->decr_next);
+}
+
+#if defined(TARGET_PPC64H)
+uint32_t cpu_ppc_load_hdecr (CPUState *env)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+
+ return _cpu_ppc_load_decr(env, &tb_env->hdecr_next);
+}
+
+uint64_t cpu_ppc_load_purr (CPUState *env)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+ uint64_t diff;
+
+ diff = qemu_get_clock(vm_clock) - tb_env->purr_start;
+
+ return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
+}
+#endif /* defined(TARGET_PPC64H) */
+
/* When decrementer expires,
* all we need to do is generate or queue a CPU exception
*/
-static inline void cpu_ppc_decr_excp (CPUState *env)
+static always_inline void cpu_ppc_decr_excp (CPUState *env)
{
/* Raise it */
-#ifdef DEBUG_TB
- printf("raise decrementer exception\n");
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "raise decrementer exception\n");
+ }
#endif
ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
}
-static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
- uint32_t value, int is_excp)
+static always_inline void cpu_ppc_hdecr_excp (CPUState *env)
+{
+ /* Raise it */
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "raise decrementer exception\n");
+ }
+#endif
+ ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
+}
+
+static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
+ struct QEMUTimer *timer,
+ void (*raise_excp)(CPUState *),
+ uint32_t decr, uint32_t value,
+ int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t now, next;
-#ifdef DEBUG_TB
- printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
+ }
#endif
now = qemu_get_clock(vm_clock);
- next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
+ next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq);
if (is_excp)
- next += tb_env->decr_next - now;
+ next += *nextp - now;
if (next == now)
next++;
- tb_env->decr_next = next;
+ *nextp = next;
/* Adjust timer */
- qemu_mod_timer(tb_env->decr_timer, next);
+ qemu_mod_timer(timer, next);
/* If we set a negative value and the decrementer was positive,
* raise an exception.
*/
if ((value & 0x80000000) && !(decr & 0x80000000))
- cpu_ppc_decr_excp(env);
+ (*raise_excp)(env);
+}
+
+static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
+ uint32_t value, int is_excp)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+
+ __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer,
+ &cpu_ppc_decr_excp, decr, value, is_excp);
}
void cpu_ppc_store_decr (CPUState *env, uint32_t value)
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}
+#if defined(TARGET_PPC64H)
+static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
+ uint32_t value, int is_excp)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+
+ __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
+ &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
+}
+
+void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
+{
+ _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
+}
+
+static void cpu_ppc_hdecr_cb (void *opaque)
+{
+ _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);
+}
+
+void cpu_ppc_store_purr (CPUState *env, uint64_t value)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+
+ tb_env->purr_load = value;
+ tb_env->purr_start = qemu_get_clock(vm_clock);
+}
+#endif /* defined(TARGET_PPC64H) */
+
+static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
+{
+ CPUState *env = opaque;
+ ppc_tb_t *tb_env = env->tb_env;
+
+ tb_env->tb_freq = freq;
+ tb_env->decr_freq = freq;
+ /* There is a bug in Linux 2.4 kernels:
+ * if a decrementer exception is pending when it enables msr_ee at startup,
+ * it's not ready to handle it...
+ */
+ _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
+#if defined(TARGET_PPC64H)
+ _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
+ cpu_ppc_store_purr(env, 0x0000000000000000ULL);
+#endif /* defined(TARGET_PPC64H) */
+}
+
/* Set up (once) timebase frequency (in Hz) */
-ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq)
+clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
{
ppc_tb_t *tb_env;
if (tb_env == NULL)
return NULL;
env->tb_env = tb_env;
- if (tb_env->tb_freq == 0 || 1) {
- tb_env->tb_freq = freq;
- /* Create new timer */
- tb_env->decr_timer =
- qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
- /* There is a bug in Linux 2.4 kernels:
- * if a decrementer exception is pending when it enables msr_ee,
- * it's not ready to handle it...
- */
- _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
- }
-
- return tb_env;
+ /* Create new timer */
+ tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
+#if defined(TARGET_PPC64H)
+ tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
+#endif /* defined(TARGET_PPC64H) */
+ cpu_ppc_set_tb_clk(env, freq);
+
+ return &cpu_ppc_set_tb_clk;
}
/* Specific helpers for POWER & PowerPC 601 RTC */
-ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env)
+clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
{
return cpu_ppc_tb_init(env, 7812500);
}
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
-__attribute__ (( alias ("cpu_ppc_store_tbu") ));
+{
+ _cpu_ppc_store_tbu(env, value);
+}
uint32_t cpu_ppc601_load_rtcu (CPUState *env)
-__attribute__ (( alias ("cpu_ppc_load_tbu") ));
+{
+ return _cpu_ppc_load_tbu(env);
+}
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
{
uint64_t wdt_next; /* Tick for next WDT interrupt */
struct QEMUTimer *wdt_timer;
};
-
+
/* Fixed interval timer */
static void cpu_4xx_fit_cb (void *opaque)
{
if (next == now)
next++;
qemu_mod_timer(ppcemb_timer->fit_timer, next);
- tb_env->decr_next = next;
env->spr[SPR_40x_TSR] |= 1 << 26;
if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
- if (loglevel) {
- fprintf(logfile, "%s: ir %d TCR %08x TSR %08x\n", __func__,
- (env->spr[SPR_40x_TCR] >> 23) & 0x1,
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
+ (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
}
+#endif
}
/* Programmable interval timer */
-static void cpu_4xx_pit_cb (void *opaque)
+static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
{
- CPUState *env;
- ppc_tb_t *tb_env;
ppcemb_timer_t *ppcemb_timer;
uint64_t now, next;
- env = opaque;
- tb_env = env->tb_env;
ppcemb_timer = tb_env->opaque;
- now = qemu_get_clock(vm_clock);
- if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) {
- /* Auto reload */
+ if (ppcemb_timer->pit_reload <= 1 ||
+ !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
+ (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
+ /* Stop PIT */
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: stop PIT\n", __func__);
+ }
+#endif
+ qemu_del_timer(tb_env->decr_timer);
+ } else {
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: start PIT 0x" REGX "\n",
+ __func__, ppcemb_timer->pit_reload);
+ }
+#endif
+ now = qemu_get_clock(vm_clock);
next = now + muldiv64(ppcemb_timer->pit_reload,
- ticks_per_sec, tb_env->tb_freq);
+ ticks_per_sec, tb_env->decr_freq);
+ if (is_excp)
+ next += tb_env->decr_next - now;
if (next == now)
next++;
qemu_mod_timer(tb_env->decr_timer, next);
tb_env->decr_next = next;
}
+}
+
+static void cpu_4xx_pit_cb (void *opaque)
+{
+ CPUState *env;
+ ppc_tb_t *tb_env;
+ ppcemb_timer_t *ppcemb_timer;
+
+ env = opaque;
+ tb_env = env->tb_env;
+ ppcemb_timer = tb_env->opaque;
env->spr[SPR_40x_TSR] |= 1 << 27;
if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
- if (loglevel) {
- fprintf(logfile, "%s: ar %d ir %d TCR %08x TSR %08x %08lx\n", __func__,
- (env->spr[SPR_40x_TCR] >> 22) & 0x1,
- (env->spr[SPR_40x_TCR] >> 26) & 0x1,
+ start_stop_pit(env, tb_env, 1);
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
+ "%016" PRIx64 "\n", __func__,
+ (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
+ (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
ppcemb_timer->pit_reload);
}
+#endif
}
/* Watchdog timer */
/* Cannot occur, but makes gcc happy */
return;
}
- next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
+ next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq);
if (next == now)
next++;
- if (loglevel) {
- fprintf(logfile, "%s: TCR %08x TSR %08x\n", __func__,
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
}
+#endif
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
case 0x0:
case 0x1:
/* No reset */
break;
case 0x1: /* Core reset */
+ ppc40x_core_reset(env);
+ break;
case 0x2: /* Chip reset */
+ ppc40x_chip_reset(env);
+ break;
case 0x3: /* System reset */
- qemu_system_reset_request();
- return;
+ ppc40x_system_reset(env);
+ break;
}
}
}
{
ppc_tb_t *tb_env;
ppcemb_timer_t *ppcemb_timer;
- uint64_t now, next;
tb_env = env->tb_env;
ppcemb_timer = tb_env->opaque;
- if (loglevel)
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
- ppcemb_timer->pit_reload = val;
- if (val == 0) {
- /* Stop PIT */
- if (loglevel)
- fprintf(logfile, "%s: stop PIT\n", __func__);
- qemu_del_timer(tb_env->decr_timer);
- } else {
- if (loglevel)
- fprintf(logfile, "%s: start PIT 0x%08x\n", __func__, val);
- now = qemu_get_clock(vm_clock);
- next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq);
- if (next == now)
- next++;
- qemu_mod_timer(tb_env->decr_timer, next);
- tb_env->decr_next = next;
}
+#endif
+ ppcemb_timer->pit_reload = val;
+ start_stop_pit(env, tb_env, 0);
}
target_ulong load_40x_pit (CPUState *env)
void store_booke_tsr (CPUState *env, target_ulong val)
{
- env->spr[SPR_40x_TSR] = val & 0xFC000000;
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
+ }
+#endif
+ env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
+ if (val & 0x80000000)
+ ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
}
void store_booke_tcr (CPUState *env, target_ulong val)
{
- /* We don't update timers now. Maybe we should... */
- env->spr[SPR_40x_TCR] = val & 0xFF800000;
+ ppc_tb_t *tb_env;
+
+ tb_env = env->tb_env;
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
+ }
+#endif
+ env->spr[SPR_40x_TCR] = val & 0xFFC00000;
+ start_stop_pit(env, tb_env, 1);
+ cpu_4xx_wdt_cb(env);
+}
+
+static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
+{
+ CPUState *env = opaque;
+ ppc_tb_t *tb_env = env->tb_env;
+
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s set new frequency to %u\n", __func__, freq);
+ }
+#endif
+ tb_env->tb_freq = freq;
+ tb_env->decr_freq = freq;
+ /* XXX: we should also update all timers */
}
-void ppc_emb_timers_init (CPUState *env)
+clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
{
ppc_tb_t *tb_env;
ppcemb_timer_t *ppcemb_timer;
- tb_env = env->tb_env;
+ tb_env = qemu_mallocz(sizeof(ppc_tb_t));
+ if (tb_env == NULL) {
+ return NULL;
+ }
+ env->tb_env = tb_env;
ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
+ tb_env->tb_freq = freq;
+ tb_env->decr_freq = freq;
tb_env->opaque = ppcemb_timer;
- if (loglevel)
- fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
+#ifdef PPC_DEBUG_TB
+ if (loglevel != 0) {
+ fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer,
+ &ppc_emb_set_tb_clk);
+ }
+#endif
if (ppcemb_timer != NULL) {
/* We use decr timer for PIT */
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
ppcemb_timer->wdt_timer =
qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
}
+
+ return &ppc_emb_set_tb_clk;
}
/*****************************************************************************/
void *opaque;
};
+/* XXX: on 460, DCR addresses are 32 bits wide,
+ * using DCRIPR to get the 22 upper bits of the DCR address
+ */
#define DCRN_NB 1024
struct ppc_dcr_t {
ppc_dcrn_t dcrn[DCRN_NB];
return 0;
}
-
#if 0
/*****************************************************************************/
/* Handle system reset (for now, just stop emulation) */
projects / qemu / blobdiff