-/*
+/*
* Arm PrimeCell PL011 UART
*
* Copyright (c) 2006 CodeSourcery.
static void pl011_update(pl011_state *s)
{
uint32_t flags;
-
+
flags = s->int_level & s->int_enabled;
qemu_set_irq(s->irq, flags != 0);
}
}
}
-static int pl011_can_recieve(void *opaque)
+static int pl011_can_receive(void *opaque)
{
pl011_state *s = (pl011_state *)opaque;
return s->read_count < 1;
}
-static void pl011_recieve(void *opaque, const uint8_t *buf, int size)
+static void pl011_receive(void *opaque, const uint8_t *buf, int size)
{
pl011_state *s = (pl011_state *)opaque;
int slot;
s = (pl011_state *)qemu_mallocz(sizeof(pl011_state));
iomemtype = cpu_register_io_memory(0, pl011_readfn,
pl011_writefn, s);
- cpu_register_physical_memory(base, 0x00000fff, iomemtype);
+ cpu_register_physical_memory(base, 0x00001000, iomemtype);
s->base = base;
s->irq = irq;
s->chr = chr;
s->ifl = 0x12;
s->cr = 0x300;
s->flags = 0x90;
- if (chr){
- qemu_chr_add_handlers(chr, pl011_can_recieve, pl011_recieve,
+ if (chr){
+ qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
pl011_event, s);
}
/* ??? Save/restore. */