{
PCIIORegion *r;
- if ((unsigned int)region_num >= 6)
+ if ((unsigned int)region_num >= PCI_NUM_REGIONS)
return;
r = &pci_dev->io_regions[region_num];
r->addr = -1;
{
PCIIORegion *r;
int cmd, i;
- uint32_t last_addr, new_addr;
+ uint32_t last_addr, new_addr, config_ofs;
cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
- for(i = 0; i < 6; i++) {
+ for(i = 0; i < PCI_NUM_REGIONS; i++) {
r = &d->io_regions[i];
+ if (i == PCI_ROM_SLOT) {
+ config_ofs = 0x30;
+ } else {
+ config_ofs = 0x10 + i * 4;
+ }
if (r->size != 0) {
if (r->type & PCI_ADDRESS_SPACE_IO) {
if (cmd & PCI_COMMAND_IO) {
new_addr = le32_to_cpu(*(uint32_t *)(d->config +
- 0x10 + i * 4));
+ config_ofs));
new_addr = new_addr & ~(r->size - 1);
last_addr = new_addr + r->size - 1;
/* NOTE: we have only 64K ioports on PC */
} else {
if (cmd & PCI_COMMAND_MEMORY) {
new_addr = le32_to_cpu(*(uint32_t *)(d->config +
- 0x10 + i * 4));
+ config_ofs));
+ /* the ROM slot has a specific enable bit */
+ if (i == PCI_ROM_SLOT && !(new_addr & 1))
+ goto no_mem_map;
new_addr = new_addr & ~(r->size - 1);
last_addr = new_addr + r->size - 1;
/* NOTE: we do not support wrapping */
new_addr = -1;
}
} else {
+ no_mem_map:
new_addr = -1;
}
}
uint32_t address, uint32_t val, int len)
{
int can_write, i;
- uint32_t end;
+ uint32_t end, addr;
- if (len == 4 && (address >= 0x10 && address < 0x10 + 4 * 6)) {
+ if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
+ (address >= 0x30 && address < 0x34))) {
PCIIORegion *r;
int reg;
- reg = (address - 0x10) >> 2;
+ if ( address >= 0x30 ) {
+ reg = PCI_ROM_SLOT;
+ }else{
+ reg = (address - 0x10) >> 2;
+ }
r = &d->io_regions[reg];
if (r->size == 0)
goto default_config;
/* compute the stored value */
- val &= ~(r->size - 1);
- val |= r->type;
- *(uint32_t *)(d->config + 0x10 + reg * 4) = cpu_to_le32(val);
+ if (reg == PCI_ROM_SLOT) {
+ /* keep ROM enable bit */
+ val &= (~(r->size - 1)) | 1;
+ } else {
+ val &= ~(r->size - 1);
+ val |= r->type;
+ }
+ *(uint32_t *)(d->config + address) = cpu_to_le32(val);
pci_update_mappings(d);
return;
}
default_config:
/* not efficient, but simple */
+ addr = address;
for(i = 0; i < len; i++) {
/* default read/write accesses */
- switch(address) {
+ switch(d->config[0x0e]) {
case 0x00:
- case 0x01:
- case 0x02:
- case 0x03:
- case 0x08:
- case 0x09:
- case 0x0a:
- case 0x0b:
- case 0x0e:
- case 0x3d:
- can_write = 0;
+ case 0x80:
+ switch(addr) {
+ case 0x00:
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ case 0x08:
+ case 0x09:
+ case 0x0a:
+ case 0x0b:
+ case 0x0e:
+ case 0x10 ... 0x27: /* base */
+ case 0x30 ... 0x33: /* rom */
+ case 0x3d:
+ can_write = 0;
+ break;
+ default:
+ can_write = 1;
+ break;
+ }
break;
default:
- can_write = 1;
+ case 0x01:
+ switch(addr) {
+ case 0x00:
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ case 0x08:
+ case 0x09:
+ case 0x0a:
+ case 0x0b:
+ case 0x0e:
+ case 0x38 ... 0x3b: /* rom */
+ case 0x3d:
+ can_write = 0;
+ break;
+ default:
+ can_write = 1;
+ break;
+ }
break;
}
if (can_write) {
- d->config[address] = val;
+ d->config[addr] = val;
}
- address++;
+ addr++;
val >>= 8;
}
pci_dev = bus[(s->config_reg >> 8) & 0xff];
if (!pci_dev) {
fail:
- val = 0;
+ switch(len) {
+ case 1:
+ val = 0xff;
+ break;
+ case 2:
+ val = 0xffff;
+ break;
+ default:
+ case 4:
+ val = 0xffffffff;
+ break;
+ }
goto the_end;
}
config_addr = (s->config_reg & 0xfc) | (addr & 3);
d->config[0x02] = 0x37; // device_id
d->config[0x03] = 0x12;
d->config[0x08] = 0x02; // revision
- d->config[0x0a] = 0x04; // class_sub = pci2pci
+ d->config[0x0a] = 0x00; // class_sub = host2pci
d->config[0x0b] = 0x06; // class_base = PCI_bridge
- d->config[0x0c] = 0x01; // line_size in 32 bit words
- d->config[0x0e] = 0x01; // header_type
+ d->config[0x0e] = 0x00; // header_type
}
/* PIIX3 PCI to ISA bridge */
piix3_reset(d);
}
+/* PREP pci init */
+
+static inline void set_config(PCIBridge *s, target_phys_addr_t addr)
+{
+ int devfn, i;
+
+ for(i = 0; i < 11; i++) {
+ if ((addr & (1 << (11 + i))) != 0)
+ break;
+ }
+ devfn = ((addr >> 8) & 7) | (i << 3);
+ s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
+}
+
+static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ PCIBridge *s = opaque;
+ set_config(s, addr);
+ pci_data_write(s, addr, val, 1);
+}
+
+static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ PCIBridge *s = opaque;
+ set_config(s, addr);
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap16(val);
+#endif
+ pci_data_write(s, addr, val, 2);
+}
+
+static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ PCIBridge *s = opaque;
+ set_config(s, addr);
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap32(val);
+#endif
+ pci_data_write(s, addr, val, 4);
+}
+
+static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
+{
+ PCIBridge *s = opaque;
+ uint32_t val;
+ set_config(s, addr);
+ val = pci_data_read(s, addr, 1);
+ return val;
+}
+
+static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
+{
+ PCIBridge *s = opaque;
+ uint32_t val;
+ set_config(s, addr);
+ val = pci_data_read(s, addr, 2);
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap16(val);
+#endif
+ return val;
+}
+
+static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
+{
+ PCIBridge *s = opaque;
+ uint32_t val;
+ set_config(s, addr);
+ val = pci_data_read(s, addr, 4);
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap32(val);
+#endif
+ return val;
+}
+
+static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
+ &PPC_PCIIO_writeb,
+ &PPC_PCIIO_writew,
+ &PPC_PCIIO_writel,
+};
+
+static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
+ &PPC_PCIIO_readb,
+ &PPC_PCIIO_readw,
+ &PPC_PCIIO_readl,
+};
+
+void pci_prep_init(void)
+{
+ PCIBridge *s = &pci_bridge;
+ PCIDevice *d;
+ int PPC_io_memory;
+
+ PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
+ PPC_PCIIO_write, s);
+ cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
+
+ d = pci_register_device("PREP PCI Bridge", sizeof(PCIDevice), 0, 0,
+ NULL, NULL);
+
+ /* XXX: put correct IDs */
+ d->config[0x00] = 0x11; // vendor_id
+ d->config[0x01] = 0x10;
+ d->config[0x02] = 0x26; // device_id
+ d->config[0x03] = 0x00;
+ d->config[0x08] = 0x02; // revision
+ d->config[0x0a] = 0x04; // class_sub = pci2pci
+ d->config[0x0b] = 0x06; // class_base = PCI_bridge
+ d->config[0x0e] = 0x01; // header_type
+}
+
+
+/* pmac pci init */
+
+static void pci_pmac_config_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ PCIBridge *s = opaque;
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap32(val);
+#endif
+ s->config_reg = val;
+}
+
+static uint32_t pci_pmac_config_readl (void *opaque, target_phys_addr_t addr)
+{
+ PCIBridge *s = opaque;
+ uint32_t val;
+
+ val = s->config_reg;
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap32(val);
+#endif
+ return val;
+}
+
+static CPUWriteMemoryFunc *pci_pmac_config_write[] = {
+ &pci_pmac_config_writel,
+ &pci_pmac_config_writel,
+ &pci_pmac_config_writel,
+};
+
+static CPUReadMemoryFunc *pci_pmac_config_read[] = {
+ &pci_pmac_config_readl,
+ &pci_pmac_config_readl,
+ &pci_pmac_config_readl,
+};
+
+static void pci_pmac_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ PCIBridge *s = opaque;
+ pci_data_write(s, addr, val, 1);
+}
+
+static void pci_pmac_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ PCIBridge *s = opaque;
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap16(val);
+#endif
+ pci_data_write(s, addr, val, 2);
+}
+
+static void pci_pmac_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ PCIBridge *s = opaque;
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap32(val);
+#endif
+ pci_data_write(s, addr, val, 4);
+}
+
+static uint32_t pci_pmac_readb (void *opaque, target_phys_addr_t addr)
+{
+ PCIBridge *s = opaque;
+ uint32_t val;
+ val = pci_data_read(s, addr, 1);
+ return val;
+}
+
+static uint32_t pci_pmac_readw (void *opaque, target_phys_addr_t addr)
+{
+ PCIBridge *s = opaque;
+ uint32_t val;
+ val = pci_data_read(s, addr, 2);
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap16(val);
+#endif
+ return val;
+}
+
+static uint32_t pci_pmac_readl (void *opaque, target_phys_addr_t addr)
+{
+ PCIBridge *s = opaque;
+ uint32_t val;
+
+ val = pci_data_read(s, addr, 4);
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap32(val);
+#endif
+ return val;
+}
+
+static CPUWriteMemoryFunc *pci_pmac_write[] = {
+ &pci_pmac_writeb,
+ &pci_pmac_writew,
+ &pci_pmac_writel,
+};
+
+static CPUReadMemoryFunc *pci_pmac_read[] = {
+ &pci_pmac_readb,
+ &pci_pmac_readw,
+ &pci_pmac_readl,
+};
+
+void pci_pmac_init(void)
+{
+ PCIBridge *s = &pci_bridge;
+ PCIDevice *d;
+ int pci_mem_config, pci_mem_data;
+
+ pci_mem_config = cpu_register_io_memory(0, pci_pmac_config_read,
+ pci_pmac_config_write, s);
+ pci_mem_data = cpu_register_io_memory(0, pci_pmac_read, pci_pmac_write, s);
+
+ cpu_register_physical_memory(0xfec00000, 0x1000, pci_mem_config);
+ cpu_register_physical_memory(0xfee00000, 0x1000, pci_mem_data);
+
+ d = pci_register_device("MPC106", sizeof(PCIDevice), 0, 0,
+ NULL, NULL);
+
+ /* same values as PearPC - check this */
+ d->config[0x00] = 0x11; // vendor_id
+ d->config[0x01] = 0x10;
+ d->config[0x02] = 0x26; // device_id
+ d->config[0x03] = 0x00;
+ d->config[0x08] = 0x02; // revision
+ d->config[0x0a] = 0x04; // class_sub = pci2pci
+ d->config[0x0b] = 0x06; // class_base = PCI_bridge
+ d->config[0x0e] = 0x01; // header_type
+
+ d->config[0x18] = 0x0; // primary_bus
+ d->config[0x19] = 0x1; // secondary_bus
+ d->config[0x1a] = 0x1; // subordinate_bus
+ d->config[0x1c] = 0x10; // io_base
+ d->config[0x1d] = 0x20; // io_limit
+
+ d->config[0x20] = 0x80; // memory_base
+ d->config[0x21] = 0x80;
+ d->config[0x22] = 0x90; // memory_limit
+ d->config[0x23] = 0x80;
+
+ d->config[0x24] = 0x00; // prefetchable_memory_base
+ d->config[0x25] = 0x84;
+ d->config[0x26] = 0x00; // prefetchable_memory_limit
+ d->config[0x27] = 0x85;
+}
+
/***********************************************************/
/* generic PCI irq support */
}
/* 0 <= irq_num <= 3. level must be 0 or 1 */
+#ifdef TARGET_PPC
+void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
+{
+}
+#else
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
{
int irq_index, shift, pic_irq, pic_level;
pic_set_irq(pic_irq, pic_level);
}
}
+#endif
/***********************************************************/
/* monitor info on PCI */
if (d->config[PCI_INTERRUPT_PIN] != 0) {
printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
}
- for(i = 0;i < 6; i++) {
+ for(i = 0;i < PCI_NUM_REGIONS; i++) {
r = &d->io_regions[i];
if (r->size != 0) {
printf(" BAR%d: ", i);
{
PCIIORegion *r;
uint16_t cmd;
+ uint32_t ofs;
- pci_config_writel(d, 0x10 + region_num * 4, addr);
+ if ( region_num == PCI_ROM_SLOT ) {
+ ofs = 0x30;
+ }else{
+ ofs = 0x10 + region_num * 4;
+ }
+
+ pci_config_writel(d, ofs, addr);
r = &d->io_regions[region_num];
/* enable memory mappings */
cmd = pci_config_readw(d, PCI_COMMAND);
- if (r->type & PCI_ADDRESS_SPACE_IO)
+ if ( region_num == PCI_ROM_SLOT )
+ cmd |= 2;
+ else if (r->type & PCI_ADDRESS_SPACE_IO)
cmd |= 1;
else
cmd |= 2;
int class;
PCIIORegion *r;
uint32_t *paddr;
- int i, pin, pic_irq;
+ int i, pin, pic_irq, vendor_id, device_id;
- class = d->config[0x0a] | (d->config[0x0b] << 8);
+ class = pci_config_readw(d, PCI_CLASS_DEVICE);
+ vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
+ device_id = pci_config_readw(d, PCI_DEVICE_ID);
switch(class) {
case 0x0101:
- /* IDE: we map it as in ISA mode */
- pci_set_io_region_addr(d, 0, 0x1f0);
- pci_set_io_region_addr(d, 1, 0x3f4);
- pci_set_io_region_addr(d, 2, 0x170);
- pci_set_io_region_addr(d, 3, 0x374);
+ if (vendor_id == 0x8086 && device_id == 0x7010) {
+ /* PIIX3 IDE */
+ pci_config_writew(d, PCI_COMMAND, PCI_COMMAND_IO);
+ pci_config_writew(d, 0x40, 0x8000); // enable IDE0
+ } else {
+ /* IDE: we map it as in ISA mode */
+ pci_set_io_region_addr(d, 0, 0x1f0);
+ pci_set_io_region_addr(d, 1, 0x3f4);
+ pci_set_io_region_addr(d, 2, 0x170);
+ pci_set_io_region_addr(d, 3, 0x374);
+ }
break;
case 0x0300:
+ if (vendor_id != 0x1234)
+ goto default_map;
/* VGA: map frame buffer to default Bochs VBE address */
pci_set_io_region_addr(d, 0, 0xE0000000);
break;
+ case 0xff00:
+ if (vendor_id == 0x0106b && device_id == 0x0017) {
+ /* macio bridge */
+ pci_set_io_region_addr(d, 0, 0x80800000);
+ }
+ break;
default:
+ default_map:
/* default memory mappings */
- for(i = 0; i < 6; i++) {
+ for(i = 0; i < PCI_NUM_REGIONS; i++) {
r = &d->io_regions[i];
if (r->size) {
if (r->type & PCI_ADDRESS_SPACE_IO)
}
}
}
+
+/*
+ * This function initializes the PCI devices as a normal PCI BIOS
+ * would do. It is provided just in case the BIOS has no support for
+ * PCI.
+ */
+void pci_ppc_bios_init(void)
+{
+ PCIBridge *s = &pci_bridge;
+ PCIDevice **bus;
+ int bus_num, devfn, i, irq;
+ uint8_t elcr[2];
+
+ pci_bios_io_addr = 0xc000;
+ pci_bios_mem_addr = 0xc0000000;
+
+#if 0
+ /* activate IRQ mappings */
+ elcr[0] = 0x00;
+ elcr[1] = 0x00;
+ for(i = 0; i < 4; i++) {
+ irq = pci_irqs[i];
+ /* set to trigger level */
+ elcr[irq >> 3] |= (1 << (irq & 7));
+ /* activate irq remapping in PIIX */
+ pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
+ }
+ isa_outb(elcr[0], 0x4d0);
+ isa_outb(elcr[1], 0x4d1);
+#endif
+
+ for(bus_num = 0; bus_num < 256; bus_num++) {
+ bus = s->pci_bus[bus_num];
+ if (bus) {
+ for(devfn = 0; devfn < 256; devfn++) {
+ if (bus[devfn])
+ pci_bios_init_device(bus[devfn]);
+ }
+ }
+ }
+}
projects / qemu / blobdiff